Analog to Digital (A/D) Converter with Internal Diagnostic Circuit

Abstract

An analog to digital (A/D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S/H) output. The A/D converter also includes a voltage comparator having a first input coupled to the S/H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage. The A/D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.

Claims

1. An analog to digital (A/D) converter with an internal diagnostic circuit comprising: a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of first switches and having respective second terminals coupled to a sample and hold (S/H) output, wherein the S/H output is selectively coupled to a bias voltage via a second switch; a voltage comparator having a first input coupled to the S/H output and having a second input coupled to the bias voltage, the voltage comparator configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage; and a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.

2. The A/D converter of claim 1, wherein the capacitor array comprises a plurality of switched binary-weighted capacitors.

3. The A/D converter of claim 2, wherein the sampled charge at the S/H output is controlled by varying the number of switched binary-weighted capacitors connected to the reference voltage.

4. The A/D converter of claim 3, wherein the equivalent capacitance is increased by increasing the number of switched binary-weighted capacitors interconnected in parallel, and wherein the equivalent capacitance of the capacitor array is decreased by reducing the number of switched binary-weighted capacitors interconnected in parallel.

5. The A/D converter of claim 1, wherein the approximate digital code is a digital representation of the S/H voltage.

6. The A/D converter of claim 1, wherein the S/H output is coupled to the bias voltage via the second switch during a sample phase and is de-coupled from the bias voltage during a hold phase.

7. The A/D converter of claim 1, wherein during the sample phase both the first and second inputs of the voltage comparator are coupled to the bias voltage, and wherein during the hold phase the second input of the voltage comparator is coupled to the bias voltage and the first input of the voltage comparator is not coupled to the bias voltage.

8. The A/D converter of claim 1, wherein during the hold phase the first input of the voltage comparator is coupled to the S/H output and the second input of the voltage comparator is coupled to the bias voltage.

9. The A/D converter of claim 1, wherein a fault bit is diagnosed if at least one bit of the approximate digital code fails to toggle when the ratio is varied.

10. The A/D converter of claim 1, wherein the reference voltage is generated inside an integrated circuit.

11. An analog to digital (A/D) converter with an internal diagnostic circuit comprising: a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of first switches and having respective second terminals coupled to a sample and hold (S/H) output, wherein the S/H output is selectively coupled to a bias voltage via a second switch during a sample phase and is de-coupled from the bias voltage via the second switch during a hold phase; a voltage comparator having a first input coupled to the S/H output and having a second input coupled to the bias voltage, the voltage comparator configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage; and a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein during the sample phase both the first and second inputs of the voltage comparator are coupled to the bias voltage, and wherein during the hold phase the second input of the voltage comparator is coupled to the bias voltage and the first input of the voltage comparator is not coupled to the bias voltage.

12. The A/D converter of claim 11, wherein the capacitor array comprises a plurality of switched binary-weighted capacitors.

13. The A/D converter of claim 12, wherein the sampled charge at the S/H output is controlled by varying the number of switched binary-weighted capacitors connected to the reference voltage.

14. The A/D converter of claim 11, wherein an equivalent capacitance of the capacitor array is controlled by varying the number of switched binary-weighted capacitors connected in parallel.

15. The A/D converter of claim 14, wherein the equivalent capacitance of the capacitor array is increased by increasing the number of switched binary-weighted capacitors interconnected in parallel, and wherein the equivalent capacitance of the capacitor array is decreased by reducing the number of switched binary-weighted capacitors interconnected in parallel.

16. The A/D converter of claim 11, wherein the approximate digital code is a digital representation of the S/H voltage.

17. The A/D converter of claim 11, wherein a fault bit is diagnosed if at least one bit of the approximate digital code fails to toggle independent of adjacent bits when the ratio is varied.

18. The A/D converter of claim 11, wherein the reference voltage is generated inside an integrated circuit.

19. An analog to digital (A/D) converter with an internal diagnostic circuit comprising: a capacitor array comprising a plurality of switched binary-weighted capacitors having respective first terminals selectively coupled to a reference voltage or ground via a plurality of first switches and having respective second terminals coupled to a sample and hold (S/H) output, wherein the S/H output is selectively coupled to a bias voltage via a second switch; a voltage comparator having a first input coupled to the S/H output and having a second input coupled to the bias voltage, the voltage comparator configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage; and a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein during a sample phase the second switch couples the S/H output to the bias voltage and during a hold phase the second switch decouples the S/H output from the bias voltage, and wherein during the sample phase both the first and second inputs of the voltage comparator are coupled to the bias voltage, and wherein during the hold phase the second input of the voltage comparator is coupled to the bias voltage and the first input of the voltage comparator is not coupled to the bias voltage.

20. The A/D converter of claim 19, wherein an equivalent capacitance of the capacitor array is controlled by varying the number of switched binary-weighted capacitors connected in parallel.

21. The A/D converter of claim 20, wherein the equivalent capacitance of the capacitor array is increased by increasing the number of switched binary-weighted capacitors interconnected in parallel, and wherein the equivalent capacitance of the capacitor array is decreased by reducing the number of switched binary-weighted capacitors interconnected in parallel.

22. The A/D converter of claim 19, wherein the approximate digital code is a digital representation of the S/H voltage.

23. The A/D converter of claim 19, wherein a fault bit is diagnosed if at least one bit of the approximate digital code fails to toggle independent of adjacent bits when the ratio is varied.

24. The A/D converter of claim 19, wherein the successive approximation register applies a binary search algorithm to output the approximate digital code.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 shows an external test circuit used to test an A/D converter.

[0016] FIG. 2 is an A/D converter in accordance with an exemplary embodiment.

[0017] FIG. 3 illustrates an equivalent circuit.

[0018] FIG. 4 is a plot of a voltage sampled by a comparator.

DETAILED DESCRIPTION

[0019] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, in which some, but not all embodiments are shown. Indeed, the concepts may be embodied in many different forms and should not be construed as limiting herein. Rather, these descriptions are provided so that this disclosure will satisfy applicable requirements.

[0020] FIG. 2 is a schematic of an analog to digital (A/D) converter 200 in accordance with an exemplary embodiment. The A/D converter 200 includes an internal diagnostic circuit 204 which provides a controlled voltage source that is used to test output bits of the A/D converter 200, thus eliminating a need for an external test circuit. The A/D converter 200 can be implemented in an integrated circuit (IC) and can be used in safety/critical applications where high availability is desired.

[0021] With reference to FIG. 2, the A/D converter 200 includes a capacitor array 204 which includes a plurality of capacitors having respective first terminals 206 and second terminals 208. In an exemplary embodiment, the capacitor array 204 is formed with a plurality of switched binary-weighted capacitors (e.g., C, C/2. C/4, . . . ). The A/D converter 200 also includes first switches S0-SN-1 configured to selectively couple the first terminals 206 of the capacitor array 204 to a reference voltage Vref or ground. The second terminals 208 of the capacitor array 204 are coupled to a sample and hold (S/H) output 212. The A/D converter 206 also includes a second switch S2 configured to selectively couple the S/H output 212 to a bias voltage Vbias. During other modes of operation of the A/D converter 200, the first terminals 206 of the capacitor array 204 are connected to an input voltage Vin.

[0022] With continuing reference to FIG. 2, the A/D converter 200 also includes a voltage comparator 230 having a first input 232 coupled to the S/H output 212 and a second input 234 coupled to the bias voltage Vbias. The voltage comparator 230 is configured to output a comparison voltage responsive to a sampled charge at the S/H output 212 and the bias voltage Vbias.

[0023] In an exemplary embodiment, the sampled charge at the S/H output 212 can be varied by the number of switched binary-weighted capacitors coupled to the reference voltage Vref. Some or all of the binary weighted capacitors' first terminals 206 can be connected to the reference voltage Vref, and some or all of the binary weighted capacitors' first terminals 206 can be connected to ground.

[0024] With continuing reference to FIG. 2, the A/D converter 200 also includes a successive approximation register (SAR) 240 having an input 242 coupled to receive the comparison voltage. The SAR 240 is configured to generate an approximate digital code responsive to the comparison voltage at an output 244. The approximate digital code is a digital representation of the S/H voltage at the S/H output 212. The approximate digital code is varied by controlling an equivalent capacitance of the capacitor array 204. In an exemplary embodiment, the SAR 240 applies a binary search algorithm to output the approximate digital code

[0025] With continuing reference to FIG. 2, the equivalent capacitance of the capacitor array 204 can be controlled by varying the number of binary-weighted capacitors interconnected in parallel. By increasing the number of binary-weighted capacitors interconnected in parallel, the equivalent capacitance of the capacitor array 204 is increased, and by reducing the number of binary-weighted capacitors interconnected in parallel, the equivalent capacitance of the capacitor array 204 is decreased.

[0026] With continuing reference to FIG. 2, during a sample phase, the first terminals 206 of the capacitor array 204 are selectively connected by closing the first switches, S0-SN-1, to either the reference voltage Vref or ground. Also, during the sample phase, the second switch S2 is closed to couple the S/H output 212 to the bias voltage Vbias. Thus, during the sample phase both the first and second inputs 232, 234 of the voltage comparator 230 are coupled to the bias voltage Vbias. The capacitor array 204 is charged by the reference voltage Vref and has a charge equal to the capacitance multiplied by the reference voltage Vref. The sampled charge created is equal to (Vref)(Cn), where Cn are switched-binary-weighted capacitors connected to Vref.

[0027] Next, during a hold (or conversion) phase, the second switch S2 is opened to de-couple the S/H output 212 from the bias voltage Vbias. As a consequence, during the hold (conversion phase), although the first input 232 of the voltage comparator 230 is de-coupled from the bias voltage Vbias, the first input 232 of the voltage comparator 230 remains coupled to the S/H output 212 and the second input 234 of the voltage comparator 230 remains coupled to the bias voltage Vbias. The voltage comparator 230 outputs the comparison voltage responsive to the sampled charge at the S/H output 212 and the bias voltage Vbias. The comparison voltage is applied to the input 242 of the SAR 240. The SAR 240 applies a binary search algorithm to the comparison voltage and outputs the approximate digital code which is a digital representation of the S/H voltage. The SAR 240 can be realized in hardware or software.

[0028] FIG. 3 illustrates a simplified equivalent circuit 300 during the hold (or conversion) phase. The first input 232 of the voltage comparator 230 is de-coupled from the bias voltage Vbias. However, the first input 232 of the voltage comparator 230 remains coupled to the S/H output 212 and the second input 234 remains coupled to the bias voltage Vbias. A capacitor array 304 comprising a plurality of switched binary-weighted capacitors are coupled to the reference voltage Vref. The sampled charge at the S/H output 212 is controlled by varying the number of switched binary-weighted capacitors in the capacitor array. A selected number of capacitors 308 are coupled to ground. Although the reference voltage Vref, which is internally available inside the integrated circuit, has a constant voltage level, the sampled charge at the S/H output 212 is scaled by varying the equivalent capacitance of the capacitor array.

[0029] FIG. 4 illustrates the voltage sampled by the comparator 230. By using a user specified code, the sampled charge at the S/H output 212 is varied to a maximum value of (Vref)(Cn). The sampled charge at the S/H output 212 is varied to test the approximate digital code produced by the SAR 240. As the sampled charge at the S/H output 212 is varied using the user specified code, if at least one of the bits of the approximate digital code fails to toggle independent of adjacent bits, a determination is made that the A/D converter 200 has at least one fault bit, which may render the A/D converter 200 unsuitable for safety/critical applications where high availability is desired.

[0030] Various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. The described functionality may be implemented in varying ways for each particular application, but such implementation decision should not be interpreted as causing a departure from the scope of the present disclosure.

[0031] For simplicity and clarity, the full structure and operation of all systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a system as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described.