CRYSTAL-FREE OSCILLATOR FOR CHANNEL-BASED HIGH-FREQUENCY RADIO COMMUNICATION

Abstract

The present invention relates to a crystal-free oscillator circuit (100) for channel-based high-frequency radio communication, the crystal-free oscillator circuit (100) comprising a crystal-free oscillator element (120) configured to provide a high-frequency reference signal (101), the high-frequency reference signal (101) having a frequency of at least about 1 GHz, and a phase-locked loop (PLL) circuit (110) having a feedback loop and comprising a PLL oscillator (120), wherein the phase-locked loop circuit (110) is configured to receive a high-frequency reference signal (101), to provide a feedback signal (102) in the feedback loop, and to provide a high-frequency output signal (103), the high-frequency output signal (103) being generated by the PLL oscillator (120) in response to the high-frequency reference signal (101) and to the feedback signal (102) where the feedback signal (102) is dependent on an earlier instance of the output signal (103), wherein the crystal-free oscillator circuit (100) further comprises an adjustable frequency offset circuit (210) located in the feedback loop, the adjustable frequency offset circuit (210) comprising a frequency generator (200) and being configured to offset a frequency of the feedback signal (102) in response to an adjustment control signal (104), and wherein the crystal-free oscillator circuit (100) is configured to compensate for a temperature dependency of the crystal-free oscillator circuit (100) in response to a measured current operating temperature.

Claims

1. A crystal-free oscillator circuit for channel-based high-frequency radio communication, the crystal-free oscillator circuit comprising a crystal-free oscillator element configured to provide a high-frequency reference signal, the high-frequency reference signal having a frequency of at least about 1 GHz, and a phase-locked loop (PLL) circuit having a feedback loop and comprising a PLL oscillator, wherein the phase-locked loop circuit (110) is configured to receive the high-frequency reference signal, to provide a feedback signal in the feedback loop, and to provide a high-frequency output signal, the high-frequency output signal being generated by the PLL oscillator in response to the high-frequency reference signal and to the feedback signal where the feedback signal is dependent on an earlier instance of the high-frequency output signal, wherein the crystal-free oscillator circuit further comprises an adjustable frequency offset circuit located in the feedback loop, the adjustable frequency offset circuit comprising a frequency generator and being configured to offset a frequency of the feedback signal in response to an adjustment control signal, and wherein the crystal-free oscillator circuit is configured to compensate for a temperature dependency of the crystal-free oscillator circuit in response to a measured current operating temperature.

2. The crystal-free oscillator circuit according to claim 1, wherein the adjustment control signal represents or comprises a frequency offset value to apply to offset the frequency of the feedback signal.

3. The crystal-free oscillator circuit according to claim 1, wherein the adjustment control signal is provided in response to an obtained or received temperature signal representing a current operating temperature of at least a part of the crystal-free oscillator circuit, and a predetermined relationship or function between operating temperatures of the at least a part of the crystal-free oscillator circuit and predetermined respective associated frequency offset values.

4. The crystal-free oscillator circuit according to claim 3, wherein the predetermined relationship or function has been determined for the particular crystal-free oscillator circuit.

5. The crystal-free oscillator circuit according to claim 3, wherein the crystal-free oscillator circuit comprises a temperature sensor circuit or element configured to measure a current temperature of the at least a part of the crystal-free oscillator circuit and to provide the temperature signal in response thereto.

6. The crystal-free oscillator circuit according to claim 3, wherein the crystal-free oscillator circuit is a solid-state integrated circuit or a part thereof that further comprises a controllable heating element and a frequency counter, wherein the solid-state integrated circuit is configured to determine the predetermined relationship or function between operating temperatures and respective associated frequency values for a particular crystal-free oscillator circuit by incrementally or continuously increasing a temperature of at least a part of the crystal-free oscillator circuit using the heating element and obtaining a number of temperature values and associated frequency values, obtained by a frequency counter at respective temperature values, or a number of temperature values and associated frequency offset values derived from frequency target values and associated frequency values, obtained by the frequency counter at respective temperature values.

7. The crystal-free oscillator circuit according to claim 6, wherein the controllable heating element is a resistor circuit or element generating heat in response to being provided with an electrical current.

8. The crystal-free oscillator circuit according to claim 1, wherein the crystal-free oscillator circuit further comprises a first static frequency divider located in the feedback loop and being configured to divide down a frequency of the feedback signal by a factor being a first predetermined positive integer (N).

9. The crystal-free oscillator circuit according to claim 1, wherein the crystal-free oscillator circuit further comprises a second static frequency divider located in the feedback loop and being configured to divide down a frequency of the feedback signal by a factor being a second predetermined positive integer (M), and wherein the adjustable frequency offset circuit is configured to offset the frequency of the feedback signal after being divided down by the second static frequency divider.

10. The crystal-free oscillator circuit according to claim 9, wherein the frequency generator and the second static frequency divider each provide a first and a second output, and the adjustable frequency offset circuit comprises a first mixer or modulator, a second mixer or modulator, and an adding element, wherein the adjustable frequency offset circuit is configured to mix or modulate, by the first mixer or modulator, the first output from the frequency generator and the first output of the second frequency divider resulting in a first mixed or modulated signal, to mix or modulate, by the second mixer or modulator, the second output from the frequency generator and the second output of the second frequency divider resulting in a second mixed or modulated signal, and to add, by the adding element, the first and the second mixed or modulated signals and supply the resulting signal as output of the adjustable frequency offset circuit.

11. The crystal-free oscillator circuit according to claim 1, wherein the crystal-free oscillator circuit further comprises a phase frequency detector (PED) being configured to receive the high-frequency reference signal and the feedback signal and to derive at least one phase error signal in response thereto, and a low-pass filter (LPF) being configured to low-pass filter the at least one phase error signal and to derive an oscillator input signal in response thereto, wherein the PLL oscillator element or circuit is configured to derive the high-frequency output signal in response to the oscillator input signal.

12. The crystal-free oscillator circuit according to claim 1, wherein the crystal-free oscillator element is an LC-based oscillator.

13. The crystal-free oscillator circuit according to claim 12, wherein the LC-based oscillator (LCO) comprises a fixed inductor part and a controllable and variable capacitor part (805), wherein the controllable and variable capacitor part comprises at least one fixed or base capacitor and one or more of: a group of switchable capacitors, controlled in response to a first tuning control signal, and at least one voltage controlled capacitor, controlled in response to a second tuning control signal, wherein the LC-based oscillator (LCO) is configured to be temperature compensated by adjusting an output frequency of the LC-based oscillator (120) in according with the first tuning control signal and/or the second tuning control signal provided in response to a temperature sensor signal provided by a temperature sensor located in the vicinity of the LC-based oscillator (LCO).

14. The crystal-free oscillator circuit according to claim 1, wherein the high-frequency reference signal has a frequency of about 2 GHz, or of about 2 GHz or more.

15. The crystal-free oscillator circuit according to claim 1, wherein the crystal-free oscillator circuit is implemented as a monolithic integrated circuit.

16. The crystal-free oscillator circuit according to claim 1, wherein the output signal is provided to a channel-based radio communication element or system comprising a Bluetooth or Bluetooth Low Energy communication element or system.

17. A channel-based radio communication device or system comprising a crystal-free oscillator circuit according to claim 1.

18. A method of deriving a unique temperature and frequency profile for a particular crystal-free oscillator circuit, e.g. according to claim 1, the method comprising: determining a relationship or function between operating temperatures and respective associated frequency values of a feedback signal or a reference signal or a high-frequency output signal of the particular crystal-free oscillator circuit by incrementally or continuously increasing a temperature of at least a part of the particular crystal-free oscillator circuit using a heating element, and obtaining, and storing in a memory and/or storage 640, a number of temperature values and associated frequency values, obtained by a frequency counter at respective temperature values, or temperature values and associated frequency offset values derived from frequency target values and associated frequency values, obtained by the frequency counter at respective temperature values.

19. The method according to claim 18, wherein the steps are repeated for a number of different particular crystal-free oscillator circuits being part of a same wafer.

20. A medical device comprising a crystal-free oscillator circuit according to claim 1.

21. The medical device according to claim 20, wherein the medical device is a liquid drug delivery device, e.g. an injection device for delivering set doses of a liquid drug, comprising a housing storing, in use, a cartridge having a distal end being closed by a septum and a proximal end being closed by a movable plunger defining an interior containing the liquid drug, and a needle cannula having a distal end with a tip and a proximal end, which proximal end is in liquid communication with the interior of the cartridge when the needle cannula and the cartridge is mounted in the liquid drug delivery device.

22. A medical device according to claim 20, wherein the medical device or the channel-based radio communication device or system is a disposable and/or a time-limited use product.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0083] FIG. 1 schematically illustrates one exemplary embodiment of crystal-free oscillator circuit for channel-based high-frequency radio communication;

[0084] FIG. 2 schematically illustrates another exemplary embodiment of crystal-free oscillator circuit for channel-based high-frequency radio communication;

[0085] FIG. 3 schematically illustrates yet another exemplary embodiment of crystal-free oscillator circuit for channel-based high-frequency radio communication;

[0086] FIG. 4 schematically illustrates another exemplary embodiment of crystal-free oscillator circuit for channel-based high-frequency radio communication;

[0087] FIG. 5 schematically illustrates a further exemplary embodiment of crystal-free oscillator circuit for channel-based high-frequency radio communication;

[0088] FIG. 6 schematically illustrates an integrated circuit comprising an embodiment of a crystal-free oscillator circuit for channel-based high-frequency radio communication as disclosed herein together with additional elements;

[0089] FIG. 7 schematically illustrates one embodiment of a method of generating pairs of temperature and frequency values for a specific crystal-free oscillator circuit;

[0090] FIG. 8 schematically illustrates a device, and in particular a liquid drug delivery device, comprising a crystal-free oscillator circuit for channel-based high-frequency radio communication as disclosed herein;

[0091] FIG. 9 schematically illustrates an exemplary embodiment of a crystal-free oscillator element according to various embodiments; and

[0092] FIG. 10 schematically illustrates further details of the crystal-free oscillator element of FIG. 9 together with additional elements.

DETAILED DESCRIPTION

[0093] Various aspects and embodiments of a crystal-free oscillator circuit for channel-based high-frequency radio communication, a channel-based high-frequency radio communication device or system, a medical device comprising a crystal-free oscillator circuit for channel-based high-frequency radio communication, and a method of deriving a unique temperature and frequency adjustment profile or similar for a particular crystal-free oscillator circuit, as disclosed herein will now be described with reference to the figures.

[0094] When/if relative expressions such as upper and lower, right and left, horizontal and vertical, clockwise and counter clockwise or similar are used in the following terms, these only refer to the appended figures and not to an actual situation of use. The shown figures are schematic representations for which reason the configuration of the different structures as well as their relative dimensions are intended to serve illustrative purposes only.

[0095] In the context of the medical device, it may be convenient to define that the term distal end in the relevant appended figure is meant to refer to the end of the medical device which usually carries an injection needle and as depicted e.g. in FIG. 8 whereas the term proximal end is meant to refer to the opposite end pointing away from the injection needle.

[0096] Some of the different components are only disclosed in relation to a single embodiment of the invention, but is meant to be included in the other embodiments without further explanation.

[0097] FIG. 1 schematically illustrates one exemplary embodiment of crystal-free oscillator for channel-based high-frequency radio communication.

[0098] Illustrated is an exemplary embodiment of a crystal-free oscillator circuit 100 for channel-based high-frequency radio communication as disclosed herein, where the crystal-free oscillator circuit 100 comprises a crystal-free oscillator element 120 configured to provide a high-frequency reference signal (where the high-frequency reference signal has a frequency of at least about 1 GHz or at least about 2 GHz) and a phase-locked loop (PLL) circuit 110 having a feedback loop and comprising a PLL oscillator 120 as disclosed herein. The PLL circuit 110 is configured to receive the high-frequency reference signal 101 and to provide or generate a feedback signal 102 in/to the feedback loop. It is noted that the feedback signal 102 is to designate the signal in the whole feedback loop even though, the feedback signal will be modified, processed, changed, etc. by various elements as disclosed herein. The PLL circuit 110 is furthermore configured to provide or generate a high-frequency output signal 103 in response to the high-frequency reference signal 101 and the feedback signal 102 where the feedback signal 102 is dependent on an earlier instance of the output signal 103. The crystal-free oscillator element 120 is, at least in some embodiments, an LC-based oscillator.

[0099] In some embodiments, and as shown, the crystal-free oscillator circuit 100 further comprises a phase frequency detector (PFD) 150 receiving the high-frequency reference signal 101 and the feedback signal 102, where the PFD 150 is configured to derive at least one phase error signal 151, 152 in response to the received reference and feedback signals 101, 102. The crystal-free oscillator circuit 100 additionally comprises a low-pass filter (LPF) 155 configured to low-pass filter the at least one phase error signal 151, 152 and to derive an oscillator input signal 160 in response thereto, where the oscillator input signal 160 is provided to the PLL oscillator 120 to derive or generate the output signal 103, which is the output of the PLL circuit 110 and is also used in the feedback loop.

[0100] As disclosed herein, the crystal-free oscillator circuit 100 further comprises (in this and corresponding embodiments) an adjustable frequency offset circuit 210, as disclosed herein, comprising a frequency generator (not shown see e.g. 200 in FIGS. 2 and 3), where the adjustable frequency offset circuit 210 is configured to offset a frequency of the feedback signal 102 in response to an adjustment control signal 104, wherein the adjustable frequency offset circuit 210 is located in the feedback loop. The frequency generator is configured to generate a periodic signal having a frequency set under the control of the adjustable frequency offset circuit 210 and e.g. in particular set in dependency of the adjustment control signal 104. The precise location of the adjustable frequency offset circuit 210 may vary according to various embodiments (see e.g. FIGS. 2-4 for other exemplary locations/layouts). What is significant is that the adjustable frequency offset circuit 210 causes, as disclosed herein, an offset of the frequency of the feedback signal 102 before ultimately being used by the PLL oscillator element 120. The adjustment control signal 104 may be external (to the adjustable frequency offset circuit 210 as shown) or be generated internally (then requiring a more advanced adjustable frequency offset circuit 210). The crystal-free oscillator circuit 100 is additionally configured to compensate for a temperature dependency of the crystal-free oscillator circuit 100 where the compensation is done in response to a measured current operating temperature. This temperature dependency compensation is in some embodiments done by adjusting signals or other aspects of the crystal-free oscillator element 120 e.g. as disclosed herein. Alternatively, the temperature dependency compensation is done by the adjustable frequency offset circuit 210, whereby the needed temperature compensation data is or may be included as part of the adjustment control signal 104.

[0101] At least in some embodiments, the adjustment control signal 104 represents or comprises a frequency offset value (may be both positive and negative) used to offset the frequency of the feedback signal 102 when applied. The adjustment control signal 104 may in addition represent or comprise communication channel parameters and/or a modulation function or data. The adjustment control signal 104 may in some other embodiments be different as disclosed herein.

[0102] In some embodiments, the frequency generator 200 comprises or is a direct digital synthesizer (DDS) element or circuit (also sometimes referred to as a numerical control oscillator (NCO)) or similar providing the frequency to offset the feedback signal. A DDS is a type of frequency synthesizer that generally can create periodical functions with arbitrary frequencies.

[0103] In some embodiments, and as shown, the crystal-free oscillator circuit 100 comprises a first static frequency divider 130 configured to divide down a frequency of the feedback signal 102 by a factor being a first predetermined positive integer N. N may e.g. be 2 or 4 or any other suitable integer according to a specific implementation (e.g. taking power consumption into account) of the crystal-free oscillator circuit 100. By not dividing down by (too) large integers it is ensured that the phase noise is not increased (too much). It is also relatively simple to obtain appropriate quadrature signals from a 2 or 4 divider.

[0104] In the shown embodiment, the first frequency divider 130 is located in the feedback loop after the adjustable frequency offset circuit 210 (or at least after the adjustable frequency offset circuit 210 has offset the frequency of the feedback signal 102 as disclosed herein). Alternatively (see e.g. FIG. 4), the first frequency divider 130 (then designated a second frequency divider (M) 131) is located in the feedback loop before the adjustable frequency offset circuit 210 (or at least before the adjustable frequency offset circuit 210 has offset the frequency of the feedback signal 102 as disclosed herein).

[0105] The resulting frequency offset feedback signal 102 is then divided down by the first frequency divider 130 (if present) and the resulting signal is provided as input to the PFD 150 together with the high-frequency reference signal 101.

[0106] In the shown and corresponding embodiments, the frequencies of the crystal-free oscillator circuit 100/the PLL circuit 110 may be seen as being governed according to:

[00001]$f_{\mathrm{ref}}=\frac{1}{N}.Math.\left(f_{v.Math.c.Math.o}{f}_{\mathrm{DDS}}\right).Math.f_0=f_{\mathrm{vco}}=N.Math.\left(f_{\mathrm{ref}}{f}_{\mathrm{DDS}}\right)$

where f.sub.ref is the frequency of the high-frequency reference signal 101, f.sub.vco is the frequency of the PLL oscillator 120, f.sub.0 is the frequency of the high-frequency output signal 103, f.sub.DDS is the frequency offset value offsetting the frequency of the input of the PLL circuit (by the adjustable frequency offset circuit 210, e.g. comprising a frequency generator such as a DDS, offsetting the feedback signal as disclosed herein), and N is the integer value of the first frequency divider 130, each at each time instance.

[0107] In the shown and corresponding embodiments, the high-frequency output signal 103 is provided to an amplifier 166 e.g. acting as a power amplifier for an antenna of a channel-based high-frequency radio communication system or device.

[0108] In some embodiments, the crystal-free oscillator circuit 100 further comprises a second (static) frequency divider being located in the feedback loop and being configured to divide down the frequency of the feedback signal 102 by a factor being a second predetermined positive integer M (see e.g. 131 in FIGS. 2 and 3) and/or a third frequency divider being located between the crystal-free oscillator element and the PLL circuit and being configured to divide down a frequency of an output signal of the crystal-free oscillator element by a factor being a third predetermined positive integer (R) to generate the high-frequency reference signal (in addition, at least in some embodiments, to a first frequency divider 130 dividing down by N).

[0109] FIG. 2 schematically illustrates another exemplary embodiment of crystal-free oscillator for channel-based high-frequency radio communication.

[0110] Illustrated is an exemplary embodiment of a crystal-free oscillator circuit 100 for channel-based high-frequency radio communication as disclosed herein, where the crystal-free oscillator circuit 100 corresponds to the one shown and explained in connection with FIG. 1 except as noted in the following.

[0111] In this and corresponding embodiments, the crystal-free oscillator circuit 100 comprises a second static frequency divider 131 (in addition, at least in some embodiments, to a first frequency divider 130 dividing down by N or in some alternative embodiments instead) being located in the feedback loop and being configured to divide down the frequency of the feedback signal 102 by a factor being a second predetermined positive integer M. The adjustable frequency offset circuit 210 is configured to offset the frequency of the feedback signal 102 after being divided down M times by the second frequency divider 131 and before being divided down by first frequency divider 130 (for embodiments comprising such a first frequency divider). Dividing down the frequency before offsetting the frequency of the feedback signal reduces power consumption since the adjustable frequency offset circuit accordingly operates at a lower frequency (being the divided down frequency). M may e.g. be 2 or 4 or any other suitable integer according to a specific implementation of the crystal-free oscillator circuit 100. For embodiments also comprising a first frequency divider, both M and N may each e.g. be 2. Alternatively, N may be 2 and M may be 4. In the shown and corresponding embodiments, the adjustable frequency offset circuit 210 comprises the second frequency divider 131.

[0112] More specifically, the frequency generator 200 (of the adjustable frequency offset circuit 210) signal is mixed or modulated with the feedback signal 102 (after being divided down M times) by mixer or modulator 135 thereby offsetting the frequency of the feedback signal 102 as disclosed herein and e.g. carrying out further processing. It is noted that the feedback signal 102 as received by the adjustable frequency offset circuit 210, or more specifically the second frequency divider (M) 131, corresponds to the high-frequency output signal 103 generated by the PLL oscillator 120.

[0113] The resulting frequency offset feedback signal 102 (here being a processed signal based on the high-frequency output signal 103) is then divided down by the first frequency divider 130 (if present) and the resulting signal is provided as input to the PFD 150 together with the high-frequency reference signal 101.

[0114] In the shown and corresponding embodiments (using only a first and a second frequency divider), the frequencies of the crystal-free oscillator circuit 100/the PLL circuit 110 may be seen as being governed according to:

[00002]$f_{\mathrm{ref}}=\frac{1}{N}.Math.\left(\frac{f_{v.Math.c.Math.o}}{M}{f}_{\mathrm{DDS}}\right).Math.f_0=f_{v.Math.c.Math.o}=M.Math.\left(N.Math.f_{\mathrm{ref}}{f}_{\mathrm{DDS}}\right).Math.f_{\mathrm{DDS}}=\frac{f_0}{M}-N.Math.f_{\mathrm{ref}}$

where f.sub.ref is the frequency of the high-frequency reference signal 101, f.sub.vco is the frequency of the PLL oscillator 120, f.sub.0 is the frequency of the high-frequency output signal 103, f.sub.DDS is the frequency offset value offsetting the frequency of the input of the PLL circuit (by the adjustable frequency offset circuit 210, e.g. comprising a DDS, offsetting the feedback signal), N is the integer value of the first frequency divider 130, and M is the integer value of the second frequency divider 131, each at each time instance.

[0115] As one example, in case of Bluetooth Low Energy (BLE) communication, the channel spacing is 2 MHz, f.sub.0 (the carrier) is in the range from (about) 2400 MHz to 2480 MHz. If the f.sub.vco is about 2000 MHz, this frequency is divided by 4 resulting in a f.sub.ref of about 500 MHz.

[0116] If the first and second frequency dividers 130, 131 each divides by 2, then the frequency range of f.sub.DDS can be calculated according to:

[00003]$f_{\mathrm{DDS}}=\frac{f_0^{}+.Math..Math.f}{M}-N.Math.f_{\mathrm{ref}}.Math.f_{\mathrm{DDS}}=\frac{2.Math.0.Math.0.Math.0+.Math.f}{2}-2.Math.400=200+\frac{.Math.f}{2}$

where the frequency f is in the range from 0 MHz to 80 MHz and f may be expressed as:

f=n.Math.f.sub.chl+f.sub.T+f.sub.M(t)

where n is a channel scaler or channel (0 to 40 according to BLE), f.sub.chl is channel spacing (being 2 MHz according to BLE), f.sub.T is the offset and temperature compensated frequency, and f.sub.M(t) is a modulation frequency function versus time.

[0117] Other embodiments may correspond to the one shown in FIG. 2 but without the first frequency divider 130.

[0118] FIG. 3 schematically illustrates yet another exemplary embodiment of crystal-free oscillator for channel-based high-frequency radio communication.

[0119] Illustrated is an exemplary embodiment of a crystal-free oscillator circuit 100 for channel-based high-frequency radio communication as disclosed herein, where the crystal-free oscillator circuit 100 corresponds to the one shown and explained in connection with FIG. 2 except as noted in the following.

[0120] Instead of providing one output from each of the frequency generator 200 and the second frequency divider 131 as in FIG. 2, the frequency generator 200 and the second frequency divider 131 each provide two outputs (respectively comprising Q (of the quadrature signal) and I (of the in-phase signal)), where a first output from the frequency generator 200 and a first output of the second frequency divider 131 is mixed or modulated by mixer or modulator 135 (as described in connection with FIG. 2) (resulting in a first mixed or modulated signal) and a second output from the frequency generator 200 and a second output of the second frequency divider 131 is mixed or modulated by an additional mixer or modulator 136 (as described in connection with FIG. 2) (resulting in a second mixed or modulated signal). The two resulting signals are then added by adding element 137 and the result of the addition is output by the adjustable frequency offset circuit 210, where the resulting frequency offset feedback signal 102 (here being a processed signal based on the high-frequency output signal 103) then is divided down by the first frequency divider 130 N times (if present) where the potentially N-divided down frequency offset feedback signal 102 is provided as input to the PFD 150 together with the reference signal 101. This arrangement provides quadrature of the outputs of the frequency generator 200 and the second frequency divider 131 enabling an efficient rejection of a mirror product. Alternatively, a filter (with a relatively low order) may be used to enable rejection of mirror a product (and may e.g. be used in embodiments corresponding to the ones of FIGS. 1 and 2 and others). However, such a filter is fairly complex to realise in a usable manner in an integrated circuit.

[0121] Other embodiments may correspond to the one shown in FIG. 3 but without the first frequency divider 130. As mentioned, the crystal-free oscillator 100 may in some embodiments comprise a third static frequency divider being located between the crystal-free oscillator element and the PLL circuit and being configured to divide down a frequency of an output signal of the crystal-free oscillator element by a factor being a third predetermined positive integer (R) to generate the high-frequency reference signal

[0122] The quadrature arrangement may also be used for other embodiments, e.g. the ones (and corresponding ones) shown in FIGS. 1, 4 and 5.

[0123] FIG. 4 schematically illustrates another exemplary embodiment of crystal-free oscillator for channel-based high-frequency radio communication.

[0124] Illustrated is an exemplary embodiment of a crystal-free oscillator circuit 100 for channel-based high-frequency radio communication as disclosed herein, where the crystal-free oscillator circuit 100 corresponds to the one shown and explained in connection with FIG. 1 except as noted in the following. In FIG. 4, a second (static) frequency divider 131, dividing down by M) is located in the feedback loop before the adjustable frequency offset circuit 210 (or at least before the adjustable frequency offset circuit 210 offsets the frequency of the feedback signal 102 as disclosed herein) rather than being located after the adjustable frequency offset circuit 210 or after the adjustable frequency offset circuit 210 has offset the frequency of the feedback signal 102 as in FIG. 1 (where such a frequency divider is designated a first frequency divider (N)).

[0125] FIG. 5 schematically illustrates a further exemplary embodiment of crystal-free oscillator for channel-based high-frequency radio communication.

[0126] Illustrated is an exemplary embodiment of a crystal-free oscillator circuit 100 for channel-based high-frequency radio communication as disclosed herein, where the crystal-free oscillator circuit 100 corresponds to the one shown and explained in connection with FIG. 1 except as noted in the following. In FIG. 5, instead of compensating for a temperature dependency of the crystal-free oscillator circuit via an adjustable frequency offset circuit 210 as disclosed herein (i.e. in addition to offsetting the frequency of the feedback signal 102), then the temperature dependency compensation is done by adjusting signals or other aspects of the crystal-free oscillator element 120. More particularly, a temperature compensation signal 510 is received or used by the crystal-free oscillator element 120. In some embodiments where the crystal-free oscillator element 120 is an LC-based oscillator, this may e.g. be done by controlling a capacitor value of the LC oscillator e.g. as described in connection with FIGS. 9 and/or 10.

[0127] FIG. 6 schematically illustrates an integrated circuit comprising an embodiment of a crystal-free oscillator for channel-based high-frequency radio communication as disclosed herein together with additional elements.

[0128] Illustrated is a crystal-free oscillator circuit 100 for channel-based high-frequency radio communication as disclosed herein comprising a crystal-free oscillator element 120 and a PLL 110, e.g. a crystal-free oscillator element 120 and a PLL 110 as shown and/or explained in connection with any one of FIGS. 1-5. In this particular exemplary and corresponding embodiments, the crystal-free oscillator circuit 100 further comprises a temperature sensor 610, a frequency counter 620, a controllable heating element 630, and a memory and/or storage 640.

[0129] In some embodiments, all these elements may are manufactured as a solid-state monolithic integrated circuit. It is possible to manufacture a large number of such integrated circuits on-chip/on-silicium e.g. on a single wafer or similar 300. This is opposed e.g. to crystal-based oscillators that cannot completely be manufactured as a monolithic integrated circuit due to the resonator part of such comprising the crystal.

[0130] The controllable heating element 630 is configured to heat at least a part of the PLL 110 (e.g. a part comprising the adjustable frequency offset circuit 210) as indicated by the arrow pointing to the crystal-free oscillator element 120 and the PLL 110 from the heating element 630. In some embodiments, the controllable heating element 630 is a resistor circuit or element generating heat in response to being provided with an electrical current. In some alternative embodiments, the crystal-free oscillator circuit 100 or the PLL 110, comprises a controllable cooling element (or the heating element 630 is configured also to be able to cool) configured to cool at least a part of the crystal-free oscillator element 120 and/or the PLL 110. Cooling may e.g. be used to cool at least a part of the crystal-free oscillator element 120 and/or the PLL 110 to a predetermined starting temperature used during initial calibration as disclosed elsewhere herein. In other embodiments, the controllable heating element may be replaced by a so-called hot plate (or as a further alternative a cold plate instead or as an addition).

[0131] The temperature sensor 610 is configured to measure (as indicated by the arrow pointing from the crystal-free oscillator element 120 and the PLL 110 to the temperature sensor 610) the temperature of at least a part of the crystal-free oscillator element 120 and/or the PLL 110 or alternatively at least a part of the crystal-free oscillator circuit 100 resulting in a value representing a current operating temperature of the crystal-free oscillator element 120 and/or the PLL 110 (or the crystal-free oscillator circuit 100).

[0132] The frequency counter 620 is configured to measure or count (e.g. in reference to a known external accurate frequency) the frequency of the feedback signal 102, the frequency of the high-frequency reference signal 101, or the frequency of the high-frequency output signal 103 (e.g. for embodiments such as shown in FIGS. 1-5) during initial calibration. The frequency isat least in some embodimentsmeasured or counted where the adjustable frequency offset circuit or the frequency generator (see e.g. 210 or 200 in FIGS. 1-5) is located or where the adjustable frequency offset circuit offsets the frequency as disclosed herein. Alternatively, the frequency may be counted (e.g. for embodiments such as shown in FIGS. 9 and 10) near the crystal-free oscillator element 120 or the LC-based oscillator (LCO) 120.

[0133] These elements enable efficient determination of the predetermined relationship or function (used according to at least some embodiments by the adjustable frequency offset circuit) between operating temperatures and respective associated counted or measured frequencies (used according to at least some embodiments by the adjustable frequency offset circuit to compensate for respective frequency deviation) for the particular crystal-free oscillator circuit 100. From the respective associated counted or measured frequencies and the known external accurate frequency, an offset frequency value (may be positive or negative) can be determined for the particular crystal-free oscillator circuit 100 at respective operating temperatures

[0134] This may e.g. be done by incrementally or continuously increasing the temperature using the heating element 630 (or alternatively decrease using a cooling element) and for each temperature value then obtaining a frequency by the frequency counter 620. Each temperature value and obtained frequency value (or each temperature value and an frequency offset value derived by finding the difference between an obtained frequency value and a frequency target value) may then e.g. be stored in a suitable memory and/or storage 640 (as indicated by the arrows pointing to the memory and/or storage 640) as a data structure representing a profile, a table of pairs, or other suitable data structure of operating temperatures of the crystal-free oscillator element 120 and/or PLL 110 (or alternatively of the crystal-free oscillator circuit 100) and associated frequency values. Further details of such exemplary generation of the predetermined relationship or function is e.g. shown and given in connection with FIG. 7.

[0135] The stored values or profile may e.g. then be supplied during operation from the memory and/or storage 640 as indicated by arrow 104 or arrow 510 in FIG. 5 to the adjustable frequency offset circuit of the PLL or to the crystal-free oscillator circuit as disclosed herein. During operation, a current temperature may then be measured or obtained (by the temperature sensor 610) and from that and using the data of the memory and/or storage 640 it is possible to derive a frequency (and/or phase) offset value that is to be used by the adjustable frequency offset circuit when at (or near) the associated temperature to compensate for the frequency difference to a target frequency. It is noted, that the frequency values obtained and stored during initial calibration does not need to be absolute values but just need to correlate with the respective temperatures obtained during initial calibration. This is much simpler and reduces the needed complexity of the frequency counter 620 and also avoids the need of calibrating the temperature sensor 610. The current temperature obtained during operation does not need to exist as a temperature value in the memory and/or storage 640 as the associated frequency e.g. can be interpolated using the stored temperature and frequency values and the obtained temperature value.

[0136] FIG. 7 schematically illustrates one embodiment of a method of generating pairs of temperature and frequency values for a specific crystal-free oscillator circuit.

[0137] Illustrated is a flow-chart of one embodiment of a method of generating pairs of temperature and frequency values for a specific crystal-free oscillator circuit as disclosed herein e.g. during initial (post-manufacture) calibration.

[0138] At step 901, the method starts and potentially is initialized, etc. This may e.g. involve setting a starting temperature (e.g. by cooling) of a particular crystal-free oscillator circuit, e.g. of the crystal-free oscillator element 120 and/or the PLL (see e.g. 100, 120, and 110 in FIGS. 1-6).

[0139] At step 902, the temperature of (at least a part of) the particular crystal-free oscillator circuit, e.g. the crystal-free oscillator element 120 and/or the PLL is increased incrementally or continuously.

[0140] At step 903, a current temperature of the crystal-free oscillator circuit, e.g. the crystal-free oscillator element 120 and/or the PLL and a measured frequency of the feedback signal (see e.g. 102 in FIGS. 1-6) are determined. The current temperature is preferably determined when or close to when the frequency is measured (as the frequency will vary with temperature).

[0141] The frequency value may e.g. be determined by measuring or obtaining a frequency value, e.g. using a frequency counter or similar. The frequency value may e.g. by measured by measuring or counting (e.g. in reference to a known external accurate frequency) the frequency of the feedback signal, the frequency of the high-frequency reference signal, or the frequency of the high-frequency output signal (e.g. for embodiments such as shown in FIGS. 1-5). The frequency isat least in some embodimentsmeasured or counted where an adjustable frequency offset circuit as disclosed herein (see e.g. 200 in FIGS. 1-6) is located or where the adjustable frequency offset circuit offsets the frequency as disclosed herein. Alternatively, the frequency may be counted (e.g. for embodiments such as shown in FIGS. 9 and 10) near the crystal-free oscillator element 120 or the LC-based oscillator (LCO) 120.

[0142] At step 904, the determined frequency value and the obtained temperature are stored in a suitable memory and/or storage for later use by the adjustable frequency offset circuit e.g. as disclosed herein.

[0143] At step 905 it is tested whether further frequency value(s) should be determined for further temperature(s). If yes, the method loops back to step 902 where the temperature is increased (or alternatively decreased) further. If no, the method ends at step 907. A number of frequency and temperature value(s) should be obtained to be sufficient to reliably cover a temperature operation range of the device that the specific crystal-free oscillator circuit is to be used in. In some embodiments, the number of frequency and temperature values is about 5 or about 4-6, but the number may vary according to specific embodiment and/or use. As an example, a temperature operation range of a device may e.g. be about 5 C. to about 50 C. or some other appropriate range depending on the specific device that the specific crystal-free oscillator circuit is to be used in.

[0144] In this way, a temperature and frequency profile is established for a particular crystal-free oscillator circuit (e.g. crystal-free oscillator element and/or PLL). It is noted, that this profile very likely (if not practically guaranteed) will be unique for the particular crystal-free oscillator circuit, crystal-free oscillator element, or PLL as these will have substantial parameter variation from circuit to circuit even when produced on a same wafer or similar. Accordingly, the parameter variation inherent for crystal-free oscillators may readily be addressed.

[0145] As mentioned, it is possible (and advantageous) to manufacture several crystal-based oscillator circuits as integrated circuits e.g. on a single wafer. In such cases, the method of FIG. 7 may comprise a repeat of steps 901-906 for a next crystal-based oscillator circuit until all relevant crystal-based oscillator circuits have been processed in this way.

[0146] This method may be fully automated and is relatively very fast. As an example, it may take less than about 90 or 100 milliseconds or even only about 10 to about 50 milliseconds to determine a profile for one crystal-based oscillator circuit.

[0147] Steps 902-904 may e.g. be carried out as explained in connection with FIG. 6, as disclosed herein, or alternatively in any other suitable manner.

[0148] It is noted that step 902 may alternatively be carried out after step 903, after step 904, or in the Y/yes branch of step 905 (then looping back to step 903 in case of yes at step 906). It is also possible to only carry out step 904 once after determining all relevant temperature and frequency values have been determined (then storing all relevant pairs in one go).

[0149] In principle and as mentioned, instead of increasing from a starting temperature, the method could be modified to decrease the temperature from a starting temperature but for many typical cases this is less practical (although initial cooling to a predetermined starting temperature before heating and measuring is practical at least for some embodiments).

[0150] FIG. 8 schematically illustrates a device, and in particular a liquid drug delivery device, comprising a crystal-free oscillator circuit for channel-based high-frequency radio communication as disclosed herein.

[0151] Shown, is an exemplary injection device 400 comprising a housing 401 encompassing various components of the injection device 400.

[0152] An arrow in FIG. 8 indicates a general distal end and a general distal direction of the injection device 400 and its components while a proximal end and direction are the opposite (the arrow points towards the distal end/in the distal direction).

[0153] The housing 401 e.g. comprises or stores a cartridge or similar where the cartridge is mounted in the housing 401 or in a cartridge holder connected to the housing 401 e.g. distally to a piston rod as in basically any or at least many types of injection devices. The cartridge may e.g. have a distal end being closed by a septum or the like and a proximal end being closed by a movable plunger or the like defining an interior of the cartridge containing a liquid drug to be expelled during use.

[0154] In some embodiments, the cartridge is replaceable while in other embodiments it is not replaceable. The latter is the case e.g. for disposable injection device, which typically involve a certain number of uses. It is typically recommended for safety reasons that such disposable injection devices are discarded after a certain period of time (e.g. about three weeks or so) even if it still contains a liquid drug to dispense.

[0155] The injection device 400 further comprises a needle cannula 402 or similar e.g. being connected to a hub or the like to form a needle assembly.

[0156] The needle cannula 402 has a distal end with a tip and a proximal end that, when the needle assembly is properly attached to the injection device 400, is in liquid communication with the interior of the cartridge.

[0157] The injection device 400 may also comprise a protective cap (not shown) surrounding at least the distal end of the needle cannula 402 and a distal end of the housing 401 when the cap is fitted or mounted to or on the housing 401.

[0158] The injection device 400 comprises a crystal-free oscillator circuit for channel-based high-frequency radio communication as disclosed herein. A crystal-free oscillator circuit for channel-based high-frequency radio communication as disclosed herein is particularly advantageous for use in or with such a disposable injection device 400 as the costs for a communications capable disposable device is reduced. In this way, it is possible to provide communications related functionality (sending/receiving information, data, etc.) even for more or less disposable products e.g. involving only a single use, a few uses, or uses only for a limited amount of time such as for about a month or couple of weeks or less.

[0159] In some embodiments, the injection device 400 is an insulin injection device or a disposable insulin injection device. An injection device of the type shown in FIG. 8 is generally also referred to a pen-based injection device.

[0160] FIG. 9 schematically illustrates an exemplary embodiment of a crystal-free oscillator element according to various embodiments. Shown is an embodiment of a crystal-free oscillator element 120 as disclosed herein and in the form of an LC oscillator receiving a bias current (I.sub.bias) from a controllable current source 801 and being connected to an electrical reference potential 802 such as electrical ground. The crystal-free oscillator element 120 is as an example a differentially implemented CMOS oscillator comprising four transistors 804, connected as shown, and an LC resonator circuit 803. The LC resonator circuit 803 is tuneable with respect to frequency and comprises, in the shown embodiment, a fixed value inductor 806 (e.g. comprising one or more inductors) and a controllable and variable capacitor 805 (comprising one or more but preferably a plurality of capacitors e.g. as shown and explained further in connection with FIG. 10) connected in parallel. By varying the capacitance 805 via one or more control signals (illustrated by the freq. tuning signal(s)), the resonant frequency and thereby the output frequency (i.e. the high-frequency reference signal 101) of the crystal-free oscillator element 120 can controllably be adjusted. According to at least some embodiments, the frequency is tuned (e.g. as explained in connection with FIG. 10) to compensate for a temperature dependency of the crystal-free oscillator circuit or element in response to a measured current operating temperature as disclosed herein. It is noted, that in this respect the frequency adjustment here is made for temperature compensation purposes where an adjustable frequency offset circuit 210 still will offset the frequency in a feedback loop of a PLL as disclosed herein to provide the advantages associated therewith. The bias current may be adjusted to provide an optimal operating point of the crystal-free oscillator element 120 but it is not, at least not according to this and corresponding embodiments, used for frequency adjustments.

[0161] FIG. 10 schematically illustrates further details of the crystal-free oscillator element of FIG. 9 together with additional elements. Illustrated is a crystal-free oscillator element 120 being supplied with a bias current 801 and generating an oscillating output signal (F.sub.LCO) 101 to a PLL 110 as disclosed herein. The crystal-free oscillator element 120 is illustrated together with a controllable and variable capacitor side 805 of an LC resonator circuit (see e.g. 803 in FIG. 9). In the shown embodiments, the controllable and variable capacitor side 805 comprises at least one fixed or base capacitor 841 (illustrated as one capacitor and labelled C1), a group of (in this particular embodiment nine) switchable capacitors 842 (illustrated as one capacitor and labelled C2), e.g. arranged in a capacitor bank or the like, and at least one voltage controlled capacitor 843 (illustrated as one capacitor and labelled C3), e.g. a varactor or the like, connected in parallel.

[0162] The group of switchable capacitors 842 is controlled in response to a first tuning control signal 830 (labelled course-tune), as an example in the form of an 9 bit digital signal (for a group of nine capacitors), controlling which of the switchable capacitors of the group 842 should be activated at any given time.

[0163] Additionally, the at least one voltage controlled capacitor 843 is controlled in response to a second tuning control signal 831 (labelled fine-tune) in the form, as an example, a 10 bit digital signal. The second tuning control signal 831 is converted into an analog voltage signal by a digital to analog converter (DAC) 820 thereby controlling the amount of voltage received by the at least one voltage controlled capacitor 843 in dependency of the second tuning control signal 831. Accordingly, the output of the crystal-free LC oscillator element 120 can be tuned coarsely by the first tuning control signal 830 and finely by the second tuning control signal 831 enabling very precise and efficient control of the frequency output by the crystal-free LC oscillator element 120.

[0164] Further shown, is a temperature sensor 610 e.g. or preferably located near the crystal-free oscillator element 120 providing a temperature dependent voltage representative of the obtained temperature where the voltage is converted, by an analog to digital converter ADC 810, into a 10 bit, as an example, digital sensor signal 832 being provided to a processing circuit or element for generation (and supply) of the first and second tuning control signals 830, 831 in dependency thereto.

[0165] Further shown is a controllable heating element 630 e.g. or preferably also located near the crystal-free oscillator element 120 that in response to a heating control signal 833 generates heat in dependency thereto. The controllable heating element 630 is at least in some embodiments a resistor circuit or element 630 generating heat in response to being provided with an electrical current. The heating control signal 833 may e.g. be supplied by the processing circuit or element (and e.g. converted from a digital signal to an analog current signal by a suitable ADC (not shown)). The controllable heating element 630 may e.g. be used as disclosed herein and in particular as disclosed in connection with FIG. 7.

[0166] Some preferred embodiments have been shown in the foregoing, but it should be stressed that the invention is not limited to these, but may be embodied in other ways within the subject matter defined in the following claims.

[0167] In the claims enumerating several features, some or all of these features may be embodied by one and the same element, component or item. The mere fact that certain measures are recited in mutually different dependent claims or described in different embodiments does not indicate that a combination of these measures cannot be used to advantage.

[0168] It should be emphasized that the term comprises/comprising when used in this specification is taken to specify the presence of stated features, elements, steps or components but does not preclude the presence or addition of one or more other features, elements, steps, components or groups thereof.