Circuit and architecture for a demodulator for a wireless power transfer system and method therefor

Abstract

A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

Claims

1. A wireless power transmitter comprising: a data input node; a demodulator circuit including: a buffer having a non-inverting input, an inverting input, and an output, the non-inverting input coupled to the data input node, the inverting input coupled to the output; a sample and hold (SH) circuit including a switch having a first terminal coupled to the output of the buffer, and a capacitor coupled between a second terminal of the switch and a ground terminal; and a phase delay generator circuit having an input coupled to the output of the buffer, and an output coupled to a control terminal of the switch of the SH circuit; and a data output node coupled to the second terminal of the SH circuit.

2. The wireless power transmitter of claim 1, wherein the buffer includes a differential amplifier.

3. The wireless power transmitter of claim 1, wherein the buffer includes an open loop buffer.

4. The wireless power transmitter of claim 1, wherein the buffer is configured to receive a DC bias near zero volt.

5. The wireless power transmitter of claim 1, wherein the buffer is configured to receive a DC bias at 200 mV.

6. The wireless power transmitter of claim 1, wherein the demodulator circuits includes a tank circuit coupled between the data input node and the non-inverting input of the buffer.

7. The wireless power transmitter of claim 1, wherein the demodulator circuits includes a comparator coupled between the second terminal of the SH circuit and the data output node.

8. The wireless power transmitter of claim 7, wherein the demodulator circuit includes a low pass filter coupled between the second terminal of the switch and the comparator.

9. The wireless power transmitter of claim 8, wherein the demodulator circuit includes: an RC filter coupled between the low pass filter and the comparator, wherein the comparator has a non-inverting input coupled to the low pass filter via the RC filter, and an inverting input coupled to the low pass filter and bypassing the RC filter.

10. The wireless power transmitter of claim 8, wherein the demodulator circuit includes: a threshold detection circuit coupled between the low pass filter and the comparator, wherein the comparator has a non-inverting input coupled to the low pass filter via the threshold detection circuit, and an inverting input coupled to the low pass filter and bypassing the threshold detection circuit.

11. The wireless power transmitter of claim 10, wherein the threshold detection circuit includes a peak detector and a valley detector parallel to the peak detector.

12. The wireless power transmitter of claim 1, further comprising: a power stage circuit; a power transmission coil coupled to the power stage circuit, the power transmission coil having the data input node; and a controller having an input coupled to the data output node, and an output coupled to the power stage circuit.

13. The wireless power transmitter of claim 1, wherein the demodulator circuit is Wireless Power Consortium (WPC) standard compliant.

14. The wireless power transmitter of claim 1, wherein the demodulator circuit includes: a reference voltage source; a first resistor coupled between the reference voltage source and the non-inverting input of the buffer; and a second resistor coupled between the non-inverting input of the buffer and the ground terminal.

15. The wireless power transmitter of claim 1, wherein the demodulator circuit includes: a differentiator circuit coupled to the output of the buffer; and a slope detector circuit coupled between the differentiator circuit and the phase delay generator circuit, wherein the input of the phase delay generator circuit coupled to the output of the buffer via the differentiator circuit and the slope detector circuit.

16. The wireless power transmitter of claim 1, wherein the phase delay generator circuit is configured to generate a pulse signal having a 45 degrees phase delay from the output of the buffer.

17. A wireless power transmitter comprising: a power stage circuit; a power transmission coil coupled to the power stage circuit; a demodulator circuit including: a data input node coupled to the power transmission coil; a buffer having a non-inverting input, an inverting input, and an output, the non-inverting input coupled to the data input node, the inverting input coupled to the output; a sample and hold (SH) circuit including a switch having a first terminal coupled to the output of the buffer, and a capacitor coupled between a second terminal of the switch and a ground terminal; a phase delay generator circuit having an input coupled to the output of the buffer, and an output coupled to a control terminal of the switch of the SH circuit; and a data output node coupled to the second terminal of the SH circuit; and a controller having an input coupled to the data output node, and a controller output coupled to the power stage circuit.

18. The wireless power transmitter of claim 17, wherein the demodulator circuits includes a comparator coupled between the second terminal of the SH circuit and the data output node.

19. The wireless power transmitter of claim 18, wherein the demodulator circuit includes a low pass filter coupled between the second terminal of the switch and the comparator.

20. The wireless power transmitter of claim 19, wherein the demodulator circuit includes: an RC filter coupled between the low pass filter and the comparator, wherein the comparator has a non-inverting input coupled to the low pass filter via the RC filter, and an inverting input coupled to the low pass filter and bypassing the RC filter.

21. The wireless power transmitter of claim 19, wherein the demodulator circuit includes: a threshold detection circuit coupled between the low pass filter and the comparator, wherein the comparator has a non-inverting input coupled to the low pass filter via the threshold detection circuit, and an inverting input coupled to the low pass filter and bypassing the threshold detection circuit.

22. The wireless power transmitter of claim 21, wherein the threshold detection circuit includes a peak detector and a valley detector parallel to the peak detector.

23. The wireless power transmitter of claim 17, wherein the demodulator circuit is Wireless Power Consortium (WPC) standard compliant.

24. The wireless power transmitter of claim 17, wherein the demodulator circuit includes: a reference voltage source; a first resistor coupled between the reference voltage source and the non-inverting input of the buffer; and a second resistor coupled between the non-inverting input of the buffer and the ground terminal.

25. The wireless power transmitter of claim 17, wherein the demodulator circuit includes: a differentiator circuit coupled to the output of the buffer; and a slope detector circuit coupled between the differentiator circuit and the phase delay generator circuit, wherein the input of the phase delay generator circuit coupled to the output of the buffer via the differentiator circuit and the slope detector circuit.

26. The wireless power transmitter of claim 17, wherein the phase delay generator circuit is configured to generate a pulse signal having a 45 degrees phase delay from the output of the buffer.

27. A demodulator circuit comprising: a data input node adaptive to be coupled to a wireless power transmission coil; a buffer having a non-inverting input, an inverting input, and an output, the non-inverting input coupled to the data input node, the inverting input coupled to the output; a sample and hold (SH) circuit including a switch having a first terminal coupled to the output of the buffer, and a capacitor coupled between a second terminal of the switch and a ground terminal; a phase delay generator circuit having an input coupled to the output of the buffer, and an output coupled to a control terminal of the switch of the SH circuit; and a data output node coupled to the second terminal of the SH circuit, the data output node configured to output a data signal for regulating power transmission by the wireless power transmission coil.

28. The demodulator circuit of claim 27, wherein the buffer includes a differential amplifier.

29. The demodulator circuit of claim 27, wherein the buffer includes an open loop buffer.

30. The demodulator circuit of claim 27, wherein the buffer is configured to receive a DC bias near zero volt.

31. The demodulator circuit of claim 27, wherein the buffer is configured to receive a DC bias at 200 mV.

32. The demodulator circuit of claim 27, further comprising: a comparator coupled between the second terminal of the SH circuit and the data output node.

33. The demodulator circuit of claim 32, further comprising: a low pass filter coupled between the second terminal of the switch and the comparator.

34. The demodulator circuit of claim 33, further comprising: an RC filter coupled between the low pass filter and the comparator, wherein the comparator has a non-inverting input coupled to the low pass filter via the RC filter, and an inverting input coupled to the low pass filter and bypassing the RC filter.

35. The demodulator circuit of claim 33, further comprising: a threshold detection circuit coupled between the low pass filter and the comparator, wherein the comparator has a non-inverting input coupled to the low pass filter via the threshold detection circuit, and an inverting input coupled to the low pass filter and bypassing the threshold detection circuit.

36. The demodulator circuit of claim 35, wherein the threshold detection circuit includes a peak detector and a valley detector parallel to the peak detector.

37. The demodulator circuit of claim 27, further comprising: a reference voltage source; a first resistor coupled between the reference voltage source and the non-inverting input of the buffer; and a second resistor coupled between the non-inverting input of the buffer and the ground terminal.

38. The demodulator circuit of claim 27, further comprising: a differentiator circuit coupled to the output of the buffer; and a slope detector circuit coupled between the differentiator circuit and the phase delay generator circuit, wherein the input of the phase delay generator circuit coupled to the output of the buffer via the differentiator circuit and the slope detector circuit.

39. The demodulator circuit of claim 27, wherein the phase delay generator circuit is configured to generate a pulse signal having a 45 degrees phase delay from the output of the buffer.

40. The demodulator circuit of claim 27, wherein the data signal is Wireless Power Consortium (WPC) standard compliant.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) Further aspects of the invention will appear from the appending claims and from the following detailed description given with reference to the appending drawings.

(2) FIG. 1 is a diagram of a wireless power system according to the prior art;

(3) FIG. 2 is a graph showing the tank waveform in a wireless power system;

(4) FIG. 3 is a graph showing the tank waveform in which the two signals in a wireless power system have the same amplitude;

(5) FIG. 4 is a block diagram of an embodiment constructed according to the principles of the present disclosure;

(6) FIG. 5 shows an alternate embodiment constructed according to the principles of the present disclosure;

(7) FIGS. 6-13 show waveforms for the circuits illustrated in FIGS. 4 and 5;

(8) FIG. 14 is a block diagram of a circuit for generating a 45 phase delayed clock;

(9) FIGS. 15-20 show waveforms for the circuit illustrated in FIG. 14.

DETAILED DESCRIPTION

(10) In order to have a reliable communication channel, the system must tolerate system parameter variations including variations in the coupling coefficient (K) of between 0.2 and 0.7, and variation in the receiver load from 5 ohms to 1 kilo ohm, transmit and receive coil inductance variation due to shielding, effects of the battery effects of a magnet used to center the receiving device on the transmitting pad and manufacturing tolerances over the entire range of operating frequency from 110 kHz to 205 kHz.

(11) The WPC defined communication channel assumes that the incoming signal is always amplitude modulated. However, the present inventors have discovered that this information may be lost because of its low value (i.e. 200 mV) which may be further reduced when the power signal level (which can be 70 Vpp) is divided down to a voltage level that can be handled by an integrated circuit, as this signal, which rides on the power signal, will also be reduced. This low level signal can be masked by changes in the load current. Accordingly, the inventors have determined that the signal data may lie within the phase of incoming carrier signal, rather than the amplitude. Therefore, a traditional amplitude demodulator channel is inadequate to solve the problems described above.

(12) FIG. 2 shows the tank signal waveform of the power transmitter where data is being sent from the receiver to the transmitter, generally as 200. In FIG. 2, the load resistance is 100 ohms, the coefficient of coupling K is 0.7, the secondary (receiver) side capacitor, utilized to transmit data or commands back to the transmitter (primary) side, is 22 nF. The primary side inductance is 9.36 H and the secondary side inductance is 16 H with the circuit having an operating frequency of 155 kHz. Waveform 202 is without the capacitor being coupled across the secondary side of receiver coil and the waveform 204 shows the same signal with the capacitor coupled across the secondary side receive coil to transmit information. Under these circumstances, there is a difference in amplitude between the two waveforms and the information in the signal can be amplitude detected.

(13) FIG. 3 shows the tank signal waveform of a power transmitter generally as 300. In FIG. 3, the load resistance is 5 ohms, the coupling coefficient is 0.2, the capacitance is 22 nF, the primary side inductor is 9.36 H, the secondary side inductor is 16 H and the operating frequency is 155 kHz. As can be seen, the peaks of the waveforms with and without capacitance being switched in at the secondary side, are identical at 306. The exploded view shows the signal 302 which is the signal without the capacitor being switched in across the receiver side coil and the signal 304 which shows the capacitor switched in across the coil. Therefore, it may be very difficult to detect the data when the signal peaks are essentially identical utilizing amplitude demodulation.

(14) FIG. 4 shows an embodiment of a solution to this problem generally as 400. In FIG. 4, the tank waveform from the transmitter side tank circuit is coupled via resistor divider 402, 404 to a capacitor 406. The resistor divider 402, 404 divides of the voltage across the tank circuit, which may be as much as 70 V peak to peak, to a voltage level that can be handled by an integrated circuit. Capacitor 406 blocks the DC level of the input waveform from affecting the setpoint of a buffer circuit 412, the non-inverting input of which is coupled to the capacitor 406. This allows the setpoint of the buffer 412 to be set via the resistor divider 408, 410 between a reference voltage and ground. The inventors have found it to be advantageous to utilize the voltage just slightly above 0 V, for example, 100 or 200 mV as the setpoint for the buffer 412. In addition, the circuit may be operated at a higher voltage than may be used for other portions of the transmitter circuit, for example 4 V rather than 3.3 V. The combination of these two features allows for an increased voltage swing of the measured data or commands in the signal stream. Buffer 412 has its output coupled to the inverting input thereof so that it has a gain of unity. The output of buffer 412 is coupled to a differentiator circuit 414, 416, 418, 420 and 422. The amplifier 422 has its inverting input coupled to the output of the buffer 412 via resistor 414 and coupling capacitor 416, which are coupled in series. The amplifier 422 has its output coupled to the inverting input with the parallel combination of resistor 418 and capacitor 420. Placing a small value capacitor such as capacitor 420 across the feedback resistor 418 and placing a resistor in series with the input, such as resistor 414, increases the stability of the differentiator circuit. The non-inverting input to amplifier 422 is coupled to half the supply voltage as a reference for maximizing the dynamic range of the input and output signals. The output of amplifier 422 is coupled to the non-inverting input of a zero slope detector 424. The inverting input of slope detector 424 is coupled to the inverting input of amplifier 422. The output of amplifier 424 is coupled to an input of a 45 delayed pulse generator 426, which generates a 45 delay. The output of 45 delayed pulse generator 426 operates the switch 428 of sample hold circuit 428, 430. It should be noted that the phase delay can range at least between 15 and 75 without departing from the principles of the present disclosure.

(15) A sample value is stored in capacitor 430 which is coupled between the switch and ground. The voltage across capacitor 430 is filtered by a low pass filter 432, here in a fifth order Butterworth low pass filter. The output of the low pass filter 432 is connected to the inverting input of a low-offset or auto-zero comparator 438. The output of the low pass filter 432 is also coupled through RC filter 434, 436 to the non-inverting input of auto-zero comparator 438. The resistor 434 is coupled in series between the output of low pass filter 432 and the non-inverting input of auto zero comparator 438. The capacitor is connected between the non-inverting input of the auto-zero comparator 438 and ground. The output of auto zero comparator 438 is the data or command signal.

(16) In operation, the coil voltage from the transmit coil in the transmit tank circuit can be sensed directly. This voltage, which can be as high as 70 V peak to peak the varying DC level, is AC coupled to the demodulator signal chain through a resistor divider 402, 404 which reduces the voltage to level it can be handled by an integrated circuit. Depending upon the voltage reduction of the resistor divider 402, 404, the signal to be detected can be 100 mV or lower riding on top of the 10-70 V peak to peak carrier amplitude. Thus it has a very low signal-to-noise ratio (SNR). In addition, the carrier has both positive and negative swings with respect to ground. Therefore, the present invention maximizes the signal amplitude by setting the DC setpoint at the input of amplifier 412 very close to ground, for example 200 mV. This, along with a higher voltage (for example for 4 V) supply for the amplifier 412 allows for a signal swing of almost 4 V.

(17) The input voltage to the non-inverting terminal of buffer amplifier 412 is shown in FIG. 6, generally as 600. As can be seen, it is an amplitude (or phase) modulated sine wave of frequency between 110 kHz-205 kHz. The amplitude modulation frequency is 2 kHz. The 600 shows two periods; one just before the modulation and one after the modulation.

(18) The output of buffer amplifier 412 is shown in FIG. 7 as a half wave rectified sine wave 700. The output of buffer amplifier 412 is coupled to differentiator circuit 414, 416, 418, 420, 422 which converts the sine wave input (signal 700) into a cosine wave signal 800 shown in FIG. 8. The zero crossing of waveform 800, at 802 in FIG. 8 is detected by zero slope detector 424 which generates an output pulse 900 shown in FIG. 9. The rising edge 902 of pulse 900 corresponds to the zero crossing 802 of signal 800. Pulse 900 is coupled to 45 delayed pulse generator 426 which generates a signal 1000 which is delayed by 45 from the rising edge 902 of signal 900. The inventors have discovered through extensive simulations and analysis that the incoming carrier will have sufficient modulation depth if samples taken between 40 and 50 with respect to the peak are utilized. The signal 1000 is used to operate switch 428 of sample hold circuit 428, 432 to store a sample at the 45 delay point from the tank circuit peak voltage on capacitor 430.

(19) The sampled voltage is shown in FIG. 11 generally as 1100. In order to remove high-frequency noise from the signal, it is passed through a low pass filter, here a fifth order Butterworth low pass filter. The output of the Butterworth low pass filter is shown in FIG. 12 generally as 1200. In order to determine the threshold utilized to extract data or commands from signal stream, RC filter comprising resistor 434 coupled in series between the output of the fifth order Butterworth low pass filter and the non-inverting input of auto zero comparator 438 and a capacitor 436 coupled from the non-inverting input of amplifier 438 to ground is utilized. The threshold 1202 generated by the low pass filter 434, 436 is utilized to extract the data which appears that the output of the auto zero comparator 438. The signal 1206 represents a digital zero and the signal 1204 represents a digital one. The signal 1300 is the output of auto-zero comparator 438, with a digital one output being shown at 1302.

(20) FIG. 5 shows an alternative embodiment of a solution to this problem generally as 500. In FIG. 5, the tank waveform from the transmitter side tank circuit is coupled via resistor divider 502, 504 to a capacitor 506. The resistor divider 502, 504 divides the voltage across the tank circuit, which may be as much as 70 V peak to peak, to a level that can be handled by an integrated circuit. Capacitor 506 blocks the DC level of the input waveform from affecting the setpoint of a buffer circuit 512, the non-inverting input of which is coupled to the capacitor 506. This allows the setpoint of the buffer 512 to be set via the resistor divider 508, 510 between a reference voltage and ground. The inventors have found it to be advantageous to utilize the voltage just slightly above 0 V, for example, 100 or 200 mV as the setpoint for the buffer 512. In addition, this circuit is operated at a higher voltage than may be used for other portions of the transmitter circuit, for example 4 V rather than 3.3 V. The combination of these two features allows for an increased voltage swing of the measured data or commands in the signal stream. Buffer 512 has its output coupled to the inverting input thereof so that it has again of unity. The output buffer 512 is coupled to a differentiator circuit 514, 516, 518, 520 and 522. The amplifier 522 has its inverting input coupled to the output of the buffer 512 via resistor 514 and coupling capacitor 516, which are coupled in series. The amplifier 522 has its output coupled to its inverting input utilizing the parallel combination of the resistor 518 and capacitor 520. Placing a small value capacitor such as capacitor 520 across the feedback resistor 518 and placing a resistor in series with the input, such as resistor 514, increases the stability of the differentiator circuit. The non-inverting input to amplifier 522 is coupled to half the supply voltage as a reference. The output of amplifier 522 is coupled to the non-inverting input of a zero slope detector 524. The inverting input of slope detector 524 is coupled to the inverting input of amplifier 522. The output of amplifier 524 is coupled to an input of a 45 delayed pulse generator 526, which generates a 45 delay. The output of the 45 delayed pulse generator 526 operates the switch 528 of sample hold circuit 528, 530. A sample value is stored in capacitor 530 which is coupled between the switch and ground.

(21) The voltage across capacitor 530 is filtered by a low pass filter 532. In this embodiment only a fourth order Butterworth low pass filter is required. The output of the low pass filter 532 is connected to a threshold detection circuit 540. This threshold detection circuit 540 utilizes a peak detector circuit 542 and a valley detector circuit 560. Peak detector 542 and valley detector 560 are coupled to receive the output of the fourth order Butterworth filter 532 on the data line. This signal is coupled to the non-inverting input of amplifier 544 in peak detector circuit 542 and to the non-inverting input of amplifier 556 in valley detector circuit 560. The output of amplifier 544 is coupled through diode 546 to the inverting input thereof. A capacitor 548 is coupled between the inverting input of the amplifier 544 and a reference voltage, represented by ground. The output of amplifier 556 is coupled through diode 558 to the inverting input thereof. The inverting input is also coupled via a capacitor 550 to the reference potential represented by ground. A pair of resistors 552 and 554 are coupled in series between the inverting input to the amplifier 544 and inverting input to the amplifier 556. A node 553 is at the junction of the two resistors. Node 553 is coupled to the inverting input of comparator 538, the non-inverting input of which is coupled to receive the data. The recovered data is at the output of the comparator 538. This circuit allows smaller capacitors to be utilized, for example two 100 pF capacitors and two 25 mega ohm resistors. Further detail about the threshold detection circuit 540 can be found in commonly-owned application (TI 73620) filed on even date and incorporated herein by reference in its entirety for all purposes.

(22) FIG. 12 shows the threshold signal at the input of comparator 538 as 1202 and shows the data signal at the output 1200 of a fourth order Butterworth low pass filter 532 having a digital zero at 1206 a digital one at 1204. FIG. 13 shows the output of the current threshold detector circuit at 1300, a digital one being shown at 1302.

(23) A circuit for the generation of the phase shift, such as the 45 phase shift of blocks 426 and 526, is shown in FIG. 14, generally as 1400. The clock signal, such as the output of zero slope detector 424, 524 and illustrated in FIG. 15, is applied to the input of a 50 ns pulse generator 1402. The output of pulse generator 1402 is coupled to operate a switch 1404 which samples the voltage across capacitor Cramp 1408 in capacitor hold 1410. The capacitor 1408 is charged by a constant current source 1406. The voltage across the sample and hold capacitor 1410 is divided by resistor divider 1412, 1414, between the switch 1404 and ground. The signal across the capacitor 1408 is shown in FIG. 18, generally as 1800. The output of the resistor divider is shown in FIG. 19 generally in 1900. The output of the 50 ns pulse generator 1402 is also coupled to an input of a 30 ns pulse generator 1416. The pulse generator 1402 can generate a pulse in the range of 20-70 ns and the pulse generator 1416 can generate a pulse in the range of 10-40 ne, for example. The output of pulse generator 1416 is shown in FIG. 17, generally as 1700. This signal is used to operate switch 1420 which discharges the capacitor, thus generating the ramp signal shown in FIG. 18 as 1800. The voltage of the output voltage divider 1412, 1414 is coupled to the non-inverting input of comparator 1422 the inverting input of which is coupled to the voltage across the capacitor 1408. The output signal, shown in FIG. 20, as 2000, is delayed from the input signal by an amount determined by the ratio of resistor 1412, 1414. In this case, the value of resistor 1412 is seven times the value of the resistor 1414, thereby yielding a 45 phase shift (one eighth of 360 degrees).

(24) The 45 phase delayed pulse generators 426, 526 shown in FIGS. 4 and 5, respectively, can be replaced with fixed time delay circuits. The fixed time delay could be 250 ns to 1.2 s, for example. The pulse generated by the time delay circuits may be 300 ns wide, for example. These circuits are somewhat simpler in construction than a phase delayed pulse generator circuit. Circuits capable of generating such time delayed pulses are well known in the art and need not be discussed further herein.

(25) Although the invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.