Landless multilayer circuit board and manufacturing method thereof

Abstract

A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

Claims

1. A landless multilayer circuit board, comprising: a first substrate; a plurality of first circuits on a surface of the first substrate; at least one connecting pillar on a top surface of one of the plurality of first circuits; a second substrate on the surface of the first substrate and at least one top of the at least one connecting pillar, having an opening relating to the at least one top of the at least one connecting pillar; a plating layer on a portion of a surface of the second substrate, and the plating layer doesn't contact the at least one connecting pillar; and a plurality of second circuits, wherein a portion of the second circuits is on the at least one top of the connecting pillar and another portion of the second circuits is on the plating layer, the another portion of the second circuits doesn't contact the portion of the second circuits, the portion of the second circuits contact the connecting pillar directly, a bottom surface of the portion of the second circuits is not on a same plane as a bottom surface of the another portion of the second circuits, and a top surface of the portion of the second circuits is on a same plane as a top surface of the another portion of the second circuits, and wherein an area of the at least one top of the at least one connecting pillar is greater than an area of at least one bottom surface of the at least one connecting pillar connected to the surface of the first circuit; wherein an area of the first circuit connected to the first substrate is greater than the area of the at least one bottom surface of the at least one connecting pillar; and wherein an area of the portion of the second circuits is smaller than an area of the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

2. The landless multilayer circuit board as claimed in claim 1, further comprising at least one first plating layer between a bottom surface of the first circuit and the surface of the first substrate.

3. The landless multilayer circuit board as claimed in claim 1, further comprising at least one second plating layer between the connecting pillar and the second substrate on the top surface of the first circuit.

4. The landless multilayer circuit board as claimed in claim 1, wherein an area of a top surface of the second circuit mounted on the at least one connecting pillar is smaller than an area of the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

5. The landless multilayer circuit board as claimed in claim 1, wherein an area of a top surface of the portion of the second circuits is smaller than an area of the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

6. The landless multilayer circuit board as claimed in claim 1, wherein a width of the portion of the second circuits is different from a width of the another portion of the second circuits.

7. A landless multilayer circuit board, comprising: a first substrate; a plurality of first circuits on a surface of the first substrate; at least one connecting pillar on a top surface of one of the plurality of first circuits; a second substrate on the surface of the first substrate and at least one top of the at least one connecting pillar, having an opening relating to the at least one top of the at least one connecting pillar; a plating layer on a portion of a surface of the second substrate, and the plating layer doesn't contact the at least one connecting pillar; and a plurality of second circuits, wherein a portion of the second circuits is on the at least one top of the connecting pillar and another portion of the second circuits is on the plating layer, the another portion of the second circuits doesn't contact the connecting pillar and the portion of the second circuits, the portion of the second circuits contact the connecting pillar directly, a bottom surface of the portion of the second circuits is not on a same plane as a bottom surface of the another portion of the second circuits, and a top surface of the portion of the second circuits is on a same plane as a top surface of the another portion of the second circuits; wherein an area of the at least one top of the at least one connecting pillar is greater than an area of at least one bottom surface of the at least one connecting pillar connected to the surface of the first circuit.

8. The landless multilayer circuit board as claimed in claim 7, further comprising at least one first plating layer between a bottom surface of the first circuit and the surface of the first substrate.

9. The landless multilayer circuit board as claimed in claim 7, further comprising at least one second plating layer between the connecting pillar and the second substrate on the top surface of the first circuit.

10. The landless multilayer circuit board as claimed in claim 7, wherein an area of a top surface of the portion of the second circuits is smaller than an area of the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

11. The landless multilayer circuit board as claimed in claim 7, wherein a width of the portion of the second circuits is different from a width of the another portion of the second circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a flowchart of an embodiment of a manufacturing method of a landless multilayer circuit board;

(2) FIGS. 2A-2V are schematic views of the manufacturing method of a landless multilayer circuit board;

(3) FIG. 3 is a sectional view of an embodiment of a landless multilayer circuit board;

(4) FIGS. 4A-4M are schematic views of manufacturing a conventional multilayer circuit board;

(5) FIG. 5 is a sectional view of a conventional multilayer circuit board having a gap at an edge of at least one via of the conventional multilayer circuit board;

(6) FIG. 6 is a schematic view of connecting a circuit board with a conventional multilayer circuit board.

DETAILED DESCRIPTION OF THE INVENTION

(7) With reference to FIG. 1, the present invention is a landless multilayer circuit board and a manufacturing method thereof. The manufacturing method of the landless multilayer circuit board comprises the following steps:

(8) providing a first substrate (S100);

(9) patterning a first photoresist layer (S101);

(10) forming a first circuit (S102);

(11) removing the first photoresist layer (S103);

(12) removing a portion of a first plating layer mounted on the first substrate (S104);

(13) forming a second photoresist layer (S105);

(14) patterning the second photoresist layer to form at least one via (S106);

(15) forming a second plating layer (S107);

(16) forming at least one connecting pillar that fills the at least one via (S108);

(17) forming a third photoresist layer (S109);

(18) patterning the third photoresist layer (S110);

(19) removing a portion of the second plating layer (S111);

(20) removing the third photoresist layer (S112);

(21) removing the second photoresist layer (S113);

(22) forming a second substrate (S114);

(23) drilling the second substrate (S115);

(24) forming a third plating layer on the surface of the second substrate (S116);

(25) forming a fourth photoresist layer on the surface of the third plating layer (S117);

(26) patterning the fourth photoresist layer (S118);

(27) forming a second circuit (S119);

(28) removing the fourth photoresist layer (S120);

(29) removing the third plating layer (S121).

(30) Further with reference to FIGS. 1 and 2A-2V, in FIG. 2A, as recited in the step (S100), a first substrate 10 is provided, and a first plating layer 11 is mounted on a surface of the first substrate 10, and a first photoresist layer 12 is mounted on the first plating layer 11.

(31) In FIG. 2B, as recited in the step (S101), the first photoresist layer 12 is patterned to form a groove of a first circuit pattern in the first photoresist layer 12. The first plating layer 11 is exposed in the groove of the first circuit pattern.

(32) In FIG. 2C, as recited in the step (S102), a first circuit 13 is formed in the groove of the first circuit pattern by plating the first plating layer 11 to fill the groove of the first circuit pattern.

(33) In FIG. 2D, as recited in the step (S103), the first photoresist layer 12 is removed to expose to first plating layer 11, and to maintain the first circuit 13. A portion of the first plating layer 11 is uncovered by the first circuit 13.

(34) In FIG. 2E, as recited in the step (S104), a portion of the first plating layer 11 that is uncovered by the first circuit 13 is removed, and the first circuit 13 and a portion of the first plating layer 11 that is covered by the first circuit 13 are maintained. A portion of the first substrate 10 is uncovered by the first circuit 13 and the first plating layer 11.

(35) In FIG. 2F, as recited in the step (S105), a second photoresist layer 20 is formed on the first substrate 10 to cover the first circuit 13 and the portion of the first plating layer 11 that is covered by the first circuit 13.

(36) In FIG. 2Q as recited in the step (S106), the second photoresist layer 20 is patterned to form at least one via 201 to expose a top surface of the first circuit 13.

(37) In FIG. 2H, as recited in the step (S107), a second plating layer 21 is formed on a surface of the second photoresist layer 20.

(38) In FIG. 2I, as recited in the step (S108), at least one connecting pillar 202 that fills the at least one via 201 is formed by plating a portion of the first circuit 13 connected by the at least one via 201 and the second plating layer 21.

(39) In FIG. 2J, as recited in the step (S109), a third photoresist layer 22 is formed on the at least one connecting pillar 202 and the plated second plating layer 21.

(40) In FIG. 2K, as recited in the step (S110), the third photoresist layer 22 is patterned to cover at least one top of the at least one connecting pillar 202 and to expose the plated second plating layer 21.

(41) In FIG. 2L, as recited in the step (S111), the exposed and plated second plating layer 21 is removed.

(42) In FIG. 2M, as recited in the step (S112), the third photoresist layer 22 is removed.

(43) In FIG. 2N, as recited in the step (S113), the second photoresist layer 20 is removed.

(44) In FIG. 2O, as recited in the step (S114), a second substrate 30 is formed on the first substrate 10 to cover the first circuit 13 and the at least one connecting pillar 202.

(45) In FIG. 2P, as recited in the step (S115), the second substrate 30 is drilled by laser to expose the top of the at least one connecting pillar 202.

(46) In FIG. 2Q, as recited in the step (S116), a third plating layer 31 is formed on the surface of the second substrate 30. The third plating layer 31 is electronically connected to the at least one connecting pillar 202.

(47) In FIG. 2R, as recited in the step (S117), a fourth photoresist layer 32 is formed on the surface of the third plating layer 31.

(48) In FIG. 2S, as recited in the step (S118), the fourth photoresist layer 32 is patterned to form a groove of a second circuit pattern. The top of the at least one connecting pillar 202 and at least one portion of a top surface of the third plating layer 31 are exposed in the groove of the second circuit pattern.

(49) In FIG. 2T, as recited in the step (S119), a second circuit 33 in the groove of the second circuit pattern is formed by plating the third plating layer 31. The second circuit 33 is electronically connected to the at least one connecting pillar 202 and the third plating layer 31.

(50) In FIG. 2U, as recited in the step (S120), the fourth photoresist layer 32 is removed.

(51) In FIG. 2V, as recited in the step (S121), a portion of the third plating layer 31 that is uncovered by the second circuit 33 is removed, and the second circuit 33 and a portion of the third plating layer 31 that is covered by the second circuit 33 are maintained. A portion of the second substrate 30 is uncovered by the second circuit 33 and the third plating layer 31.

(52) When the first to fourth photoresist layers 12, 20, 22, 32 are patterned, the first to fourth photoresist layers 12, 20, 22, 32 are processed by exposure and development to form the first to fourth photoresist layers 12, 20, 22, 32 having specific patterns.

(53) When the first to fourth photoresist layers 12, 20, 22, 32 are removed, the first to fourth photoresist layers 12, 20, 22, 32 are removed by stripper.

(54) When the first to third plating layers 11, 21, 31 are removed, the first to third plating layers 11, 21, 31 are removed by etchant.

(55) In the embodiment, the first to fourth photoresist layers 12, 20, 22, 32 are dry films.

(56) In the present invention, the second photoresist layer 20 is patterned to form the at least one via 201, and the at least one connecting pillar 202 is formed by plating the second plating layer 21 to fill the at least one via 201 before the second substrate 30 is formed. Therefore, when the second circuit 33 is formed, the fourth photoresist layer 32 may not need to be patterned to match the at least one via 201, and the second circuit 33 may be directly electronically connected to the at least one connecting pillar 202 to connect to the first circuit 13.

(57) Besides, the second substrate 30 is formed after the at least one connecting pillar 202 is formed, and the at least one top of the at least one connecting pillar 202 is exposed out of the surface of the second substrate 30. When the second circuit 33 is formed by plating the third plating layer 31, the at least one via 201 does not need to be filled, and the second circuit 33 is formed on the at least one top of the at least one connecting pillar 202 and the surface of the second substrate 30. Then, a top surface of the second circuit 33 may be flat. Therefore, when a circuit board is welded at the second circuit 33, the circuit board may be well welded at the second circuit 33 because of an even surface, and the circuit board may be firmly welded at the second circuit 33.

(58) In the embodiment, an area of the patterned third photoresist layer 22 that covers the at least one via 201 is greater than a section area of the at least one via 201. When the exposed and plated second plating layer 21 is removed, the unexposed second plating layer 21 is connected to the at least one connecting pillar 202, and an area of the unexposed second plating layer 21 that is not removed is greater than a section area of the at least one connecting pillar 202. Therefore, an area of the at least one connecting pillar 202 exposed out of the surface of the second substrate 30 is greater than an area of the at least connecting pillar 202 connected to the first circuit 13. When the second circuit 33 is formed, the second circuit 33 has a greater connecting area to connect the at least one connecting pillar 202, and the second circuit 33 may connect to the first circuit 13 through the at least one connecting pillar 202 with the greater connecting area.

(59) In conclusion, the at least one via 201 is fully filled to form the at least one connecting pillar 202, and the connecting area between the second circuit 33 and the at least one connecting pillar 202 is increased. Therefore, connection strength between the first circuit 13 and the second circuit 33 may be raised. Further, a yield rate of the landless multilayer circuit board may be raised.

(60) With reference to FIG. 3, the landless multilayer circuit board of the present invention comprises a first substrate 10, a first circuit 13, at least one connecting pillar 202, a second substrate 30, and a second circuit 33.

(61) The first circuit 13 is mounted on a surface of the first substrate 10. The at least one connecting pillar 202 is connected to the first circuit 13. The second substrate 30 is mounted on the surface of the first substrate 10 and covers the first circuit 13 and the at least one connecting pillar 202. At least one top of the at least one connecting pillar 202 is exposed out of a surface of the second substrate 30, and an area of a portion of the at least one connecting pillar 202 that is exposed out of the surface of the second substrate 30 is greater than an area of a portion of the at least one connecting pillar 202 that is connected to the first circuit 13. The second circuit 33 is mounted on the surface of the second substrate 30 and the at least one connecting pillar 202, and is connected to the portion of the at least one connecting pillar 202 that is exposed out of the surface of the second substrate 30.

(62) The at least one top of the at least one connecting pillar 202 is exposed out of the surface of the second substrate 30, and the portion of the at least one connecting pillar 202 that is exposed out of the surface of the second substrate 30 is at a same plane with the surface of the second substrate 30. Therefore, the second circuit 33 may be flatly formed. When a circuit board is welded at the second circuit 33, the circuit board may be firmly welded at the second circuit 33.

(63) Further, since the area of the portion of the at least one connecting pillar 202 that is exposed out of the surface of the second substrate 30 is greater than the area of the at least one connecting pillar 202 connected to the first circuit 13, the second circuit 33 may be firmly connected to the at least one connecting pillar 202, and be firmly connected to the first circuit 13 through the firmly connected at least one connecting pillar 202. Therefore, a yield rate of the landless multilayer circuit board may be raised.

(64) Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only. Changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.