Method for cycle accurate data transfer in a skewed synchronous clock domain

Abstract

A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address resister. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.

Claims

1. A method for performing data write and data read operations on a data register in a skewed synchronous clock domain, said method comprising the following steps: initializing on reset, Least Significant Bit (LSB) of a write address register to 1, and initializing remaining bits of the write address register to 0, such that the LSB of the write address register holds 1 and at least a Most Significant Bit (MSB) of the write address register holds 0; initializing on the reset, Least Significant Bit (LSB) of a read address register to 1, and initializing remaining bits of the read address register to 0, such that the LSB of the read address register holds 1, and at least a Most Significant Bit (MSB) of the read address register holds 0; issuing a source clock after the reset and extracting data stored in a memory location pointed to by a write address register bit storing a value 1, and preparing for extracted data to be pushed into the data register; inverting original bits of said write address register and generating inverted bits, and performing a first AND operation between the inverted bits and contents previously stored in the data register, and generating a first bit pattern as a resultant of said first AND operation; performing a second AND operation between the original bits of the write address register and the data to be pushed into the data register, and generating a second bit pattern as a resultant of said second AND operation; performing a first OR operation on said first bit pattern and second bit pattern, and updating the data register based on resultant of said first OR operation; issuing a skewed source synchronous clock after the reset, and performing an AND operation between bits of the read address register and the contents stored in the data register, and generating a third bit pattern; performing a second OR operation on said third bit pattern, and reading data stored in the data register, based on resultant of said second OR operation.

2. The method as claimed in claim 1, wherein the method further includes the step of rotating the Least Significant Bit (LSB) of the write address register and the read address register by at least one position per one active clock edge.

3. The method as claimed in claim 1, wherein the step of inverting the original bits of said write address register, further includes the step of inverting the original bits using an AND gate with bubble logic.

4. The method as claimed in claim 1, wherein the step of preparing extracted data to be pushed into the data register, further includes the step of pushing the extracted data into the data register, based at least on a position of the write address register bit storing the value 1.

5. The method as claimed in claim 1, wherein the method further includes the following steps: selecting the number of bits in the write address register and the read address register, based on the phase shift between the source clock and the destination clock; and selecting number of bits in the data register to be equivalent to the number of bits in the write address register and the read address register.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The other objects, features and advantages will occur to those skilled in the art from the following description of the preferred embodiment and the accompanying drawings in which:

(2) FIG. 1 illustrates a timing diagram to show the data reliability issue when transferring data from one clock domain to a skewed source synchronous clock domain, in accordance with the present disclosure;

(3) FIG. 2A illustrates the 1-hot, variable depth write address register, in accordance with the present disclosure;

(4) FIG. 2B illustrates the 1-hot, variable depth read address register, in accordance with the present disclosure;

(5) FIG. 3 illustrates write function to a data register, in accordance with the present disclosure; and

(6) FIG. 4 illustrates a read function of the data register, in accordance with the present disclosure.

(7) FIG. 5 illustrates the method to achieve cycle accurate data transfer between source synchronous skewed clock domains

(8) Although the specific features of the present invention are shown in some drawings and not in others, this is done for convenience only as each feature may be combined with any or all of the other features in accordance with the present disclosure.

DETAILED DESCRIPTION

(9) FIG. 1 illustrates a timing chart to show the data reliability issue when transferring data from source clock domain to a skewed source synchronous clock domain of a digital system, according to one embodiment of the present disclosure.

(10) The timing chart 100 as shown in FIG. 1 illustrates the clock signals of the source clock and the (source synchronous skewed) destination clock. As illustrated in the timing diagram 100, the destination clock has a large skew symbolically represented by 110. As illustrated in the timing diagram 100, any data launched from the t.sub.1 edge of the source should be captured on the t.sub.2 edge of the destination. If the skew between the (source and destination) clocks is large, the digital system has no means to detect the correct destination t.sub.2 edge as the t.sub.1 destination edge appears near to the t.sub.2 source edge. Instead of the data being captured on the t.sub.2 destination edge, the data is susceptible to be captured on the t.sub.1 destination edge. Alternatively, the data capture by the t.sub.2 can take place even early based on the skew of the system. This leads to the error in the data read and write mechanism.

(11) FIG. 2A illustrates the 1-hot, variable depth write register 210, in accordance with the present disclosure. The write address register 210 is 1-hot encoded set of registers that holds the current address of the data that has to be written into the data register. 1-hot encoding refers to one of the bits in the register set to 1, and the rest of the bits of the register set to 0. Examples of the 1-hot encoding of the registers include 00000001, 10000000, 00010000, and the like.

(12) In accordance with the present disclosure, on reset 230, the least significant bit (LSB) position of write address register 210 holds the value 1 and the other positions including the most significant bit (MSB) hold the value 0. On every active clock edge, the LSB of the write address register 210 rotates in a circular manner with the LSB data moved to the MSB position and the MSB data is moved to position MSB-1 and so on.

(13) FIG. 2B illustrates the 1-hot, variable depth read address register 220, in accordance with the present disclosure. The read address register 220 is 1-hot encoded set of registers that holds the current address of the data that has to be read from the data register. In accordance with the present disclosure, on reset 230, the least significant bit (LSB) position of the read address register 220 holds the value 1 and the other positions including the most significant bit (MSB) hold the value 0. On every active clock edge, the LSB of the read address register 220 rotates in a circular manner with the LSB data moved to the MSB position and the MSB data is moved to MSB-1 and so on.

(14) FIG. 3 illustrates the implementation of a write function on the data register 310, in accordance with the present disclosure. FIG. 3 includes a write address register 210, a data register 310, a plurality of AND gates 320, 325 with bubble logic, a plurality of AND gates 340, 345 without bubble logic, a plurality of OR gates 330, 335, and a clock source 350.

(15) In accordance with the present disclosure, a reset signal is applied to initialize the write address register 210 and the read address register 220 to point out to a memory location 0. The clock source 350 is stopped to disable active clock edges to both the write address register 210 and the read address register 220 during the reset to ensure clock and reset timing relationship. The clock source 350 is started after the reset active clock edges are delivered to the write address register 210, the read address register 220 and the data register 310.

(16) In accordance with the present disclosure, on every active source clock edge, the data register 310 is updated as described herein: based on the current 1-hot bit position of the write address register 210, the new data (either 0 or 1) is pushed into a bit position of the data register 310. For example, if the write address register (w.sub.adr) 210 forms a pattern 000100, the data register (d.sub.atar) 310 forms a pattern 110001, the new data (n.sub.data) 360 to be transferred is 1. The new value (n.sub.datar) of data register 310 is given be a Boolean equation: n.sub.datar=(w.sub.adr.Math.n.sub.data)|(|w.sub.adr.Math.d.sub.atar), which is 110101 in this example. Subsequently, the write address register 210 is shifted to point to the next memory location. In accordance with the present disclosure, both 0 and 1 are considered active data to be transferred.

(17) FIG. 4 illustrates an implementation of a read function of the data register, in accordance with the present disclosure. FIG. 4 includes a read address register 220, the data register 310, plurality of AND gates 410 and 415, an OR gate 420, new data 430, a skewed source synchronous clock 440. On every active skewed clock edge, the read functionality is achieved using the steps mentioned herein: based on the current 1-ho: bit position of read address register 220, the data is read from the data register 310. For example, if the read address register (r.sub.adr) is 001000, and the data register (d.sub.atar) is 110001, then the new data (n.sub.data) is given by Boolean equation: n.sub.data=(r.sub.datr.Math.d.sub.atar), which is 0 in this example. Subsequently, the read address register 220 is shifted to point to next location.

(18) Further, in accordance with the present disclosure, there are address increments on every active edge of the clock. Due to the delayed nature of the (source synchronous skewed) clock reaching the read address register 220, the write address register 210 increments first and stores data into the data register subsequently followed by reading the data register 310 based on read address register 220. Further, according to the present disclosure, the depth of the read address register, write address register and data register is equivalent and depends on the skew of the clock source.

(19) Referring to FIG. 5, there is shown a flowchart illustrating the method for performing data write and data read operations on a data register in a skewed synchronous clock domain. The method, in accordance with the present disclosure comprises the following steps: initializing on reset, Least Significant Bit (LSB) of a write address register to 1, and initializing remaining bits of the write address register to 0, such that the LSB of the write address register holds 1 and at least a Most Significant Bit (MSB) of the write address register holds 0 (step 500); initializing on reset, Least Significant Bit (LSB) of a read address register to 1, and initializing remaining bits of the read address register to 0, such that the LSB of the read address register holds 1, and at least a Most Significant Bit (MSB) of the read address register holds 0 (step 502). issuing source clock after reset and pushing data into the data register based at least on the position of a write address register bit storing a value 1 (step 504); inverting the original bits of the write address register and generating inverted bits, and performing a first AND operation between the inverted bits and contents stored in the data register, and generating a first bit pattern as a resultant of the first AND operation (step 506); performing, a second AND operation between the original bits of the write address register and data pushed into the data register, and generating a second bit pattern as a resultant of the second AND operation (step 508); performing a first OR operation on the first bit pattern and second bit pattern, and updating the data register based on resultant of the first OR operation (step 510); issuing skewed source synchronous clock after reset and performing an AND operation between the bits of the read address register and the contents stored data register, and generating a third bit pattern (step 512); performing a second OR operation on the third bit pattern, and reading data stored in the data register, based on resultant of the second OR operation (step 514).

(20) In accordance with the present disclosure, the method further includes the step of rotating the Least Significant Bit (LSB) of the write address register and the read address register by at least one position per one active clock edge.

(21) In accordance with the present disclosure, the step of inverting the original bits of the write address register, further includes the step of inverting the original bits using an AND gate with bubble logic.

(22) In accordance with the present disclosure, the step of pushing data into the data register, further includes the step of extracting the data stored in a memory location pointed to by the write address register bit storing the value 1.

(23) In accordance with the present disclosure, the method further includes the step of selecting the number of bits in the write address register and the read address register, based on the phase shift between the source clock and the destination clock.

(24) In accordance with the present disclosure, the method further includes the step of selecting the number of bits in the data register to be equivalent to the number of bits in the write address register and the read address register.

(25) The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, those skilled in the art will recognize that the embodiments herein can be practiced with modifications.

(26) The technical advantages envisaged by the present disclosure include the realization of a system and method that enables cycle accurate data transfer. Further, the system and method envisaged by the present disclosure also provides for cycle accurate data transfer between skewed source synchronous clock domains. Further, the system and method obviate the skew and the corresponding repercussions during data transfer between different clock domains. Further, the system and method provide for maintaining an accurate timing relationship during data transfer between different clock domains. Further, the system and method do not bring about addition of variable latency and necessitate availability of additional clock cycles.