Mechanical Oscillator and Associated Production Method

Abstract

A mechanical oscillator endowed with a strip, with the aforesaid strip incorporating a first silicon layer having a crystal lattice extending along a first direction of one plane, a thermal compensation layer composed of a material having a Young's modulus thermal coefficient of opposite sign to that of the silicon, and a second silicon layer having a crystal lattice extending in a second direction of the plane, with the first and direction being offset at an angle of 45° within the plane of the layers, and with the thermal compensation layer extending between the first and second silicon layers.

Claims

1. A mechanical oscillator endowed with a strip, the strip comprising: a first silicon layer having a crystal lattice extending along a first direction of a plane; and a thermal compensation layer made of a material having a thermal coefficient of the Young's modulus of opposite sign to that of the silicon; wherein the strip also comprises a second silicon layer having a crystal lattice extending along a second direction of the plane, the first and the second direction being offset by an angle of 45° within the plane of the layers, and the thermal compensation layer extending between the first and second silicon layers.

2. A mechanical oscillator according to claim 1, wherein the strip comprises: a third silicon layer comprising a crystal lattice extending in a third direction parallel to the direction of the first silicon layer; and a second thermal compensation layer made of a material having a thermal coefficient of the Young's modulus of opposite sign to that of the silicon; with each thermal compensation layer being located between two superposed silicon layers; with the direction of the second silicon layer located between the two other silicon layers being offset by an angle of 45° in relation to the direction of the other two silicon layers.

3. A mechanical oscillator according to claim 1, wherein the strip comprises an outer thermal compensation layer made of a material having a Young's modulus thermal coefficient of opposite sign to that of the silicon.

4. A mechanical oscillator according to claim 1, wherein the thermal compensation layer, of which the material has a thermal coefficient of the Young's modulus of opposite sign to that of the silicon, is manufactured in Silicon oxide.

5. A mechanical oscillator according to claim 1, wherein the volume ratio between the material having a Young's modulus thermal coefficient of opposite sign to that of the silicon and the silicon layers is between 20% and 30% at an ambient temperature of approximately 20° C.

6. A mechanical oscillator according to claim 1, wherein the mechanical oscillator is a spiral spring designed to equip the rocker arm of a mechanical clockwork assembly and formed from a spiral strip.

7. A method for manufacturing a mechanical oscillator endowed with a strip comprising a first silicon layer having a crystal lattice extending along a first direction of a plane, a thermal compensation layer made of a material having a thermal coefficient of the Young's modulus of opposite sign to that of the silicon, wherein the strip also comprises a second silicon layer having a crystal lattice extending along a second direction of the plane, the first and second direction being offset by an angle of 45° within the plane of the layers and the thermal compensation layer extending between the first and second silicon layers, the method comprising: etching a pattern of the mechanical oscillator onto the first silicon layer and onto the thermal compensation layer and the second silicon layer.

8. A method for manufacturing a mechanical oscillator in accordance with claim 7, the method further comprising: depositing a thermal compensation layer on a first silicon layer of a first silicon-on-insulator wafer; etching the pattern of the mechanical oscillator onto the thermal compensation layer and onto the first silicon layer of the first silicon-on-insulator wafer; sealing a second silicon-on-insulator wafer onto the first silicon wafer, with a rotation of 45° in relation to the first silicon wafer, such that a second silicon layer of the second silicon wafer is in contact with the thermal compensation layer; removing a substrate and an insulator layer of the first silicon-on-insulator wafer; etching the second silicon layer of the second silicon wafer, using the first silicon layer as a mask; and removing a substrate and an insulator layer of the second silicon-on-insulator wafer; the first and second silicon-on-insulator silicon wafer consisting of a substrate topped by an insulator layer followed by one of the aforesaid first or second monocrystalline silicon layers.

9. A method for manufacturing a mechanical oscillator in accordance with claim 7, the method further comprising: depositing a first part of a thermal compensation layer onto a first silicon layer of a first silicon-on-insulator wafer; depositing a second part of the thermal compensation layer onto a second silicon layer of a second silicon-on-insulator wafer; etching the pattern of the mechanical oscillator onto the first part (Cop1) of the thermal compensation layer, and onto the first silicon layer of the first silicon-on-insulator wafer; etching the mechanical oscillator pattern onto the second part of the thermal compensation layer, and onto the second silicon layer of the second silicon-on-insulator wafer; sealing the second silicon wafer onto the first silicon wafer, with a rotation of 45° in relation to the first silicon wafer, such that the two parts of the thermal compensation layer are in contact; removing a substrate and an insulator layer of the second silicon-on-insulator wafer; and removing a substrate and an insulator layer of the first silicon-on-insulator wafer; the first and second silicon-on-insulator wafers consisting of a substrate topped by an insulator layer followed by one of the aforesaid first or second monocrystalline silicon layers.

10. A method for manufacturing a mechanical oscillator in accordance with claim 7, the method further comprising: etching the pattern of the mechanical oscillator onto a first silicon layer, a second insulator layer and a second silicon layer of a silicon wafer of dual silicon-on-insulator type; and removing a substrate and a first insulator layer of the silicon wafer; with the first silicon-on-insulator wafer consisting of a substrate toped by a first insulator layer, a first monocrystalline silicon layer of a second insulating layer followed by a second monocrystalline silicon layer, with the first and second silicon layers of the dual silicon-on-insulator wafer comprising crystal lattices of which the directions are offset at an angle of 45°.

11. A method for manufacturing a mechanical oscillator in accordance with claim 7, the method further comprising: etching the pattern of the mechanical oscillator onto a second silicon layer and a second insulator layer of a first dual silicon-on-insulator wafer; sealing a second silicon wafer onto the second silicon layer of the first silicon wafer; removing a substrate and a first insulator layer of the first silicon wafer; etching the pattern of the mechanical oscillator onto a first silicon layer of the first silicon wafer; and removing the second silicon wafer; with the first dual silicon-on-insulator wafer consisting of a substrate topped by a first insulator layer, a first monocrystalline silicon layer, a second insulator layer followed by a second monocrystalline silicon layer, with the first and second silicon layers of the dual silicon-on-insulator wafer comprising crystal lattices of which the directions are offset at an angle of 45°; with the second silicon wafer being composed of a single silicon layer that may or may not be topped by an insulating layer.

12. A method for manufacturing a mechanical oscillator in accordance with claim 7, the method further comprising: depositing a thermal compensation layer on a silicon layer of a first silicon-on-insulator wafer; etching the pattern of the mechanical oscillator onto the thermal compensation layer and onto the silicon layer of the first silicon wafer; sealing a second silicon wafer comprising the aforesaid second silicon layer onto the first silicon wafer, with a rotation of 45° in relation to the first silicon wafer, such that the second silicon wafer is in contact with the thermal compensation layer; thinning the second silicon wafer; etch the pattern of the mechanical oscillator onto the second silicon wafer; and removing a substrate and an insulator layer of the first silicon wafer; with the first silicon-on-insulator wafer consisting of a substrate topped by an insulator layer followed by a monocrystalline silicon layer; with the second silicon wafer being composed of a single silicon layer that may or may not be topped by an insulating layer.

13. A method for manufacturing a mechanical oscillator in accordance with claim 7, the method further comprising: thinning a substrate forming the aforesaid second silicon layer of a silicon-on-insulator wafer; etching the pattern of the mechanical oscillator onto a silicon layer of the silicon wafer; depositing a structuring layer onto the substrate of the silicon wafer; etching the pattern of the mechanical oscillator onto a substrate and an insulator layer of the silicon wafer, using the first silicon layer as a mask; and removing the structuring layer of the substrate of the silicon wafer; with the silicon-on-insulator wafer consisting of a silicon substrate topped by an insulator layer followed by a monocrystalline silicon layer, with the first silicon layer and the silicon substrate of the silicon-on-insulator wafer having crystal lattices of which the directions are offset at a 45° angle.

14. A method for manufacturing a mechanical oscillator in accordance with claim 8, further comprising an additional step of oxidation of the strip.

15. A method for manufacturing a mechanical oscillator in accordance with claim 8, further comprising an additional step consisting in affixing a second thermal compensation layer and a third silicon layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The manner of implementation of the disclosed embodiments and the advantages accruing therefrom will come clearly to the fore in the implementation that follows, with the aid of the appended drawings, in which FIGS. 1 to 12 depict the following:

[0049] FIG. 1 is a cross-sectional view of a strip of a mechanical oscillator, in accordance with a first embodiment;

[0050] FIG. 2 is a schematic representation of the various directions of the axes of the crystal lattice on a silicon wafer of <100> type;

[0051] FIG. 3 is a representation of the mechanical characteristics of one of the two silicon layers of the strip in FIG. 1, according to the direction in the plane of the center line of the crystal lattice;

[0052] FIG. 4 is a cross-sectional view of a strip of a mechanical oscillator according to a second embodiment;

[0053] FIG. 5 is a cross-sectional view of a strip of a mechanical oscillator according to a third embodiment;

[0054] FIG. 6 is a cross-sectional view of a strip of a mechanical oscillator according to a fourth embodiment;

[0055] FIG. 7 is a schematic illustration of the manufacturing process for the strip in FIG. 1, according to one first embodiment;

[0056] FIG. 8 is a schematic illustration of the manufacturing process for the strip in FIG. 1, according to a second embodiment;

[0057] FIG. 9 is a schematic illustration of the manufacturing process for the strip in FIG. 1, according to a third embodiment;

[0058] FIG. 10 is a schematic illustration of the manufacturing process for the strip in FIG. 1, according to a fourth embodiment;

[0059] FIG. 11 is a schematic illustration of the manufacturing process for the strip in FIG. 1, according to a fifth embodiment; and

[0060] FIG. 12 is a schematic illustration of the manufacturing process for the strip in FIG. 1, according to a sixth embodiment.

DETAILED DESCRIPTION

[0061] FIG. 1 illustrates a strip (11) of a mechanical oscillator—in the form of a straight segment, a helicoid or a spiral, for example—incorporating a stack of three layers: a first layer of monocrystalline silicon (Cs1) in direct contact with a thermal compensation layer (Co1) in direct contact with a second monocrystalline silicon layer (Cs2). The first silicon layer (Cs1) extends over a height hs1 and over the entire width L of the strip (11). The second silicon layer (Cs2) extends over a height hs2 essentially the same as height hs1, and over the entire width L of the strip (11). The thermal compensation layer (Co1) extends over a height hot that is much smaller than the two heights hs1 and hs2, and over the entire width L of the strip (11).

[0062] The two silicon layers (Cs1, Cs2) incorporate two identical crystal lattices. Each crystal lattice of each silicon layer (Cs1, Cs2) has a predetermined direction (Ds1, Ds2). The term “direction” of the silicon layers is deemed to mean the direction of a crystal lattice in which the crystal lattice has a maximal Young's modulus in the plane of the corresponding silicon layer (Cs1, Cs2).

[0063] The hatchings in FIGS. 1, 4, 5 and 6 provide a schematic illustration of the offsets between the directions (Ds1, Ds2 and Ds3).

[0064] However, the offsets between the directions (Ds1, Ds2 and Ds3) are in the plane of the silicon layers (Cs1, Cs2 and Cs3) and, therefore, are not visible in the same way in a true-to-life cross-sectional view of the strip (11). The phrase “a crystal lattice extends in one direction” means that the crystal lattice incorporates a crystalline structure of which the maximum Young's modulus is attained in the predetermined direction.

[0065] FIG. 2 illustrates a monocrystalline network, of <100> type, of the first silicon layer (Cs1) modeled in accordance with three linear springs. For a crystal lattice of the <100> type, the mechanical strength of the first silicon layer (Cs1) in the crystalline direction [−110] of the x axis, and in the crystalline direction [−1−10] of they axis is greater than the mechanical strength in the crystalline directions [100] of the x1 axis and [010] of the y1 axis. FIG. 3 illustrates the mechanical characteristics of a wafer of <100> type, as a function of the angular direction of a force F identified in the plane of the crystal lattice of <100> type at constant temperature. E represents the variation of the Young's modulus. This mechanical magnitude has local maxima in the <110> and <1 10> directions, and local minima in the <100> and <010> directions. From this, one can thus deduce that the stiffness of the <100>-type crystal lattice of the first silicon layer (Cs1) differs in the x [−110] and y1 [010] directions. This stiffness is identical between the x [−110] and y [−1−10] directions.

[0066] Given the thickness of the thermal compensation layer (Co1), the mechanical properties of the strip (11) largely depend on the mechanical properties of the two silicon layers (Cs1, Cs2). If the two silicon layers (Cs1, Cs2) have the same crystalline orientation and the same height, such that hs1=hs2, the strength F.sub.tot X of the strip (11) in the x [−110] direction is equal to the sum of the strengths (F1, F2) of the two silicon layers (Cs1, Cs2). The Young's modulus E.sub.−110 in the direction x [−110] of the two silicon layers (Cs1, Cs2) being identical, the strengths F1 and F2 are also identical, such that:

[00003]$F_1=F_2=\frac{\mathrm{hs}.Math..Math.1\times L\times E_{-110}}{\mathrm{.Math.}};$

[0067] where ε represents the distortion coefficient.

[0068] The strength F.sub.tot X of the strip (11) in the direction x [−110] is therefore:

[00004]$F_{\mathrm{tot}.Math..Math.X}=F_1+F_2=\frac{2\times \mathrm{hs}.Math..Math.1\times L\times E_{-110}}{\mathrm{.Math.}}.$

[0069] This strength F.sub.tot X in the x [−110] direction is the same in the Y [−1−10] direction in the case of a single-core spiral.

[0070] However, the strength F.sub.tot y1 of the strip (11) in the y1 [010] direction is:

[00005]$F_{\mathrm{tot}.Math..Math.y.Math..Math.1}=F_1+F_2=\frac{2\times \mathrm{hs}.Math..Math.1\times L\times E_{010}}{\mathrm{.Math.}}.$

[0071] However, FIG. 3 shows that the Young's modulus E.sub.010 of the silicon layers (Cs1, Cs2) in the y1 [010] direction is less than the Young's modulus E.sub.−110 of the silicon layers (Cs1, Cs2) in the x [−110] direction, which gives rise to a difference in strengths is the x [−110] and y1 [010] directions. Thus, the strength F.sub.tot X of the strip (11) in the x [−110] direction is greater than the strength F.sub.tot y1 of the strip (11) in the y1 [010] direction. The strip (11) thus has a weakness in its strength in the y1 [010] direction.

[0072] The contemplated embodiments compensate for this difference in strength by shifting the directions (Ds1, Ds2) of the silicon layers (Cs1 and Cs2) by a 45° angle in the plane of the silicon layers (Cs1, Cs2). Thus, the Young's modulus in a given direction is different between the two layers (Cs1 and Cs2). For example, in the y1 [010] direction, the Young's modulus E.sub.−110 of the first silicon layer (Cs1) differs from the Young's modulus E.sub.010 of the second silicon layer (Cs2). The strength F.sub.tot X of the strip (11) in the direction x [−110] is therefore:

[00006]$F_{\mathrm{tot}.Math..Math.X}=F_1+F_2=\frac{\mathrm{hs}.Math..Math.1}{\mathrm{.Math.}}\times L\times \left(E_{-110}+E_{010}\right).$

[0073] The strength F.sub.tot y1 of the strip (11) in the y1 [010] direction is:

[00007]$F_{\mathrm{tot}.Math..Math.y.Math..Math.1}=F_1+F_2=\frac{\mathrm{hs}.Math..Math.1}{\mathrm{.Math.}}\times L\times \left(E_{010}+E_{1-10}\right).$

[0074] Given that E.sub.1-10 is equal to E.sub.−110, the strengths are identical in the two directions x [−110] and y1 [010]. The structure of the strip (11) in FIG. 1 thus provides identical mechanical characteristics in all the directions x, y and y1 of the crystal lattice.

[0075] The thermal compensation layer Co1 is composed of a material having a thermal coefficient of the Young's modulus of opposite sign to that of the silicon, such that the variation in mechanical strength of the silicon layers (Cs1, Cs2) as a function of temperature is at least partially compensated by the thermal compensation layer (Co1). The thermal compensation layer (Co1) is preferably made of silicon oxide. The thermal coefficient of the Young's modulus for silicon is −64.Math.10-6K-1, while the thermal coefficient of the Young's modulus for silicon oxide is 187,5.Math.10-6K-1 at an ambient temperature of around 20° C. Thus, to compensate—at least partially—the variation in mechanical strength of the silicon layers (Cs1, Cs2) as a function of temperature, the volume ratio between the thermal compensation layer (Co1) and the silicon layers (Cs1, Cs2) is at least 20% at an ambient temperature of around 20° C. In FIG. 1, the surface area of the ho1.L section is therefore at least 20% of the surface area of the sections L.hs1 and L.hs2.

[0076] FIG. 4 illustrates an embodiment in which the strip (11) incorporates three silicon layers (Cs1, Cs2, Cs3) intersected by two thermal compensation layers (Co1, Co2). The first and third silicon layers (Cs1, Cs3) have crystal lattices oriented in the same direction (Ds1, Ds3). The second silicon layer Cs2 located between the first and third silicon layer (Cs1, Cs3) incorporates a crystal lattice of which the direction (Ds2) is offset at a 45° angle to the directions (Ds1, Ds3). To procure identical mechanical characteristics in all directions (x, y and y1) of the crystal lattice, the height hs2 of the second silicon layer (Cs2) must be equal to the sum of the heights hs1 and hs3 of the other two silicon layers (Cs1, Cs3). In order to compensate—at least partially—for temperature variation, the sum of the heights ho1 and h02 must be at least 20% of the sum of the heights hs1, hs2 and hs3 in the case of silicon oxide.

[0077] FIGS. 5 and 6 illustrate a variant in which a thermal compensation layer is also positioned around the strip (11) of FIGS. 1 and 4. This implementation makes it possible to restrict the thickness of the thermal compensation layer (Co1) located between the silicon layers (Cs1, Cs2). For example, in the case of FIG. 5, the surface area of the thermal compensation layer includes the following areas:

[0078] Ho1.L, the area of the outer layer (Coe) above the strip (11);

[0079] Lo1.H, the area of the outer layer (Coe) on the left of the strip (11);

[0080] Lo2.H, the area of the outer layer (Coe) on the right of the strip (11);

[0081] Ho3.L, the area of the outer layer (Coe) below the strip (11), and

[0082] Ho2.L, area of the layer (Co1) between the silicon layers (Cs1, Cs2).

[0083] The sum of these surface areas must also be equal, in the case of silicon oxide, to at least 20% of the sum of the surfaces hs1.Ls and hs2.Ls of the silicon layers (Cs1, Cs2), to compensate for temperature variation. Thus, the thickness of the thermal compensation layers—namely the internal layer (Co1) and the outer layer (Coe)—is smaller than the implementation in FIG. 1. FIG. 6 illustrates an identical implementation in which the strip incorporates three silicon layers (Cs1, Cs2 and Cs3) as illustrated in FIG. 4.

[0084] FIGS. 7 to 12 illustrate manufacturing processes for the strip (11) in FIG. 1. The process in FIG. 7 uses two silicon wafers of silicon type on insulator SOI. Each silicon-on-insulator (SOI) wafer incorporates a substrate (Su1, Su2) topped with an insulator layer (C1, Ci2) followed by monocrystalline silicon layer (Cs1, Cs2). The substrate (Su1, Su2) can be made of silicon. In a first step (21), a thermal compensation layer (Co1) is deposited on the silicon layer (Cs1) of the first SOI wafer. In a second step (22), a pattern of the mechanical oscillator is etched on the thermal compensation layer (Co1) and on the silicon layer (Cs1). In a third step (23), the silicon layer (Cs2) of the second wafer is sealed onto the thermal compensation layer (Co1). The second wafer is offset by an angle of 45° in relation to the first wafer before this sealing step (23), so that the directions (Ds1, Ds2) of the crystal lattices are also offset by a 45° angle. In one step (24), the assembly is turned over and the substrate (Su1) and the insulator layer (01) of the first wafer are removed. In one step (25), the silicon layer (Cs2) of the second wafer is etched with the pattern of the mechanical oscillator, using the first silicon layer as etching mask. The etching can be performed by a deep reactive ion etching technique (also known as DRIE for “Deep Reactive Ion Etching”). The substrate (Su2) and the insulator layer (Ci2) of the second silicon wafer are then removed in a step (26), to release the mechanical oscillator.

[0085] FIG. 8 illustrates an implementation process that also uses two SOI wafers. In steps (32 and 33), two parts (Cop1, Cop2) of the thermal compensation layer (Co1) are deposited respectively on each silicon layer (Cs1, Cs2) of the two SOI wafers.

[0086] In steps (34 and 35), the patterns of the oscillator are then etched onto the two parts (Cop1 and Cop2) of the thermal compensation layer (Co1), as well as onto the two silicon layers (Cs1, Cs2) of the two wafers. In a step (36), the two parts (Cop1, Cop2) are then sealed with a 45° offset between the wafers, so as to form the complete thermal compensation layer (Co1). Steps (37, 38) consist in removing the two substrates (Su1, Su2), as well as the two insulator layers (Ci1, Ci2), to release the mechanical oscillator.

[0087] FIG. 9 illustrates an implementation process using a single dual-SOI wafer. A dual-SOI wafer consists of a substrate (Su1) topped by a first insulator layer (C1), a first monocrystalline silicon layer (Si1), a second insulator layer (Ci2) followed by a second monocrystalline silicon layer (Si2). The second insulator layer (Ci2) thus fulfills the function of the thermal compensation layer (Co1) of the strip (11). The first silicon layer (Cs1) and the second silicon layer (Cs2) incorporates crystal lattices of which the directions are offset by a 45° angle. A first step (41) consists of etching the pattern of the mechanical oscillator onto the first silicon layer (Cs1), the second insulator layer (Ci2) and the second silicon layer (Cs2). A second step (42) consists in removing the substrate (Su1) and the first insulator layer (Ci1), to release the mechanical oscillator.

[0088] FIG. 10 illustrates a variant of the process in FIG. 9, using a dual-SOI wafer. A first step (51) consists in etching the pattern of the mechanical oscillator onto the second silicon layer (Cs2) and the second insulator layer (Ci2). In a second step (52), a silicon wafer (Si2) is sealed onto the second silicon layer (Cs2). This silicon wafer (Si2) is a sacrificial layer that only acts as a medium for the structure, and it is eliminated in a subsequent step. In a step (53), the assembly is turned over, and the substrate (Su1) and the first insulating layer (Ci1) of the first wafer are removed. The pattern of the mechanical oscillator is etched on the first silicon layer (Cs1) in a step (54) and in a step (55) the silicon wafer (Si2) is removed, to release the mechanical oscillator.

[0089] This variant of the process in FIG. 9 can be implemented when the strip (11) is too thick and the etching step (41) does not enable the first silicon layer (Cs1) to be etched properly.

[0090] FIG. 11 illustrates an implementation process using an SOI wafer and a silicon wafer (Si2). In a first step (61), a thermal compensation layer (Co1) is deposited on the silicon layer (Cs1) of the first SOI wafer. In a second step (62), a pattern of the mechanical oscillator is etched onto the thermal compensation layer (Co1) and onto the silicon layer (Cs1). The silicon wafer (Si2) is then sealed with a 45° offset onto the thermal compensation layer (Co1) in a step (63). Step (64) consists in thinning the silicon wafer (Si2) until the height hs2 desired for the second silicon layer (Cs2) of the strip (11) of FIG. 1 is attained. In a step (65), the pattern of the mechanical oscillator is etched on the second silicon layer (Cs2) formed by the silicon wafer (Si2) and, in a step (66), the substrate (Su1) and the insulator layer (Ci1) are removed, to release the mechanical oscillator.

[0091] FIG. 12 illustrates an implementation process using a single wafer of SOI type, in which the substrate (Su1) is made of silicon and forms the second silicon layer (Cs2) of FIG. 1. The thermal compensation layer (Co1) is formed by the insulator layer (Ci1), which is preferably made of silicon oxide. A first step (71) consists in thinning the substrate (Su1) until the desired height hs2 for the second silicon layer (Cs2) of the strip (11) of FIG. 1 is attained. In a step (72), the pattern of the mechanical oscillator is etched on the silicon layer (Cs1). A structuring layer (Cst) is then deposited on the thinned substrate (Su1) in a step (73) to stiffen the structure, and then the pattern of the mechanical oscillator is etched onto the insulator (Ci1) and substrate (Su1) layers in a step (74). In a step (75), the structuring layer (Cst) is removed, to release the mechanical oscillator.

[0092] A variant of these processes can be adapted to implement one of the variants of FIGS. 4 to 6. For example, an outer thermal compensation layer (Coe) can be manufactured in a silicon oxidation chamber, thus forming a layer of silicon oxide around the strip (11). A second thermal compensation layer (Co2) and a third silicon layer (Cs3) can be manufactured—for example, by sealing a third wafer of silicon-on-insulator type, and by performing corresponding additional etching steps. The disclosed embodiments thus make it possible to procure a mechanical oscillator of which the stiffness is isotropic within the plane and independent of temperature, without increasing the size of the strip, and without using an isotropic silicon layer in the plane.