Dopant enhanced solar cell and method of manufacturing thereof
20200287065 ยท 2020-09-10
Assignee
Inventors
- Maciej Krzyszto Stodolny (Petten, NL)
- John Anker (Petten, NL)
- Martien Koppes (Petten, NL)
- Ingrid Gerdina Romijn (Petten, NL)
- Lambert Johan Geerligs (Petten, NL)
Cpc classification
H01L31/02245
ELECTRICITY
Y02E10/547
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L31/0745
ELECTRICITY
Y02P70/50
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y02E10/546
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L31/1804
ELECTRICITY
International classification
Abstract
The present invention relates to a dopant enhanced silicon based solar cell and method of manufacturing thereof. The solar cell includes on a surface of the silicon substrate a layer stack including a thin oxide layer and a polysilicon layer, the thin oxide layer being arranged as a tunnel oxide layer in-between the surface of the substrate and the polysilicon layer. The solar cell is provided with fire-through metal contacts arranged on the layer stack locally penetrating into the polysilicon layer. The silicon substrate is provided at the side of the surface with a dopant species that creates a dopant profile of a first conductivity type in the silicon substrate. The dopant profile in the silicon substrate has a maximal dopant level between about 110.sup.+18 and about 310.sup.+19 atoms/cm.sup.3 and a depth of at least 200 nm within the substrate to a dopant atom level of 110.sup.+17 atoms/cm.sup.3.
Claims
1. A solar cell based on a silicon substrate, comprising on a surface of the silicon substrate a layer stack comprising a thin oxide layer and a polysilicon layer, the silicon dioxide layer being arranged as a tunnel oxide layer in-between said surface of the silicon substrate and the polysilicon layer; the solar cell being provided with metal contacts arranged on the layer stack locally penetrating into the polysilicon layer; wherein the silicon substrate is provided at the side of said surface with a dopant species that creates a dopant profile of a first dopant species of a first conductivity type in the silicon substrate, and the dopant profile of the first dopant species in the silicon substrate has a maximal dopant level between about 110.sup.+18 and about 310.sup.+19 atoms/cm.sup.3 and at a depth of at least 200 nm within the silicon substrate has a dopant atom level of 110.sup.+17 atoms/cm.sup.3, wherein the metal contacts are fire-through metal contacts that locally fully penetrate the polysilicon as well as the thin oxide, resulting in local contacts between the metal and the silicon substrate, such that the metal contacts are locally in direct contact with the silicon substrate.
2. The solar cell according to claim 1, wherein the polysilicon layer is provided with a second dopant species of the first conductivity type having a dopant level in the polysilicon layer above the maximal dopant level in the silicon substrate.
3. The solar cell according to claim 2, wherein the dopant level in the polysilicon layer is between about 110.sup.+20 and about 310.sup.+20 atoms/cm.sup.3.
4. The solar cell according to claim 2, wherein the dopant level has a decreasing gradient between the polysilicon layer and the silicon substrate, across the silicon dioxide layer.
5. The solar cell according to claim 1, wherein the maximal dopant level in the silicon substrate is measured at about 50 nm below the interface of the silicon dioxide layer and the substrate.
6. The solar cell according to claim 1, wherein the depth of the dopant profile to the dopant level of 10.sup.+17 atoms/cm.sup.3 is between about 200 nm and about 1 m.
7. The solar cell according to claim 1, wherein the layer stack further comprises an hydrogen-rich dielectric coating layer on the surface of the polysilicon layer facing away from the silicon substrate.
8. The solar cell according to claim 7, wherein the hydrogen rich coating layer is selected from a group comprising a SiN.sub.x:H layer and an Al.sub.2O.sub.3 layer.
9. The solar cell according to claim 1, wherein the metal contacts are fire-through contacts, which penetrate during the firing step through a dielectric coating layer and into the polysilicon layer and are based on a fire-through metal paste.
10. (canceled)
11. The solar cell according to claim 4, wherein the dopant profile in the silicon substrate as function of depth in the silicon substrate is described by a Gaussian profile with the maximal dopant level positioned in the silicon substrate at a first distance from the interface of the silicon substrate and the thin oxide layer, and the maximal dopant level of the first dopant species in the silicon substrate is lower than an average dopant level of the second dopant species in the polysilicon layer by a factor of three or more.
12. The solar cell according to claim 2, wherein the second dopant species in the polysilicon layer is identical to the first dopant species in the silicon substrate.
13. The solar cell according to claim 1, wherein the first conductivity type is n-type, and the first dopant species and second dopant species are each selected from a group comprising P, As, and Sb.
14. The solar cell according to claim 1, wherein the polysilicon layer has a thickness between about 20 and about 300 nm.
15. The solar cell according to claim 1, wherein the thin oxide layer has a thickness of about 5 nm or less but at least three atomic layers.
16. A method for manufacturing a solar cell based on a silicon substrate, comprising: providing the silicon substrate; creating on said surface a layer stack comprising: creating a thin oxide layer on a surface of the silicon substrate, and creating a doped polysilicon layer on the thin oxide layer, the doped polysilicon layer containing a dopant species of a first conductivity type, such that the layer stack comprises the thin oxide layer arranged as a tunnel oxide layer in-between said surface of the silicon substrate and the doped polysilicon layer; the method further comprising: creating in a surface of the silicon substrate a dopant profile of a dopant species of the first conductivity type, wherein the creation of the dopant profile in the silicon substrate is done either in a first process preceding the creation of the doped polysilicon layer or in a second process simultaneously during the creation of the doped polysilicon layer, and wherein the dopant profile in the silicon substrate is created under such conditions that the dopant profile of the dopant species of the first conductivity type in the silicon substrate has a maximal dopant level between about 110.sup.+18 and about 310.sup.+19 atoms/cm.sup.3 and at a depth of at least 200 nm within the silicon substrate has a dopant atom level of about 110.sup.+17 atoms/cm.sup.3, wherein the method comprises creating on the layer stack metal contacts that locally penetrate into at least the polysilicon layer, wherein the metal contacts are created from a pattern of fire-through metal paste on the layer stack by a fire-through annealing step, such that the metal contacts are fire-through metal contacts that locally fully penetrate the polysilicon as well as the thin oxide, resulting in local contacts between the metal and the silicon substrate, and the metal contacts are locally in direct contact with the silicon substrate.
17. The method according to claim 16, further comprising: providing a dopant level of the dopant species of the first conductivity type in the polysilicon layer under such conditions that a dopant level in the polysilicon layer is above the maximal dopant level in the silicon substrate.
18. The method according to claim 16, wherein the maximal dopant level and the dopant atom level at the depth of at least 200 nm are obtained after completion of the doping and activation of the doped polysilicon layer.
19. The method according to claim 16, wherein the thin oxide layer is created by a process selected from a group comprising atomic layer deposition, high temperature oxidation, wet chemical oxidation, plasma oxidation or a reaction with ozone.
20. The method according to claim 16, wherein the first process for creating the dopant profile in the silicon substrate is a process selected from a group comprising: elevated temperature solid source diffusion of the dopant species, elevated temperature gas source diffusion of the dopant species, ion-implantation of the dopant species.
21. The method according to claim 16, further comprising: preceding the creation of the dopant profile in the silicon substrate, creating in the layer stack an anti-reflective layer on the surface of the polysilicon layer that is facing away from the silicon substrate, wherein the polysilicon layer is created by a chemical or physical vapour deposition process, and the dopant profile of the second doping species in the polysilicon layer is created by a process selected from a group comprising: co-deposition of the dopant species with the polysilicon, in-situ doping of the polysilicon, ion-implantation of the dopant species, gas source diffusion of the dopant species.
22. The method according to claim 18, further comprising a partial etch back of the silicon substrate preceding the creation of the layer stack.
23.-25. (canceled)
26. The method according to claim 16, further comprising: preceding the creation of the dopant profile in the silicon substrate, creating in the layer stack an anti-reflective layer on the surface of the polysilicon layer that is facing away from the silicon substrate
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The present invention will be discussed in more detail below, with reference to the attached drawings, in which:
[0016]
[0017]
[0018]
DESCRIPTION OF EMBODIMENTS
[0019]
The silicon substrate 10 has a front surface 2, intended for facing the Sun when in use, and a rear surface onto which a tunnel oxide layer 20 has been created. A thin oxide is commonly used as tunnel oxide material. The layer has a minimum thickness of about 1 nm, 3 atomic layers, and is maximised at around 5 nm. The silicon substrate is a doped silicon wafer, which has been doped in a pre-diffusion step and/or during doping of polySi resulting in the claimed dopant profile which is discussed with reference to
[0020] On top of the thin oxide layer 20, the polysilicon layer 30 has been deposited, such that the surface interface of the thin oxide layer and the silicon substrate 15 comprises the front surface of the thin oxide layer and the surface interface of the tunnel oxide layer and the polysilicon layer 25 comprises the rear surface of the thin oxide layer. The polysilicon layer is a doped layer, preferably of the n-type, created by a phosphorus dopant. However, a p-type dopant species such as boron dopant may also be used, resulting in a p-type doped layer. Further, the polysilicon layer may contain other additional elements such as carbon or oxygen atoms.
[0021] The anti-reflection layer 40, usually an anti-reflective coating, covers the free surface of the polysilicon layer. A metal contact 50 has been applied on the solar cell layer stack 1 such that it protrudes the anti-reflection layer 40 and part of the polysilicon layer 30. The metal contact is preferably a fire-through paste contact, since it is a low cost contact that can be applied using well established manufacturing technology, thereby contributing to the affordability of efficient solar cells. A FT metal contact may locally fully penetrate the polySi or the polySi as well as the thin oxide, resulting in local contacts between the metal and the Si substrate. This may enhance the intimate electrical contact between the FT contact and the substrate for charge carrier collection, improving the series resistance of the cell.
[0022]
[0023] The first section represents the dopant profile in the polysilicon layer 31, which is delimited by the interface 25 of the silicon dioxide layer and the polysilicon layer. The dopant level of the polysilicon layer is between about 110.sup.+20 and about 310.sup.+20 atoms/cm.sup.+3 and may be p- or n-type, depending on the base conductivity type of the silicon substrate.
[0024] The second section represents the dopant profile around and within the tunnel oxide layer 21, which is delimited on the first side by the interface 25 of the thin oxide layer and the polysilicon layer and on the second side by the interface 15 of the thin oxide layer and the silicon substrate. In this second section, the profile comprises a drop with inflection point, in the profile between the doped polysilicon and the profile in the silicon substrate, substantially across the thin oxide layer.
[0025] It should be noted that the dopant profile around and within the thin oxide layer is normally an laterally averaged quantity, as it is known that e.g. pinholes in the thin oxide can result in microscopic local lateral variations of the dopant concentration. A measurement method such as electrochemical profiling (ECV) or secondary ion mass spectrometry (SIMS) will show this laterally averaged quantity.
[0026] The third section represents the dopant profile within the silicon substrate 11, also called tail. The profile of the tail comprises a tail depth D of at least 200 nm, optionally up to about 1000 nm, as measured from the polysilicon interface up to a depth position where the dopant level is 110.sup.+17 atoms/cm.sup.3, and a peak dopant level in the silicon substrate of between 110.sup.+18 and 310.sup.+19 atoms/cm.sup.3. Thus the maximum, i.e., the peak dopant level, 12 is at least a factor three lower than the average dopant level in the polysilicon layer. The peak dopant level 12 should be determined sufficiently far away from the interface 15, e.g. 15 nm, to avoid smearing effects from measurement artefacts. For thinner layers of polysilicon the tail depth D is preferably larger than 200 nm to reach the desired effect of limited recombination at the interface 15.
[0027] As previously described, the dopant used is either be p-type or n-type, although n-type may be preferred. Obtaining the desired and required dopant profile tail may be an easier controllable process in n-type polysilicon.
[0028]
[0029] In
[0030] Further, this step may comprise a partial etch back of the silicon substrate after doping before later provision of the layer stack, to ensure the dopant profile indeed has a maximum concentration between 110.sup.+18 and about 310.sup.+19 atoms/cm.sup.3 and a depth of at least 200 nm to dopant atom level of 110.sup.+17 atoms/cm.sup.3.
[0031] In a next step 53 a thin oxide layer is created on the same surface the pre-diffusion step was previously performed on. The thin oxide layer is created by a process selected from a group comprising atomic layer deposition, high temperature oxidation or wet chemical oxidation, ozone oxidation, plasma oxidation, and consists of at least silicon oxide.
[0032] The following step 54 comprises the deposition of a polysilicon (polySi), using a chemical or physical vapour deposition process. This polysilicon layer is then doped 58 in a second doping step, using the same dopant as the first dopant species used for doping the silicon substrate, whereby the dopant profile as described for the first section 31 of
[0033] Next, a dielectric coating layer, preferably hydrogen-rich, is created 55 on the surface of the polysilicon layer facing away from the silicon substrate.
[0034] This step is followed by 56 creating on the dielectric coating layer a metal contact pattern which locally penetrates into the polysilicon layer. The metal contacts are created from a pattern of fire-through metal paste on the layer stack by a fire-through annealing step 57. The fire-through annealing step is carried out under conditions such that the metal contacts do not penetrate into the silicon dioxide layer or the silicon substrate. Alternatively, the fire-through annealing step results in metal contacts locally penetrating the polySi or the thin oxide and touching the silicon substrate, resulting in local direct contacts between the metal and the silicon substrate. Furthermore, the fire-through annealing step 57 is carried out such that the dopant profile in the silicon substrate is not significantly affected meaning that further diffusion of the dopant species in the silicon substrate is negligible.
[0035] Alternatively, the manufacturing process 301 may follow the steps shown in
[0036] In a further alternative manufacturing process 302, shown in
[0037] In each of the manufacturing processes 300, 301, 302 the dopant species profile in the silicon substrate is tuned to the meet the requirements set forth as above at the stage before metallization, e.g. after later process steps to dope and anneal the polySi layer.
[0038] The invention has been described with reference to the preferred embodiments. Although the dopant enhanced solar cell is described as having FT contacts, the invention is not limited thereto. The invented dopant profile is likely to provide a significant advantage or improvement for solar cells having contacts applied with technologies other than FT, firing through.
[0039] Also, although the invention has been described with respect to back side contacts of the solar cell, the invention can also be beneficially applied to contacts on a front side of a solar cell.
[0040] Further obvious modifications and alterations will occur to others upon reading and understanding the preceding detailed description. It is intended that the invention be construed as including all such modifications and alterations insofar as they come within the scope of the appended claims.