ELECTRIC CIRCUIT, ELECTRONIC MODULE FOR A CHIP CARD FORMED ON THE ELECTRIC CIRCUIT, AND METHOD FOR THE PRODUCTION OF SUCH AN ELECTRIC CIRCUIT

Abstract

An electrical circuit, for example a printed circuit, for producing a module for integration into a card such as a chip card. This module includes electrical contact or connector which includes lands for the connection and communication of the chip with a read/write system. To give them a white color, or a color close to white, these electrical contact lands are at least partially covered with a layer of a rhodium alloy. The invention also relates to a method for manufacturing such an electrical circuit.

Claims

1. An electrical circuit, in particular for producing chip card modules, comprising a substrate and at least one conductive track, this conductive track being at least partially covered with a visible surface layer formed of a rhodium alloy, deposited by electrodeposition on the conductive track, characterized by the fact that the concentration by weight of rhodium in the rhodium alloy is higher than or equal to 50% and by the fact that the rhodium alloy is deposited on at least one barrier layer deposited on the conductive track, prior to the deposition of the surface layer of the rhodium alloy by electrodeposition, this barrier layer comprising at least one of the elements from the following list: pure nickel, nickel-phosphorus alloy and cobalt-tungsten alloy.

2. The electrical circuit as claimed in claim 1, wherein the rhodium alloy comprises ruthenium.

3. The electrical circuit as claimed in claim 1, comprising a primer layer deposited on the barrier layer, and under the surface layer of the rhodium alloy, this primer layer comprising at least one of the metals, or at least one alloy of a metal, included in the following list: rhodium, ruthenium, palladium, silver and gold.

4. The electrical circuit as claimed in claim 3, wherein the thickness of the primer layer is less than or equal to 15 nanometers.

5. The electrical circuit as claimed in claim 1, wherein the thickness of the layer of rhodium alloy is between 10 nanometers and 150 nanometers.

6. An electronic module for a chip card, comprising an electrical circuit as claimed in claim 1, with a substrate and at least one conductive track forming a contact land that is electrically connected to the chip, wherein the conductive track is at least partially covered with a layer of rhodium alloy, the concentration by weight of rhodium in the alloy being higher than 50%, this layer of rhodium alloy being electrodeposited on a barrier layer deposited on the conductive track, prior to the deposition of the surface layer of the rhodium alloy by electrodeposition, this barrier layer comprising at least one of the elements from the following list: pure nickel, nickel-phosphorus alloy and cobalt-tungsten alloy.

7. A method for manufacturing an electrical circuit, in particular for producing chip card modules, comprising the following steps: providing a substrate; producing a conductive layer that at least partially covers the substrate, this conductive track being at least partially covered with a visible surface layer made of a rhodium alloy, deposited by electrodeposition on the conductive track, characterized by the fact that the concentration by weight of rhodium in the rhodium alloy is higher than or equal to 50% and by the fact that the layer of rhodium alloy is electrolytically deposited at least partly on a barrier layer comprising at least one of the materials from the list consisting of pure nickel, a nickel-phosphorus alloy and a cobalt-tungsten alloy.

8. The method as claimed in claim 7, wherein a primer layer is deposited on the barrier layer, prior to the deposition of the surface layer of the rhodium alloy by electrodeposition, this primer layer comprising at least one of the metals or at least one alloy of a metal included in the following list: rhodium, ruthenium, palladium, silver and gold.

9. The method as claimed in claim 7, wherein the conductive track comprises a set of contacts made by photolithography, before the deposition of the surface layer of the rhodium alloy by electrodeposition.

10. The method as claimed in claim 7, wherein the conductive track is produced by co-laminating a lead frame onto the substrate.

11. The method as claimed in claim 7, wherein the face of the substrate opposite that which is at least partially covered with the conductive layer is at least partially masked.

Description

[0025] Other features and advantages of the invention will become apparent upon reading the detailed description and the appended drawings, in which:

[0026] FIG. 1 schematically shows, in perspective, a chip card comprising an example of a module according to the invention;

[0027] FIG. 2 schematically shows, from above, a portion of an electrical circuit according to the invention, comprising a plurality of connectors for a chip card module;

[0028] FIG. 3 partially and schematically shows, in cross section, an example of a connector for a module such as that shown in FIG. 1;

[0029] FIGS. 4a to 4k schematically show steps of an example of the implementation of the method according to the invention; and

[0030] FIG. 5 schematically shows an example of stacked layers that may be obtained using the method according to the invention, the nature of the layers being specified in the table below.

[0031] In this document, an exemplary application of the electrical circuit according to the invention is taken from the field of chip cards, but a person skilled in the art will be able, without exercising inventive skill, to transpose this example to other electrical circuit applications. In particular, the invention is particularly advantageous in all cases where the conductive tracks will be visible on the finished product, as used by the consumer. For example, producing white-colored contacts for SD memory cards or USB keys can bring esthetic added value.

[0032] According to an exemplary application of the electrical circuit according to the invention, illustrated by FIG. 1, a chip card 1 comprises a module 2 with a connector 3. The module 2 is generally produced in the form of a separate element which is inserted into a cavity made in the card. This element comprises a generally flexible substrate 4 (see FIG. 2) of PET, glass epoxy, etc. on which the connector 3 is produced, to which a chip (not shown) is subsequently connected, via the face of the substrate opposite that comprising the connector 3.

[0033] FIG. 2 illustrates an example of a portion of an electrical circuit, here a printed circuit 5, with six connectors 3. Each connector 3 comprises a contact land 8 formed of conductive tracks 6. In the example illustrated here, eight electrical contacts 7 are formed from the conductive tracks 6.

[0034] More particularly, as shown in cross section in FIG. 3, a connector 3 (i.e. basically a module without a chip) has a multilayer structure formed of the substrate 4, of an adhesive layer 9, of a copper layer 10, of a nickel layer 11 (potentially actually composed of a first layer of pure nickel on which a second layer of nickel-phosphorus rests), of an optional primer layer 12 and finally of a layer of a rhodium alloy 13.

[0035] FIGS. 4a to 4k schematically illustrate different steps of an exemplary method according to the invention for manufacturing the connector 3. These steps comprise: [0036] providing a substrate 4 (FIG. 4a); [0037] coating one face of the substrate 4 with a layer of adhesive 9 (FIG. 4b); [0038] perforating the substrate 4 provided with the layer of adhesive 9 in order to produce connection wells 14 and potentially a cavity 15 in which a chip will later be housed (FIG. 4c); [0039] complexing the substrate 4 provided with the adhesive layer 9 with a conductive layer 10 such as a sheet of copper, aluminum or other, hot-crosslinking the adhesive layer 9 and deoxidizing the complex thus obtained (FIG. 4d); [0040] laminating a dry film photoresist 16 (FIG. 4e) onto the conductive layer 10; [0041] exposing the film photoresist 16 through a mask (FIG. 4f); [0042] developing the film photoresist 16 (FIG. 4g); [0043] chemically etching the conductive layer 10 in the regions not protected by the film photoresist 16 (FIG. 4h); [0044] dissolving the film photoresist 16 (FIG. 4i); [0045] metallizing the tracks of the conductive layer 17 obtained after etching, in one or more steps, to form the barrier layer 11 of nickel (or alloyed nickel), the potential primer layer 12 (FIG. 4j), and one or more potential layers (for example nickel 11 and gold 19) deposited at the bottom of the connection wells 14; and [0046] metallizing again to form a layer of rhodium alloy 13 (FIG. 4k). It should be noted that the potential layer of gold 19 may also be deposited after the rhodium alloy rather than before.

[0047] This last step is advantageously carried out by protecting, by masking, the back face 18 (i.e. the face intended not to be visible on the finished product). For this, a mask is applied to the face of the electrical circuit opposite that which accommodates the conductive tracks 6. Specifically, to obtain better solderability of the wires for connection to a chip, on the back face of the conductive tracks (opposite that referred to as the front face or contact face, which is intended to receive the rhodium alloy), it may be advantageous to perform a selective metalization by applying a protective film or by applying a masking belt or else by using a selective metalization wheel on this face in the step of depositing the rhodium alloy. Thus, by virtue of selective masking, the possibility is retained of leaving gold as a surface layer on the back face for soldering the connection wires of the chip.

[0048] The layer of rhodium alloy 13 is deposited by (electrochemistry). Its thickness is between 10 nanometers and 150 nanometers. This thickness, along with the deposition conditions, make it possible to obtain a substantially clear deposit. The rhodium alloy is advantageously a rhodium-ruthenium alloy, in which the rhodium represents 50% or more, by weight, of the alloy. Increasing the ruthenium concentration decreases the cost of solutions for electrolytic baths, but leads to an alloy of darker color.

[0049] The rhodium alloy solution is for example a solution sold by Metalor or Umicore. Advantageously, this solution contains no sulfamic acid and/or practically no (i.e. the magnesium concentration is in all cases lower than 1 ppm) magnesium (for example in the form of magnesium sulfate).

[0050] The deposition is performed at a temperature of 55 C.+/10 C., with a solution containing 5+8/3 g/l of rhodium, between 0 and 0.5 g/l of ruthenium and a pH of less than 1. The rate of metalization is adjusted according to the number of electrolytic metalization cells used to produce the desired thickness of rhodium alloy. The current-density conditions are also adjusted according to the areas to be treated, the desired thicknesses and the composition of the desired alloy.

[0051] The layer of rhodium alloy obtained using the method according to the invention has good corrosion resistance meeting the specifications of the field and an electrical resistance lower than 500 m.

[0052] The table below presents some examples of stacks of layers A to D (the layer A forming a barrier layer and the layers B and C being able to form primer layers) which may be produced, on a conductive layer 10 such as a sheet of copper, aluminum or other, using the method according to the invention (see FIG. 5in FIG. 5, any metal layers deposited on the bank face are not shown):

TABLE-US-00001 D Alloyed Alloyed Alloyed Alloyed Alloyed Alloyed Rh Rh Rh Rh Rh Rh C Alloyed Pd Alloyed Pd Pd Alloyed Au Alloyed Alloyed Alloyed Rh Rh Pd Au Rh Rh B Alloyed Alloyed Au or Ag Au Au or Ag Alloyed Au or Ag Alloyed Alloyed Pd Pd Pd Pd Rh Rh Rh Au Au A Ag Ni Ni Ni Alloyed Alloyed Alloyed Alloyed Alloyed Ni Alloyed Alloyed Ni Ni Ni Ni Ni Ni Ni Ni

[0053] In the table above, nickel may be replaced with a cobalt-tungsten alloy.

[0054] According to a variant of the method described above, by producing a mask before the step of depositing the rhodium alloy, it is possible to produce patterns, such as logos, of gray-white color on a yellow background (underlying layer of gold, for example) or darker gray (underlying layer of palladium, silver or nickel, for example). Such patterns may also be produced for the purposes of graphical personalization or copy protection.