MULTILINE RECEIVE BEAMFORMERS AND RELATED SYSTEMS AND METHODS

Abstract

Microbeamformers coupled to groups of array elements which partially beamform groups of elements for the formation of multiple receive lines are provided. In the microbeamformers, a delay line can be configured to output multiple signal streams that can be delayed by different amounts to support multiline receive in a microbeamformer. A read process during beamforming is not destructive, thereby allowing multiline receive beams to be generated from a single delay line.

Claims

1. A receive beamformer comprising a delay element including analog random access memory, wherein the delay element comprises: an input line configured to receive an input analog electrical signal generated from an acoustic signal received by an array of transducer elements; a write shift register configured to operate a plurality of write switches connected to the input line; a plurality of capacitive elements configured to store a charge that can be read from a plurality of outputs of each capacitive element at different delay times; a plurality of read shift registers configured to operate a plurality of read switches connected to the plurality of outputs of each capacitive element such that the charge in each capacitive element is read at the different delay times from different outputs of each capacitive element; and a plurality of summing elements, each summer configured to sum output signals from one of the plurality of outputs of each one of the capacitive elements.

2. The receive beamformer of claim 1, wherein the stored charges can be read from the plurality of outputs of each capacitive element in parallel at different delay times.

3. The receive beamformer of claim 1, wherein at least one capacitive element of the plurality of capacitive elements includes a capacitor that is coupled to the input line and a DC voltage source during a write operation, and wherein the capacitor is coupled to a plurality of amplifiers configured to allow interrogation of a stored charge on the capacitor at different delay times.

4. The receive beamformer of claim 1, wherein at least one of the capacitive elements includes a plurality of capacitors, wherein each of the capacitors is coupled to a separate write switch such that charge can be written on to each respective capacitor in the plurality of capacitors of the at least one of the capacitive elements.

5. The receive beamformer of claim 4, wherein the plurality of capacitors of the at least one of the capacitive elements are coupled to a plurality of amplifiers configured to allow interrogation of stored charges on the capacitors.

6. The receive beamformer of claim 4, wherein the stored charges on the capacitors of the at least one of the capacitive elements are configure to be read at same or different times.

7. The receive beamformer of claim 1, wherein a number of summing elements in the beamformer corresponds to a number of lines beamformed during a multiline receive beamforming.

8. The receive beamformer of claim 7, wherein the multiline receive beamforming comprises 2×, or greater multiline receive beamforming.

9. The receive beamformer of claim 1, wherein the array of transducer elements comprises a one-dimensional array or a two-dimensional array of transducer elements, and wherein the received acoustic signal is generated from a patch of transducer elements in the array.

10. (canceled)

11. The receive beamformer of claim 1, wherein the summing elements comprise summing nodes, common buses, and/or summing circuits, and wherein the write and read shift registers comprise decoders and input and output counters, respectively, for programmable delay times.

12. (canceled)

13. (canceled)

14. An ultrasound probe comprising the receive beamformer of claim 1.

15. The ultrasound probe of claim 14, wherein the receive beamformer is coupled to a system beamformer in an ultrasound system.

16. A method of multiline receive beamforming, the method comprising: receiving, on an input line, an input analog electrical signal generated from an acoustic signal received by an array of transducer elements; operating by a write shift register a plurality of write switches connected to the input line; storing a charge on a plurality of capacitive elements, each having a plurality of outputs; operating by a plurality of read shift registers a plurality of read switches connected to the plurality of outputs of each capacitive elements such that the charge in each capacitive element is read at the different delay times from different outputs of each capacitive element; and summing output signals from each of the outputs of the capacitive elements on a plurality of summing elements, wherein each summing element summing output signals from one of the plurality of outputs of each capacitive element.

17. The method of claim 16, wherein at least one capacitive element of the plurality of capacitive elements includes a capacitor that is coupled to the input line and a DC voltage source during a write operation, and wherein the capacitor is coupled to a plurality of amplifiers configured to allow interrogation of a stored charge on the capacitor at different delay times.

18. The method of claim 16, wherein at least one of the capacitive elements includes a plurality of capacitors, wherein each of the capacitors is coupled to a separate write switch such that charge can be written on to each respective capacitor in the plurality of capacitors of the at least one of the capacitive elements.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a schematic view of an embodiment of an ultrasound imaging system according to an illustrative embodiment of the invention.

[0011] FIG. 2 is a block diagram illustrating a microbeamformer and system beamformer according to an illustrative embodiment of the invention.

[0012] FIG. 3 shows a block diagram view of a beamforming architecture according to an illustrative embodiment of the invention.

[0013] FIG. 4 shows an analog random access memory used as a programmable delay line according to an illustrative embodiment of the invention.

[0014] FIG. 5 illustrates a circuit included in an analog random access memory according to an illustrative embodiment of the invention.

[0015] FIG. 6 illustrates a circuit included in an analog random access memory according to an illustrative embodiment of the invention.

DETAILED DESCRIPTION

[0016] In the following detailed description, for purposes of explanation and not limitation, illustrative embodiments disclosing specific details are set forth in order to provide a thorough understanding of an embodiment according to the present teachings. However, it will be apparent to one having ordinary skill in the art having had the benefit of the present disclosure that other embodiments according to the present teachings that depart from the specific details disclosed herein remain within the scope of the appended claims. Moreover, descriptions of well-known apparatus and methods may be omitted so as to not obscure the description of the illustrative embodiments. Such methods and apparatus are within the scope of the present teachings.

[0017] The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present system is defined only by the appended claims. The leading digit(s) of the reference numbers in the figures herein typically correspond to the figure number, with the exception that identical components which appear in multiple figures are identified by the same reference numbers. Moreover, for the purpose of clarity, detailed descriptions of certain features will not be discussed when they would be apparent to those with skill in the art so as not to obscure the description of the present system.

[0018] The present invention is related to array transducers which use microbeamformers coupled to groups of array elements which partially beamform groups of elements for the formation of multiple receive lines. Microbeamforming can use an Analog RAM, which is a switched-capacitor storage array that samples an incoming RF signal on every microchannel and applies a delay by reading out the samples some time later. The time from the write event to a particular capacitor to when that charge is read out is the effective delay. The write event can be controlled by a cycling one-hot shift register that strobes a passgate to charge up one capacitor (relative to a constant voltage referred to as VMID) during the sampling interval. The read event can be controlled by another one-hot shift register that connects the two sides of the capacitor across an output buffer. The output buffer creates a step-wise voltage at the output that mimics the voltage stored across the capacitor. Another sample interval later another capacitor can be switched across that output buffer. In this way the output voltage is a delayed step-wise representation of the input RF signal.

[0019] Multiline is frequently used to provide improved frame rates, but currently microbeamformers provide only a single-read capability. In certain aspects, the present invention is directed to a read process—switching the storage capacitor across the output buffer—that is non-destructive, which allows multiple read operations. For example, the present invention utilizes the same ARAM delay line and just re-reads the samples for each uniquely delayed output. In particular, the present invention provides an analog circuit that allows a delay line to output multiple output streams that could be delayed by different amounts to support multiline receive in a microbeamformer. Each output from the delay line can be a constituent to a beam for multiline receive beamforming. For example, two outputs correspond to 2× multiline receive beamforming, four outputs to 4× multiline receive beamforming, and so on. The present invention, e.g., allows for the possibility of re-reading from that same capacitor at some later time (controlled by a second, third, or fourth shift register) and connecting it across a second, third, or fourth output buffer. This allows numerous step-wise output sample streams to be derived from the same single input, where each output stream can have a unique delay. The write control and ARAM storage cap structure can be shared among each of these unique outputs, thereby providing increased space and power efficiency. The increased space and power efficiency can have a number of advantages for ultrasound probes, such more available space for other components in the probe as well as less heat generated during scanning.

[0020] Microbeamforming involves consolidating information from many elements (a group or patch) into a single output that is then digitized by the mainframe. Multiline receive, as typically done in the mainframe (using multi-port RAMs), becomes difficult or impossible to do depending on how large a group of elements is summed together ahead of the A/D. This is because the differential delays needed for multiline receive in the mainframe can only be applied to entire (microbeamformed) groups. In the limit, a microbeamformer could do all of the beamforming ahead of a single A/D and at that point mainframe-based receive multiline is impossible (the beam is already fully formed—1×). The present invention, e.g., applies different delays to each microchannel in order to form differently steered receive multilines. The present invention can also allow high-funneling-ratio microbeamformers (i.e. large groups) to still be able to do reasonably high order multiline that improves frame rate.

[0021] In some aspects, the present invention provides ultrasound transducer probes and ultrasound systems that include delay lines having multiple outputs for multiline receive beamforming. Referring first to FIG. 1, an ultrasound system constructed in accordance with the principles of the present invention is shown in block diagram form. A probe 10 has a transducer, such as a two dimensional array transducer 12. The elements of the array are coupled to a microbeamformer 14 located in the probe behind the transducer array. The microbeamformer applies timed transmit pulses to elements of the array to transmit beams in the desired directions and to the desired focal points in the three dimensional image field in front of the array. Echoes from the transmitted beams are received by the array elements and coupled to delays of the microbeamformer 14 where they are individually delayed. As provided further herein, received signals from the array can be input into the microbeamformer and according to the architecture of the present invention with a non-destructive read of the stored charge, multiple outputs can be read at different delay times. In some aspects, the delayed signals of a group of transducer elements constituting a patch can be combined to form a partial sum signal for the patch. The elements of a patch in this embodiment are operated together and have their signals individually delayed in relation to a reference and then combined by the microbeamformer to form one signal from the patch to a probe conductor or an ultrasound system beamformer channel. Because multiple outputs from the delay line can be read at different times, different beams can be formed with a single delay line using different delays for each of the respective outputs. Combining of the different signals can be done by coupling the delayed signals from the elements of the patch to a common bus or summing node. Summing circuits or other circuitry can also be used. The summing node of each patch is coupled to a conductor of a cable 16, which conducts the partial beamsum patch signal to the system mainframe. In the system mainframe the patch signals are digitized and coupled to channels of a system beamformer 22, which appropriately delays each patch signal. The delayed patch signals are then combined to form a coherent steered and focused receive beam. The beam signals from the 3D image field are processed by a system image processor 24 to produce 2D or 3D images for display on an image display 30. Control of ultrasound system parameters such as probe selection, beam steering and focusing, and signal and image processing is done under control of a controller 26 which is coupled to various modules of the system. In the case of the probe 10 some of this control information is provided to the microbeamformer from the system mainframe over data lines of the cable 16. The user controls many of these operating parameters by means of a control panel 20.

[0022] FIG. 2 illustrates the concept of a partially summing microbeamformer including the delay line elements of the present invention. The drawing of FIG. 2 is sectioned into three areas by dashed lines 34 and 36. Components of the probe 10 are shown to the left of line 34, components of the system mainframe are shown to the right of line 36, and the cable 16 is shown between the two lines. The elements of the transducer array 12 of the probe are divided into patches of contiguous transducer elements. Five of the patches of the array 12 are shown in the drawing, each including nine neighboring elements. The microbeamformer channels for patches 12a, 12c, and 12e are shown in the drawing. The nine elements of patch 12a are coupled to nine delay lines of the microbeamformer indicated as DL1. Similarly the nine elements of patches 12c and 12e are coupled to the delay lines indicated at DL2 and DL3. The delays imparted by these delay lines are a function of numerous variables such as the size of the array, the element pitch, the spacing and dimensions of the patch, the range of beam steering and focusing, and others. The delay line groups DL1, DL2, and DL3 each delay the signals from the elements of their respective patch to a common time or phase reference. As shown, each of the delay lines in DL1, DL2, and DL3 have two outputs that may apply different delays to the signal. Two outputs are shown by way of example. Multiple outputs are envisioned, including four, eight, sixteen, and thirty-two outputs could be used, e.g., for 2×, 4×, 8×, 16×, and 32× multiline beamforming. The delayed signals from each output of each group of delay lines are then combined by a respective summer Σ.sub.1, Σ.sub.2, Σ.sub.3, Σ.sub.4, Σ.sub.5, and Σ.sub.6, respectively, to form a partial sum signal of the array from the patch of elements. Each partial sum signal is put on a separate bus 15, each of which is coupled to a conductor of the cable 16, which conducts the partial sum signals to the system mainframe. In the system mainframe each partial sum signal is applied to an A/D converter 25 and then to a delay line 28 of a channel of the system beamformer 22. These delay lines steer and focus the partial sum signals into multiple output beams via system beamformer summers 30 and 31 (shown as E.sub.A and E.sub.B). The fully formed beams that represent the signal intensities along two different lines in the field of view can then be forwarded to the system image processor for further signal processing and display. The mainframe beamforming delays 28 can also be further bifurcated in the manner of standard receive multiline beamforming, to form more receive beams that the two shown here 30 & 31.

[0023] While the example of FIG. 2 is shown with 9-element patches, it will be appreciated that a constructed microbeamformer system will often have patches with larger numbers of elements such as 16, 32, 48, or 70 elements or more. The elements of a patch can be adjacent to each other, be spaced apart, or even intermingled in a checkerboard pattern, with “odd” numbered elements combined in one patch and “even” numbered elements combined in another. The patches can be linear, square, rectangular, diamond-shaped, hexagonal, or any other desired shape. It will also be appreciated that the position of the microbeamformer 14 in the handle of the transducer 10 is intended to reduce cable complexity, however, in some embodiments the microbeamformer could be more closely integrated with the mainframe beamformer with, for example, a conventional cable linking a conventional array to the connector or system containing the microbeamformer and mainframe beamformer.

[0024] FIG. 3 illustrates a more detailed view of the delay elements of the beamformer, in accordance with an embodiment of the present invention. As described in connection with FIG. 3, the channels 44.sub.1, 44.sub.2, 44.sub.3, . . . 44.sub.N of receive beamformer 40, which are coupled to the array 12, include programmable delay elements 46.sub.1, 46.sub.2, 46.sub.3, . . . 46.sub.N that have multiple outputs that correspond to different delayed reads of the stored charge in the delay element. Here, two outputs are shown by way of example. The first output from each delay line is coupled to a first summing element 48.sub.1, whereas the second output for each delay line is coupled to a second summing element 48.sub.2. The summing elements add the delayed signals from the respective outputs and provide the summed signals to the channel outputs 50.sub.1 and 50.sub.2 of receive beamformer 40.

[0025] In some embodiments, the beamformer 40 can be operated using a system controller, which includes a microprocessor and an associated memory. The system controller can be configured to control the operation of an ultrasound imaging system. For example, the system controller provides delay commands to the transmit beamformer channels via a bus. The delay data steers and focuses the generated transmit beams over transmit scan lines of a wedge-shaped transmit pattern, a parallelogram-shaped transmit pattern, or other patterns. The system controller also provides delay commands to the channels of the receive beamformer via a bus. The applied relative delays control the steering and focusing of the synthesized receive beams. As shown, each receive beamformer channel 44.sub.N includes a variable gain amplifier (PREAMP), which controls gain as a function of received signal depth, and a delay element 46.sub.N that delays acoustic data to achieve beam steering and dynamic focusing of the synthesized beam. The beamformer signal represents a receive ultrasound beam synthesized along a receive scan line.

[0026] Referring again to FIG. 3, each analog delay line 46.sub.N includes an analog RAM as is described in connection with FIG. 4. In FIG. 4, an analog random access memory (RAM) device 60 can be configured as a programmable delay element. The analog RAM device 60 includes a group of M storage capacitive elements (including, e.g., capacitors) 62.sub.1, 62.sub.2, . . . , 62.sub.M for sampling the input signal using decoder 66.sub.1 connected to input switches 65.sub.1, 65.sub.2, . . . , 65.sub.M. The analog RAM device 60 also includes a first and second read capability where the decoders 66.sub.2 and 66.sub.3 control first output switches 67.sub.1, 67.sub.2, . . . , 67.sub.M and second output switches 68.sub.1, 68.sub.2, . . . , 68.sub.M, respectively, to read the stored signal out with potentially different delays. An input buffer 64 receives a transducer signal that is then sent by input switch 65.sub.N controlled by decoder 66.sub.1 to storage capacitive element 62.sub.N. As described further herein, the capacitive element of the present invention is configured for non-destructive reads such that when one read is processed the stored charge stays and can be read again at a different time. Here, two outputs from the capacitive elements are shown. Decoder 66.sub.2 coupled to output switches 67.sub.M samples the individual capacitor charges at delay times determined by the difference in timing between an input counter 70 and a first output counter 72.sub.1. Accordingly, the transducer signals are delayed by selected delay times as they are transferred from input buffer 64 to a first output buffer 74.sub.1. Decoder 66.sub.3 coupled to output switches 68.sub.M samples the individual capacitor charges at delay times determined by the difference in timing between an input counter 70 and a second output counter 72.sub.2. Accordingly, the transducer signals are delayed by selected delay times as they are transferred from input buffer 64 to a second output buffer 74.sub.2. It is noted that the dashed lines for the second output are shown to infer that the capacitive elements couple to the second decoder and output counter for different delay times to be applied to the second output from the capacitive elements. It is envisioned that other configurations can be used to write and read the charge off of the capacitive elements. For example, cyclized shift registers could also be used instead of a counter and decoder.

[0027] FIG. 5 illustrates an example of an ARAM storage capacitor structure of the present invention. This example shows a 2×-multiline ARAM structure with two summing nodes from two different elements. As shown, the write-side passgates (80a, 80b, 80c, 80d) at the left connect to VMID 82a, 82b (e.g., a constant 1.25V) and the output of the preamplifiers 84a, 84b, (similar to the preamplifier 64 in FIG. 4) which are coupled to elements in the array 12. The passgates are controlled by digital circuits (not shown, but discussed earlier as possibly a counter 70 and decoder 66.sub.1) that enable each storage capacitor in sequence for a given time period depending on sample rate (e.g., 20-50 nsec). The voltage from the preamp is sampled and stored on the capacitor 62. The read ports for each corresponding output from the capacitor (86a and 87a for the first output, and 86b and 87b for the second) get enabled at different times and connect to two different output buffers 88a and 88b that in turn drive different summing elements 89a and 89b. For example, read ports 86a and 87a can be read at a first time providing a first delay, and read ports 86b and 87b can be read at a later, second time providing a second delay. Inverting amplifiers 88a and 88b are coupled to different ends of the capacitor, respectively, to non-destructively read the charge stored on the capacitor so that the voltage at the output of the buffer 88a and 88b are largely equivalent.

[0028] Another possible implementation of this structure would essentially bifurcate the capacitive element into two equal halves (e.g., two different capacitors) that are shorted together by a switch during the write interval and then read out separately at the same or different times. This implementation is shown in FIG. 6, which is similar to FIG. 5, except that the write passgates 80a and 80b and storage capacitors 62a and 62b are split and the read side passgates 86a/87a and 86b/87b are read from the two different capacitors 62a and 62b. This structure includes two full delay structures per microchannel and the storage capacitor that is read out for each partial sum is half the size that was written to. This structure allows the two read ports to apply the same overall delay, whereas the shared structured shown in FIG. 5 could not have 86a/87a and 86b/87b passgates connected to the same capacitor at the same time (the amplifiers would fight one another). FIG. 6 further includes inverting amplifiers 88a and 88b; however, certain embodiments include the option in which no inverting amplifiers are used. In the latter, the read is destructive and in the former the read is non-destructive.

[0029] Certain additional advantages and features of this invention may be apparent to those skilled in the art upon studying the disclosure, or may be experienced by persons employing the novel system and method of the present invention, chief of which is that twice as many receive beams may be formed simultaneously, thus dramatically improving imaging frame rate.

[0030] Of course, it is to be appreciated that any one of the above embodiments or processes may be combined with one or more other embodiments and/or processes or be separated and/or performed amongst separate devices or device portions in accordance with the present systems, devices and methods.

[0031] Finally, the above-discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the claims that follow. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.