PRINTABLE INORGANIC SEMICONDUCTOR STRUCTURES

Abstract

The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.

Claims

1-25. (canceled)

26. A printable inorganic semiconductor structure comprising: a semiconductor element having a substrate side and a handle side opposite the substrate side; a first electrical contact on the handle side of the semiconductor element; a second electrical contact on the substrate side of the semiconductor element; an interlayer forming an anchor separated from and adjacent to the semiconductor element; a handle substrate adhered to the interlayer; and a tether bridging the substrate side of the semiconductor element to the anchor, thereby physically securing the semiconductor element to the anchor.

27. (canceled)

28. The structure of claim 26, wherein the handle substrate is a wafer.

29. The structure of claim 26, wherein the sacrificial layer comprises a material selected from the group consisting of Si (1 1 1), InAlP, InP, GaAs, InGaAs, AlGaAs, GaSb, GaAlSb, AlSb, InSb, InGaAlSbAs, InAlSb, and InGaP.

30-33. (canceled)

34. The structure of claim 26, wherein the semiconductor layer comprises multiple sub-layers.

35. The structure of claim 26, comprising protrusions (e.g., metal protrusions) on the first electrical contact.

36-41. (canceled)

42. The structure of claim 26, comprising one or more additional electrical contacts, wherein the semiconductor element, the first electrical contact, and the second electrical contact and the one or more additional electrical contacts form a transistor and integrated circuit.

43. The structure of claim 26, wherein the first electrical contact has a different thickness than the second electrical contact.

44. The structure of claim 26, wherein the first electrical contact and the second electrical contact extend to a common distance from a surface of the semiconductor element.

45. The structure of claim 26, wherein a portion of the semiconductor element is removed such that a portion of the first electrical contact is exposed.

46. The structure of claim 26, wherein the semiconductor structure has a width from 1-8 μm.

47. The structure of claim 26, wherein the semiconductor structure has a length from 5-10 μm.

48. The structure of claim 26, wherein the semiconductor structure has a height from 0.5-3 μm.

49. A wafer comprising a plurality of printable semiconductor structures, each printable semiconductor structure comprising a semiconductor element having a substrate side and a handle side opposite the substrate side, a first electrical contact on the handle side of the semiconductor element, a second electrical contact on the substrate side of the semiconductor element, an interlayer forming an anchor separated from and adjacent to the semiconductor element, a handle substrate adhered to the interlayer, and a tether bridging the substrate side of the semiconductor element to the anchor, thereby physically securing the semiconductor element to the anchor, wherein the interlayer and handle substrate are common to each of the plurality of the printable semiconductor structures.

50. (canceled)

51. The array of inorganic semiconductor structures comprisingof claim 52, wherein: each semiconductor element of the plurality of semiconductor elements, is surrounded by a trench of a plurality of trenches; comprising a sacrificial layer covering the first electrical contact and covering the handle side of at least a portion of the plurality of semiconductor elements and filling a portion of the plurality of trenches; wherein the interlayer is formed over the sacrificial layer, wherein a portion of the interlayer contacts the source substrate at a base of at least a portion of the plurality of trenches to form the anchor structure comprising a plurality of anchors; and wherein at least a portion of the interlayer is between the handle substrate and the sacrificial layer.

52. An array of printable inorganic semiconductor structures comprising: a plurality of semiconductor elements, each having a substrate side and a handle side opposite the substrate side; a plurality of first electrical contacts, each first electrical contract on the handle side of one of the semiconductor elements of the plurality of semiconductor elements; a plurality of second electrical contacts, each second electrical contact on the substrate side of one of the semiconductor elements of the plurality of semiconductor elements; an interlayer forming an anchor structure separated from and adjacent to the plurality of semiconductor elements, wherein the anchor structure comprises a plurality of anchors; a handle substrate adhered to the interlayer; and a plurality of tethers, each respective tether bridging the substrate side of one of the semiconductor elements of the plurality of semiconductor elements to one of the anchors of the plurality of anchors, thereby physically securing each semiconductor element to the anchor structure.

53. A method of making an array of inorganic semiconductor structures suitable for micro-transfer printing, comprising: providing a source substrate; forming a semiconductor layer on the source substrate, wherein the semiconductor layer has a first side and a second side opposite the first side and adjacent to the substrate; forming a plurality of first electrical contacts on the first side of the semiconductor layer opposite the source substrate; removing a portion of the semiconductor layer surrounding each of the plurality of first electrical contacts to form a plurality of trenches, each surrounding a semiconductor element of a plurality of semiconductor elements made from the semiconductor layer, each semiconductor element having a substrate side in contact with the source substrate and a handle side opposite the substrate side; providing a sacrificial layer covering the plurality of first electrical contact and covering at least a portion of the handle side of each of the plurality of semiconductor elements and filling a portion of each of the plurality of trenches; providing an interlayer over the sacrificial layer, the interlayer having different chemical selectivity than the sacrificial layer, wherein a portion of the interlayer contacts the source substrate at the base of each of the plurality of trenches to form a plurality of anchors; adhering the interlayer to a handle substrate; removing the source substrate to expose the substrate side of each of the plurality of semiconductor elements; forming a plurality of second electrical contacts, each second electrical contract on the exposed substrate side of one of the semiconductor elements of the plurality of semiconductor elements; optionally forming a plurality of tethers, each tether bridging the exposed substrate side of one of the semiconductor elements of the plurality of semiconductor elements to one of the anchors of the plurality of anchors; and removing the sacrificial layer, thereby forming an array of printable semiconductor structures partially released from the handle substrate and physically secured to a respective anchor by a corresponding tether.

54. A method of making an array of inorganic semiconductor structures suitable for micro-transfer printing, comprising: providing a source substrate; forming a semiconductor layer on the source substrate, wherein the semiconductor layer has a first side and a second side opposite the first side and adjacent to the substrate; removing a portion of the semiconductor layer to form a plurality of trenches, each trench surrounding a semiconductor element of a plurality of semiconductor elements made from the semiconductor layer, each semiconductor element having a substrate side in contact with the source substrate and a handle side opposite the substrate side; providing a sacrificial layer covering at least a portion of the handle side of each of the plurality of semiconductor elements and filling a portion of each of the plurality of trenches; providing an interlayer over the sacrificial layer, the interlayer having different chemical selectivity than the sacrificial layer, wherein a portion of the interlayer contacts the source substrate at the base of each of the plurality of trenches to form a plurality of anchors; adhering the interlayer to a handle substrate; removing the source substrate to expose the substrate side of each of the plurality semiconductor elements; removing a portion of each of the plurality of semiconductor elements to form a plurality of cantilever extension, each cantilever extension of one of the plurality of semiconductor elements; forming a plurality of first electrical contacts, each on one of the plurality of cantilever extensions; forming a plurality of second electrical contacts, each on the exposed substrate side of one of the plurality of semiconductor elements; optionally forming a plurality of tethers bridging the exposed substrate side of one of the plurality of semiconductor elements to one of the plurality of anchors; and removing the sacrificial layer, thereby forming a printable semiconductor structure partially released from the handle substrate.

55. A method of making an array of inorganic semiconductor structures suitable for micro-transfer printing, comprising: providing a source substrate; forming a semiconductor layer on the source substrate, wherein the semiconductor layer has a first side and a second side opposite the first side and adjacent to the substrate; removing a portion of the semiconductor layer to form a plurality of cantilever extensions; forming a plurality of first electrical contacts on the semiconductor layer; form a plurality of second electrical contact, each on one of the plurality of cantilever extensions; removing a portion of the semiconductor layer surrounding each pair of first and second electrical contacts to form a plurality of trenches, each surrounding a semiconductor element of a plurality of semiconductor elements made from the semiconductor layer, the plurality of semiconductor elements having a substrate side in contact with the source substrate and a handle side opposite the substrate side; providing a sacrificial layer covering the plurality of first and second electrical contacts and covering at least a portion of the handle side of each of the plurality of semiconductor elements and filling a portion of each of the plurality of trenches; providing an interlayer over the sacrificial layer, the interlayer having different chemical selectivity than the sacrificial layer, wherein a portion of the interlayer contacts the source substrate at the base of each of the plurality of trenches to form a plurality of anchors; adhering the interlayer to a handle substrate; removing the source substrate to expose the substrate side of each of the plurality of semiconductor elements; optionally forming a plurality of tethers, each bridging the exposed substrate side of one of the plurality of semiconductor elements to one of the plurality of anchors; and removing the sacrificial layer, thereby forming a plurality of printable semiconductor structures partially released from the handle substrate and physically secured to a respective anchor by a corresponding tether.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The foregoing and other objects, aspects, features, and advantages of the present disclosure will become more apparent and better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:

[0071] FIGS. 1-10 are cross sections illustrating a method and structures in accordance with embodiments of the present invention;

[0072] FIG. 11 is a cross section corresponding to an inverted view of the illustration of

[0073] FIG. 10 in accordance with an embodiment of the present invention;

[0074] FIG. 12 is a cross section illustrating conductive protrusions in accordance with an embodiment of the present invention;

[0075] FIG. 13 is a cross section of an embodiment of the present invention having exposed first and second electrical electrodes;

[0076] FIG. 14 is a cross section of an embodiment of the present invention having exposed first and second electrodes;

[0077] FIG. 15 is a cross section of an embodiment of the present invention having first and second electrodes exposed to a similar side of the semiconductor element;

[0078] FIGS. 16-18 are sequential cross sections illustrating a method of micro-transfer printing useful in accordance with embodiments of the present invention;

[0079] FIG. 19 is a cross section illustrating conductive protrusions making electrical contact with an electrical conductor on a destination substrate in accordance with an embodiment of the present invention;

[0080] FIG. 10-21 are cross sections illustrating various arrangements of electrical contacts and semiconductor elements in accordance with embodiments of the present invention;

[0081] FIGS. 22-27 are flow charts illustrating methods in accordance with embodiments of the present invention;

[0082] FIGS. 28-29 are cross sections illustrating structures having substrate tethers in accordance with embodiments of the present invention;

[0083] FIGS. 30-31 are cross sections illustrating structures having interlayer tethers in accordance with embodiments of the present invention;

[0084] FIG. 32 is a cross section illustrating structures having an ablation layer in accordance with an embodiment of the present invention;

[0085] FIG. 33 is a cross section illustrating structures after the removal of an ablation layer and substrate in accordance with an embodiment of the present invention; and

[0086] FIGS. 34-35 are cross sections illustrating structures having passivation layers in accordance with embodiments of the present invention.

[0087] The features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The figures are not drawn to scale since the variation in size of various elements in the Figures is too great to permit depiction to scale.

DETAILED DESCRIPTION OF THE INVENTION

[0088] The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. Various semiconductor elements may be formed using the methods and techniques described here, including diode (e.g., micro-diodes), lasers (micro-lasers), light-emitting diode (e.g., micro-LEDs).

[0089] FIGS. 1-10 are diagrams illustrating step-by-step fabrication of a printable semiconductor element 60 secured to an anchor 12 by a tether 10 such that the semiconductor element 60 may be picked up by a transfer device as illustrated in FIG. 16. FIG. 22 is a flowchart illustrating a series of steps (e.g., in sequential order) corresponding to the fabrication of a printable semiconductor element 60 as shown in FIGS. 1-10. Referring to FIGS. 1 and 22, a source substrate 1 is provided in step 100. In some embodiments, the source substrate 1 is a wafer substrate 1, such as a sapphire wafer. Sapphire is a useful substrate because it has a lattice structure more closely matched to that of GaN (useful for LEDs) than silicon. Wafer substrates in a variety of material types and sizes may be used. For the purpose of this description, source substrate 1 will be described as a wafer.

[0090] A semiconductor layer 2 is located on the wafer substrate 1 in step 110. The semiconductor layer 2 may be located on the wafer substrate 1, in some embodiments, by forming crystalline layers using molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). The semiconductor layer 2 can be further processed, if necessary, to provide a crystalline semiconductor layer. In some embodiments, the semiconductor layer 2 is crystalline GaN. The GaN material can be doped, for example, with magnesium to form a p-type semiconductor or with silicon or oxygen to form an n-type semiconductor. The semiconductor layer 2 can be formed having sub-layers with different concentrations of different material, for example, to provide different sub-layers having different electrical properties. In some embodiments, one sub-layer is doped to provide increased electrical conductivity and another sub-layer is doped to provide light-emitting properties in response to an electrical current passing through the semiconductor crystal.

[0091] Referring to FIG. 2, an electrically conductive layer is deposited on the semiconductor layer 2 and patterned to form a first electrical contact 3 in step 120. In some embodiments, the first electrical contact 3 is a metal or metal oxides.

[0092] Referring next to FIG. 3, a trench 4 is formed in the semiconductor layer 2 (step 130) thereby forming a semiconductor element 60. In some embodiments, the trench 4 is formed by patterning the semiconductor layer 2, for example, using photolithographic patterning methods (e.g., etching) to form a trench 4 around the semiconductor element 60. The semiconductor element 60 has a substrate side 62 in contact with the wafer substrate 1 and a handle side 64 opposite the substrate side 62. When separated from the larger semiconductor layer 2 and electrically connected with two or more electrical contacts, the semiconductor element 60 can form a variety of semiconductor structures, including a diode, a light-emitting diode (LED), a transistor, or a laser. In some embodiments, the steps illustrated in FIG. 22 are performed in a different order. For example, step 130 may be performed before step 120 such that the trench 4 is formed prior to the first electrical contact 3.

[0093] The handle side 64 of the semiconductor element 60 can include all of the surfaces of the semiconductor element 60 other than the substrate side 62 (e.g., that contacts the wafer substrate 1) including the edges and adjacent sides (e.g., not including the substrate side 64). In some embodiments, the handle side 64 only includes the side of the semiconductor element 60 opposite (e.g., and parallel) the wafer substrate 1.

[0094] As shown in FIG. 4, a sacrificial layer 5 (step 140) is deposited over the first electrical contact 3. In some embodiments, the sacrificial layer 5 also covers at least a portion of the handle side 64 of the semiconductor element 60 and fills a portion of the trench 4. In one embodiment, the sacrificial layer 5 is formed over the entire handle side 64 of the semiconductor element 60 and over the first electrical contact 3. In another embodiment, the sacrificial layer 5 is formed over the first electrical contact 3 and a portion of the semiconductor element 60, for example, leaving a portion of the semiconductor element 60 exposed, adjacent to, or in contact with the wafer substrate 1. In some embodiments, the sacrificial layer 5 is a polymer, inorganic dielectric, or metals. In some embodiments, the sacrificial layer 5 is Si (1 1 1), InAlP, InP, GaAs, InGaAs, AlGaAs, GaSb, GaAlSb, AlSb, InSb, InGaAlSbAs, InAlSb, or InGaP.

[0095] An interlayer 6 is provided in step 150 (FIG. 22) as shown in FIG. 5. The interlayer 6 is located over the sacrificial layer 5 and also fills a portion of the trench 4 to form an anchor 12. The interlayer 6 can be a metal, dielectric, or polymer and has a different chemical selectivity than the sacrificial layer 5. This allows removal of the sacrificial layer 5 without removing the interlayer 6. In this way, the anchor 12 (made of the interlayer 6) will remain in place after the sacrificial layer 5 is moved. As explained below, a tether 10 is formed to connect the semiconductor element 60 to the anchor 12 such that the position and/or orientation of the semiconductor element 60 is maintained after the sacrificial layer 5 is removed. In some embodiments, the sacrificial layer 5 can be etched with chemical solvents such as acids and bases. For example, a basic developer may be used to remove a polymer sacrificial layer. In other embodiments, hydrofluoric acid is used to remove an inorganic oxide sacrificial layer.

[0096] In some embodiments, the interlayer 6 is located in a portion of the trench 4 as shown in FIG. 5. In at least some of the trenches 4 (but not necessarily all), the sacrificial layer 5 is present so that the semiconductor element 60 can be released from the wafer substrate 1 using a printing method. Thus, in one embodiment, the interlayer 6 is present in a portion of all of the trenches 4 because the sacrificial layer 5 is also present in all of the trenches 4. In another embodiment, the sacrificial layer 5 is present in only some, but not all, of the trenches 4, so that the interlayer 6 fills some, but not all, of the trenches. As illustrated in FIG. 30, an interlayer 6 that fills (i.e., coats) an entire trench 4 is also in contact with a portion of the semiconductor element 60 and serves as an interlayer tether 17. In the example shown in FIG. 30, the tether 17 and anchor 12 is formed by the interlayer 6. Thus, when the sacrificial layer 5 is removed, the interlayer 6 (i.e., tether 17) remains connected to the semiconductor element 60 and maintains the position and/or orientation of the semiconductor element 60 until a stamp picks up the semiconductor element 60 (e.g., thereby breaking the tether 17).

[0097] In step 160, the interlayer 6 is adhered to a handle substrate 8 as illustrated in FIG. 6. The handle substrate 8 can be, for example, a glass, metal, or plastic substrate or a wafer. In some embodiments, an adhesive layer 7 is provided on the interlayer 6 and the handle substrate 8 is adhered to the adhesion layer 7. The adhesive layer 7 may be an adhesive material, plastic, resin, or other inorganic materials. The adhesive layer 7 may be provided as a coating over the interlayer 6. The adhesive layer 7 adheres the interlayer 6 to the handle substrate 8. In an alternative embodiment, the interlayer 6 is itself adhesive or the adhesion layer 7 includes the same material as the interlayer 6.

[0098] The wafer substrate 1 is then removed (step 170) as shown in FIG. 7 to expose the substrate side 62 of the semiconductor element 60. In some embodiments, the wafer substrate 1 is removed using ablation, for example, laser ablation, grinding, etching, and polishing. In one embodiment, a thin portion of the substrate side 62 of the semiconductor element 60, any portion of the sacrificial layer 5 in contact with the wafer substrate 1 and any portion of the interlayer 6 in contact with the wafer substrate 1 are ablated. In another embodiment a thin laser ablation layer 18 that effectively absorbs laser radiation is provided on the wafer substrate 1 before the semiconductor layer 2 is formed such that the ablation layer 18 is between the semiconductor layer 2 and the wafer substrate 1 as shown in FIG. 32.

[0099] In yet another embodiment, a portion of the semiconductor layer 2 serves as an ablation layer. In this embodiment, step 130 of providing a trench 4 in the semiconductor layer 2 removes only a portion of the semiconductor layer 2 in the trench 4. The remaining semiconductor material below the trench 4 and a portion of the semiconductor material making up the semiconductor element 60 (e.g., the bottom portion on the substrate side 62) serves as the ablation layer. A portion of the semiconductor layer 2 on the wafer substrate 1 under the semiconductor element 60 is also designated as the ablation layer even though the same semiconductor materials form both layers. In this embodiment, the semiconductor ablation layer is located between the wafer 1 on one side and both the sacrificial layer 5, the interlayer 6, and semiconductor element 60 on the other. The portion of the ablation layer beneath the semiconductor element 60 is essentially equivalent to the embodiment above in which a thin layer of the semiconductor element 60 is ablated. Once the thin ablatable layer between the wafer substrate 1 and the elements formed over the wafer substrate 1 is ablated, the wafer substrate 1 can be removed by mechanical means, by washing, or by other methods resulting in the structure of FIG. 33.

[0100] After the wafer substrate 1 (source substrate) is removed from the semiconductor element 60, a second electrical contact 9 is formed in step 180 on the exposed substrate side 62 of the semiconductor element 60, as shown in FIG. 8. Similar photolithographic methods and materials can be used to form the second electrical contact 9 as are used to form the first electrical contact 3.

[0101] A tether 10 is formed (step 200) (e.g., across the trench 4) to bridge the semiconductor element 60 to the anchor 12 as shown in FIG. 9. The tether 10 can be made in a common step, a different step, before, or after the second electrical contact 9 is formed in step 180. The tether 10 is formed to connect the semiconductor element 60 to the anchor 12 such that the position and/or orientation of the semiconductor element 60 is maintained after the sacrificial layer 5 is removed.

[0102] In step 200 and as shown in FIG. 10, the sacrificial layer 5 is removed to form a printable semiconductor structure, for example, an LED, a diode, or other semiconductor devices. Tether 10 tethers the printable semiconductor structure to the anchor 12 formed by the interlayer 6. This maintains the position of the printable semiconductor structure even though separation 11 now exists with the sacrificial layer 5 removed. The interlayer 6 has a different chemical selectivity than the sacrificial layer 5, thereby allowing removal of the sacrificial layer 5 without removing the interlayer 6. If the interlayer 6 forms the interlayer tether 17 (as shown in FIG. 30), the sacrificial layer 5 removal step 200 results in the structure illustrated in FIG. 31.

[0103] FIG. 11 illustrates the same structure as that of FIG. 10 but inverted and in a position to be printed using, for example, an elastomeric stamp. The micro transfer printing process described in U.S. Pat. Nos. 7,622,367 and 8,506,867, each of which is hereby incorporated by reference in its entirety.

[0104] Referring to FIG. 12 and FIG. 24, in a further embodiment of the present invention, one or more protrusions 13 are formed on the first electrical contact 3 in step 125. The protrusions 13, for example, may be electrically conductive protrusions 13. When the semiconductor structure is printed onto a destination substrate 30, as shown in FIG. 19, the conductive protrusions 13 assist in providing electrical contact between the first electrical contact 3 and a first wire 50 formed on the destination substrate 30 formed on the destination substrate 30. In some embodiments, the protrusions 13 are made of a harder conductive material than the wire 50 such that the protrusions 13 penetrate the wire 50 when the semiconductor structure is printed. In some embodiments, the structure (e.g., thickness and/or shape) of the protrusions 13 and the wire 50 allow protrusions 13 to penetrate the wire 50 (or connection pad) when the semiconductor structure is printed.

[0105] In some embodiments as illustrated in FIGS. 10, 11, and 19, the first electrical contact 3 is on an opposite side of the semiconductor element 60 from the second electrical contact 9. In some embodiments, it is advantageous to have the first electrical contact 3 and the second electronic accessible from the same side of the semiconductor element. This may be accomplished in several ways.

[0106] Referring next to FIG. 13, the first electrical contact 3 is on the handle side 64 of the semiconductor element 60 and the second electrical contact 9 is on the opposite substrate side 62 of the semiconductor element 60. In this example, the first electrical contract 3 is accessible from the top (as shown in FIG. 13) when the semiconductor element 60 is printed to the destination substrate. The first electrical contract 3 is formed such that a portion of it extends beyond the edge of the semiconductor element 60, thereby enabling access to the first electrical contact 3 from the same side of the structure as the second electrical contact 9 when the structure is printed to a destination substrate 30. This may be advantageous as printed on a destination substrate 30, both the first and second electrical contacts 3, 9 are accessible for connection in a common set of photolithographic steps, as shown in FIG. 20. A further description of micro-LEDs with two or more electrodes accessible for a common set of photolithographic steps, the technology of which may be applied to other devices as well, is discussed in U.S. Patent No. 62/056419, filed Sep. 26, 2014, entitled Interconnection Architectures Advantageous for Micro-LED Displays Assembled Via Micro Transfer Printing, which is hereby incorporated by reference in its entirety.

[0107] As illustrated in FIG. 23, the structure illustrated in FIG. 13 may formed by removing a portion of the semiconductor element 60 in step 175 (e.g., by etching) such that a portion of the first electrical contact 3 is exposed (e.g., accessible from the same side as the second electrical contact 9) as shown in FIG. 13 using photolithographic processes. This may be accomplished after removing the wafer substrate 1 in step 170.

[0108] Referring next to FIG. 14, an alternative structure locates both the first and second electrical contacts 3, 9 on the substrate side 62 of the semiconductor element 60. This structure is also made by removing a portion of the semiconductor element 60 in step 175, however, the removal of semiconductor material is stopped before the portion is etched entirely through the semiconductor element 60, thereby leaving a cantilever extension 14 of the semiconductor element 60. In one embodiment, the cantilever extension 14 is doped differently from the remainder of the semiconductor element 60. This, for example, allows the cantilever extension 14 to be more electrically conductive or to better prevent light emission while the remainder of the semiconductor element 60 is doped to emit light in response to a current between the first and second electrical contacts 3, 9. After the cantilever extension 14 is formed, the second electrical contact 9 is formed on the cantilever extension 14 (e.g., by a photolithography). Referring to FIG. 25, in some embodiments, the structure of FIG. 14 is formed by using the process of FIG. 22 but skipping the step 120 of forming the first electrical contact 3 on the handle side 64 of the semiconductor structure 60. The process then continues as described with respect to FIG. 22 until after the wafer substrate 1 is removed in step 170. After the wafer substrate 1 is removed, the portion of the semiconductor element 60 is removed in step 171, forming the cantilever extension 14, and the first electrical contact 3 is formed on the cantilever extension 14 in step 172. In some embodiments, both the first and second electrical contracts 3, 9 are formed at the same time or one after the other.

[0109] The process of FIG. 25 forms the structure of FIG. 14 with the first and second electrical contacts 3, 9 on the substrate side 62 of the semiconductor element 60. In an alternative embodiment and method illustrated in FIG. 15 and FIG. 26, the first and second electrical contacts 3, 9 are formed on the handle side 64 of the semiconductor element 60. In this embodiment, as illustrated in FIG. 26, after the semiconductor layer 2 is formed (step 110), a portion is removed of the semiconductor layer 2 in step 111 to form the cantilever extension 14. The first electrical contact 3 is then formed on the semiconductor layer 2 in step 112 and the second electrical contact 9 is formed on the cantilever extension 14 in step 113. The printable semiconductor element shown in FIG. 15 may be printed with the first and second electrical contacts 3, 9 facing the destination substrate 30 or facing away from the destination substrate 30. Various techniques may be used to flip the printable structures, such as those described in U.S. Pat. No. 8,889,485, issued Nov. 18, 2014, entitled Methods for Surface Attachment of Flipped Active Components, which is hereby incorporated by reference in its entirety.

[0110] The structures of FIGS. 14 and 15 may be printed on a destination substrate 30 using a printing process employing a stamp, such as an elastomeric stamp to form the structures, such as the structure illustrated in FIG. 21. Referring to FIG. 16 a stamp 20 includes a stamp substrate 23 and a stamp post 24. The stamp posts 24 are pressed against the semiconductor structures of the present invention to fracture the tethers 10 to form fractured tethers 25 and release the semiconductor structures. The semiconductor structures then adhere to the stamp posts 24, as shown in FIG. 16. The semiconductor structures are then printed to a destination substrate 30.

[0111] In some embodiments, as shown in FIG. 17, the picked up semiconductor structure 26 is the positioned over the destination substrate 30 with the first electrical contact 3 aligned with the first contact pad 50 on the destination substrate 30. The picked up semiconductor structure 26 is then transferred to the destination substrate 30 with the first electrical contact 3 in contact with the first contact pad 50 on the destination substrate 30, as shown in FIG. 18. An electrical connection may be made to the second electrical contact 9 of the printed semiconductor structure 27. Further discussion of methods of micro transfer printing can be found in U.S. Pat. Nos. 7,622,367 and 8,506,867, each of which is hereby incorporated by reference in its entirety.

[0112] In some embodiments, the picked up semiconductor structure 26 may be assembled on the destination substrate 30 using compound micro assembly as explained in U.S. Patent Application No. 62/055,472, filed Sep. 25, 2014, entitled Compound Micro-Assembly Strategies and Devices, which is hereby incorporated by reference in its entirety.

[0113] Referring next to FIGS. 27 and 28, in an embodiment of the present invention the tethers are formed as substrate tethers 16 on the wafer substrate 1 in step 131 after the semiconductor element 60 and the first electrical contact 3 are formed. The sacrificial layer 5 and the interlayer 6 are then formed as described above in steps 140 and 150. The interlayer 6 is adhered to the handle substrate 8 in step 160 and the wafer substrate 1 is removed in step 170. The second electrical contact 9 is then formed on the semiconductor element 60 in step 180 and the sacrificial layer 5 removed to form the structure shown in FIG. 29.

[0114] In a further embodiment and as shown in FIG. 34, a passivation layer 19 is provided on a portion of the handle side 64 of the semiconductor element 60. The passivation layer 19 electrically isolates the side walls of the side of the semiconductor element 60 avoid unwanted electrical conduction when the first or second electrical contacts are electrically connected on a destination substrate 30. FIG. 35 illustrates a printable semiconductor structure with the passivation layer 19.

[0115] In a further embodiment and as also illustrated in FIG. 21, a second wire 52 is formed on the destination substrate 30 and is electrically connected to the second electrical contact 9. Both the first and the second electrical contacts 3, 9 can be made in a common step if both are on a common side of the semiconductor element 60 opposite the destination substrate 30 after printing. Using a common step to electrically connect the first and the second electrical contacts 3, 9 to the first and second wires 50, 52, respectively, on the destination substrate 30 reduces costs and improves yields. The passivation layer 19 prevents unwanted electrical conduction to the semiconductor element 60 from the first and second wires 50, 52.

[0116] In an embodiment of the present invention, the semiconductor element 60 has a length greater than its width, for example having an aspect ratio greater than or equal to 2, 4, 8, 10, 20, or 50, and first and second electrical contacts 3, 9 that are adjacent to the ends of the semiconductor element 60 along the length of the semiconductor element 60. This structure enables low-precision manufacturing processes to electrically connect the first and second wires 50, 52 to the first and second electrical contacts 3, 9 without creating registration problems and possible unwanted electrical shorts or opens. At times the present disclosure describes formation of a single semiconductor element or structure (e.g., a micro-device). The same techniques and methods may be used to form arrays of these elements, devices, and/or structures such that multiple micro-devices may be micro transfer printed to a destination substrate from a single substrate (e.g., handle substrate). Thus, the present disclosure contemplates the formation and micro transfer printing of arrays of micro-devices using the methods and techniques described herein. When formation of a single structure is described herein, it is contemplated that the same steps may be performed to an array of structures at the same time, thereby enabling the formation of arrays of micro-devices for micro transfer printing to a destination substrate. For example, micro LEDs can be formed on their native substrate with a resolution of approximately 3000 micro LEDs per square inch (e.g., 2500-3100, 2900-3500 micro LEDs per square inch).

[0117] As is understood by those skilled in the art, the terms “over”, “under”, “above”, “below”, or “beneath” are relative terms and can be interchanged in reference to different orientations of the layers, elements, and substrates included in the present invention.

[0118] Having described certain implementations of embodiments, it will now become apparent to one of skill in the art that other implementations incorporating the concepts of the disclosure may be used. Therefore, the disclosure should not be limited to certain implementations, but rather should be limited only by the spirit and scope of the following claims.

[0119] Throughout the description, where apparatus and systems are described as having, including, or comprising specific components, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are apparatus, and systems of the disclosed technology that consist essentially of, or consist of, the recited components, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the recited processing steps.

[0120] It should be understood that the order of steps or order for performing certain action is immaterial so long as the disclosed technology remains operable. Moreover, two or more steps or actions in some circumstances can be conducted simultaneously. The invention has been described in detail with particular reference to certain embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.