On-chip emulation of large resistors for integrating low frequency filters

Abstract

A system for processing of signals with poles that are low in frequency includes a switched capacitor circuit that includes two switches connected to an input and an output of a switching capacitor (C.sub.s), respectively, in an alternating manner at a selected switching frequency (f.sub.SW); and a filter capacitor connected between an input and the switched capacitor circuit. The filter capacitor and the switched capacitor circuit together function as a filter, thereby a pole frequency depending on a ratio of capacitance of the switching capacitor (C.sub.s) and the filter capacitor, instead of an RC product.

Claims

1. A system for processing of signals with poles that are low in frequency, comprising: a switching capacitor circuit network comprising two switches connected to an input and an output of a switching capacitor (C.sub.s), respectively, in an alternating manner at a selected frequency (f.sub.SW), wherein the switching capacitor circuit network is connected to a common mode reference of the system and is used for fixing a DC bias level of the system; and a filter capacitor (C.sub.HPF) connected between an input and the switching capacitor circuit network, wherein the filter capacitor and the switching capacitor circuit network together function as a fully integrated on-chip filter, thereby resulting in a pole frequency depending on a ratio of capacitance of the switching capacitor circuit network and the filter capacitor (C.sub.HPF), wherein a capacitance of the filter capacitor is substantially larger than a capacitance of the switching capacitor, wherein the system is fully integrated on chip using an advanced process node of 20 nm.

2. The system of claim 1, wherein the capacitance of the filter capacitor is 100 times or more larger than the capacitance of the switching capacitor.

3. The system of claim 1, wherein a resulting pole frequency variation, which varies with process, bias voltage, and temperature, is 10 Hz or lower.

4. The system of claim 1, wherein a resulting pole frequency variation with input signal swing is removed, thereby providing a linear filtering.

5. A method for implementing ultra large resistance on-chip without physical use of a resistor component that is sensitive to pA levels of leakage and that is either not available in advanced process nodes 20 nm or prohibitive in die area cost due to lack of high sheet resistance components, to allow integration of a large external de-coupling capacitor for realizing a fully integrated on-chip filter pole that is low in frequency, comprising; a. using a switching capacitor circuit network to implement the ultra large resistor, wherein the switching capacitor circuit network comprises two switches connected to an input and an output of a switching capacitor (C.sub.s), respectively, in an alternating manner at a selected frequency (f.sub.SW), wherein the switching capacitor circuit network is connected to a common mode reference of a system and is used for fixing a DC bias level of the system, and wherein a filter capacitor (C.sub.HPF) is connected between an input and the switching capacitor circuit network; and b. setting a pole frequency to be a function of a ratio of capacitance of the filter capacitor (C.sub.HPF) and the switching capacitor (C.sub.s), instead of a RC product, wherein a capacitance of the filter capacitor is substantially larger than a capacitance of the switching capacitor, thereby attenuating an impact of switching noise by the ratio of capacitance of the capacitors.

6. The method of claim 5, wherein the capacitance of the filter capacitor is 100 times or more larger than the capacitance of the switching capacitor.

7. The method of claim 5, wherein a resulting pole frequency variation, which varies with process, bias voltage, and temperature, is 10 Hz or lower.

8. The method of claim 5, wherein a resulting pole frequency variation with input signal swing is removed, thereby providing a linear filtering.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The appended drawings illustrate several embodiments of the invention and are not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments

(2) FIG. 1 shows a generic single-ended to differential conversion instrumentation amplifier with ac coupled inputs using external off chip components

(3) FIG. 2 shows the current state of the art single-ended to differential conversion instrumentation amplifier with AC coupled inputs using integrated on chip components

(4) FIG. 3 shows a single-ended to differential conversion instrumentation amplifier with ac coupled inputs using integrated on chip components, using switched capacitor techniques to emulate ultra large resistors in accordance with one embodiment of the invention.

DETAILED DESCRIPTION

(5) Aspects of the present disclosure are illustrated in the above-identified drawings and are described below. In the description, like or identical reference numerals are used to identify common or similar elements. The drawings are not necessarily to scale and certain features may be shown exaggerated in scale or in schematic in the interest of clarity and conciseness.

(6) Embodiments of the invention relate to innovative solutions, which address some or all of the above-mentioned limitations in the prior art and result in a robust solution to the requirement at hand, while also occupying significantly less die area. Embodiments of the invention achieve this by using a switched capacitor scheme to effectively implement a large resistor. Emulating a resistor using a switched capacitor circuit to implement ultra large resistances enables integration of large external input de-coupling capacitors. Embodiments of the invention result in several benefits and make it viable at a system level, when it otherwise might not be possible.

(7) Specifically, embodiments of the invention use novel architectures and methods to integrate ultra large resistance on-chip. In the following description, details of embodiments of the invention are illustrated with reference to the drawings. One skilled in the art would appreciate that specific examples described are for illustration only and other modifications and variations are possible without departing from the scope of the invention.

(8) FIG. 3 describes an exemplary embodiment (300) of the invention. As shown in FIG. 3, the topology of an integrated input de-coupling filter block (317), which uses a filter capacitor C.sub.HPF (301) and a switched capacitor network that comprises switches (302 and 304) and a capacitor C.sub.S (314) to effectively implement a large filter resistor (equivalent to the resistor R.sub.HPF (202) in FIG. 2), as opposed to the techniques explained previously in the prior art section. In other words, two switches (302 and 304) in conjunction with the capacitor Cs (314) in FIG. 3 function as an equivalent of the large filter resistor R.sub.HPF (202) in FIG. 2.

(9) In this description, a switched capacitor network functions as a switched capacitor resistor. The switched capacitor resistor is made of a switching capacitor C (shown as C.sub.s in FIG. 3) and two switches .sub.1 and .sub.2 (shown as 302 and 304 in FIG. 3) that alternately connect with the capacitor C.sub.s at a given frequency (switching frequency f.sub.SW) to the input and output sides of the capacitor C.sub.s.

(10) In accordance with embodiments of the invention, a switched capacitor circuit effectively implements a large filter resistor (equivalent to the resistor R.sub.HPF (202) in FIG. 2). This may be termed an ultra large resistor, which has a resistance of mega ohms or higher (M), preferably greater than 10 M, and more preferably greater than 100 M.

(11) The operating principle of this solution is explained in the next section. In addition, how the solution overcomes some or all of the limitations in the prior art approach will be highlighted. As will be seen later, our proposed solution allows us to integrate all the elements needed on-chip (305), without requiring any external off-chip components. The rest of the system comprises the elements (306) through (312), corresponding to those described in FIG. 2.

(12) By alternatively switching the capacitor C.sub.S (314) from the common-mode voltage V.sub.CM (315) to the error amplifier (303) input terminal (316) at a frequency f.sub.SW that is at least twice the band of interest, the DC voltage at the node (316) gets eventually set to the desired common-mode V.sub.CM (315), exhibiting a first order exponential settling response, characteristic of a low pass filter, with a time constant that is effectively determined by

(13) $=\left(\frac{1}{f_{\mathrm{SW}}{C}_S}\right)C_{\mathrm{HPF}}.$

(14) Once the steady-state operation is reached, the same time constant is in effect with respect to the input signal V.sub.IN (312), the only difference being that it appears as a high pass filter response, providing the required de-coupling from the input signal. It is easy to see from the above equation for T that the R.sub.HPF described earlier (see 202 in FIG. 2) is effectively given by

(15) $R_{\mathrm{HPF}}=\left(\frac{1}{f_{\mathrm{SW}}{C}_S}\right).$
Now that we have described the operation of the circuit, we will describe the decisive advantages of this scheme in the next few paragraphs.

(16) First, let us look at the area savings. An exemplary calculation with a switching frequency of 20 KHz (at the edge of the audio band and easily >2 the max microphone signal band of 7 KHz or so) shows that we would require a C.sub.S of 307 fF, to realize 163 M effectively. Assuming a metal capacitor density of 0.2 fF/m.sup.2 that is a good representation of Integrated Circuit (IC) processes, this translates into an area of 3000 m.sup.2 (0.003 mm.sup.2) for 2 capacitors, one for either side. Comparing this with the 0.27 mm.sup.2 arrived at earlier, we can see that there is an area saving of almost 100.

(17) Second, by looking at the expression for the time constant , it is to be noted that it only depends on the capacitance ratio of C.sub.HPF to C.sub.S and the switching frequency f.sub.SW. While the switching frequency is a precise and stable parameter, derived from either a Real Time Clock (RTC system) or from a system clock in audio systems (accurate to <1% drift), it is a well-known fact in the analog world that capacitor ratios can be made to match precisely with careful layout techniques to <1%. Thus, it is evidently clear that the pole location of the desired filtering is as accurate as it can ever get (easily within a few percent), with an improvement of at least 10, if not more, over current state of the art, thereby setting this solution on a pedestal far above the current state of the art explained previously.

(18) It can be gleaned by analysis of the switched capacitor circuit formed by switches (302), (304) and capacitor C.sub.S (314) that the effective impedance of this network largely depends on the switching frequency (f.sub.SW) and the value of C.sub.S and can be made independent of the impedance of the switches (302) and (304) by sizing them appropriately. Therefore, even if the switch impedance of (302) changes with the input signal, it does not impact the filter pole location mentioned above, thereby removing the non-linear filtering effect limitation that was described earlier in the prior art section. This is a highly preferred aspect of our solution as well. It should be mentioned here that practical implementation considerations will limit how low the value of C.sub.S is made. One skilled in the art would be able to determine this value for the desired outcome.

(19) Finally, the sensitivity of the proposed solution to leakage current losses at the node (316) is also very low, another significant aspect of our solution. For example, in the event of a 10 pA leakage loss for half the switching period, the resulting voltage drop is only 2.5 V, as compared to the 1.63 mV error of the prior art solutions. Further, this error never accumulates, as in the next clock cycle, it is provided from the common-mode node by the C.sub.S. Again, an overall improvement of over 500 is achieved, as compared to current state of the art. In fact, from this perspective, the solution provided by embodiments of the invention is probably the only one that can perform correctly in the presence of leakage losses. In contrast, the prior art solutions pretty much break down at even moderate leakages (common in advanced CMOS process nodes).

(20) With regards to potential issues due to switching noise propagating to the outputs, it is to be noted that the proposed topology is architected in such a way that any such noise is a common-mode signal to the instrumentation amplifier system and is therefore rejected at the differential output (311) of the amplifier by the Common-Mode Rejection Ratio (CMRR) of the system, which is typically high (>60 dB). While this aspect is common to the prior art as well, the uniqueness of our solution lies in the extra attenuation to the injected switching noise into the amplifier inputs. Circuit analysis shows that this attenuation factor, to a first order, is given by

(21) $\left(\frac{C_{\mathrm{HPF}}}{C_S}\right),$
which in our case is about 50 dB. Thus, the overall rejection to this noise at the instrumentation amplifier output is >110 dB, which is extremely high. As a result, the solution provided by embodiments of the invention is very immune to switching noise, which makes it very attractive. For these reasons, in preferred embodiments of the invention, the capacitance of the filter capacitor (C.sub.HPF) is substantially larger (e.g., 100 times greater or more) than that of the switching capacitor (C.sub.S). In this context, substantially larger means at least 10 times, preferably at least 30 times, more preferably at least 100 times, and most preferably at least 300 times.

(22) Thus, in accordance with embodiments of the invention, the proposed architecture has been shown to provide a significantly superior and competitive product by eliminating some or all of the limitations of the prior art, and even making a solution viable, when it otherwise might not be. Embodiments of the invention are unique in that they adapt and apply a known circuit technique in a larger system level scenario in a way that has never been done before, to repeat the benefits that are so valuable in terms of the overall customer requirements at a product level.

(23) Embodiments of the invention may have one or more of the following advantages: embodiments of the invention allow one to implement ultra large resistance and easily integrate on chip external ac de-coupling capacitors. Embodiments of the invention may be used to implement filters in the range of few Hz up to few tens of Hz, while still resulting in a robust, well controlled solution. Embodiments of the invention also have the added merits of requiring much less silicon areas, as compared to the current state of the art.

(24) It is to be noted that embodiments of the invention described herewith are equally applicable to low frequency systems other than audio, where similar architectural requirements are to be met, though the numbers to be implemented might be of a different magnitude.

(25) While embodiments of the invention have been illustrated with a limited number of examples, one skilled in the art would appreciate that other modifications and variations are possible without departing from the scope of the invention. Therefore, the scope of the invention should be limited only by the attached claims.