CLOSED-LOOP CLOCK CALIBRATION METHOD, TERMINAL AND COMPUTER STORAGE MEDIUM

Abstract

Disclosed is a closed-loop clock calibration method, comprising: performing clock calibration according to a calibration factor of an n.sup.th calibration period within the n.sup.th calibration period, and obtaining a calibration error of the n.sup.th calibration period; and according to the calibration error and calibration factor of the n.sup.th calibration period, obtaining a calibration factor of an (n+1).sup.th calibration period, n being a positive integer. Also disclosed are a terminal and a computer storage medium.

Claims

1. A closed-loop clock calibration method, comprising: in an n.sup.th calibration period, performing clock calibration according to a calibration factor of the n.sup.th calibration period, and obtaining a calibration error of the n.sup.th calibration period; and obtaining a calibration factor of an (n+1).sup.th calibration period according to the calibration error and the calibration factor of the n.sup.th calibration period, wherein n is a positive integer.

2. The method according to claim 1, further comprising: presetting a calibration factor of a first calibration period.

3. The method according to claim 2, wherein presetting the calibration factor of the first calibration period comprises: obtaining a calibration factor according to a theoretical frequency value of a system clock and a theoretical frequency value of a low-frequency clock; and presetting the obtained calibration factor as the calibration factor of the first calibration period.

4. The method according to claim 2, wherein presetting the calibration factor of the first calibration period comprises: in a preset time period, causing the system clock and the low-frequency clock to operate simultaneously and count respectively; after the preset time period, calculating a ratio of a count value of a system clock period to a count value of a low-frequency clock period to obtain a calibration factor; and presetting the obtained calibration factor as the calibration factor of the first calibration period.

5. The method according to claim 1, wherein, in the n.sup.th calibration period, performing clock calibration according to the calibration factor of the n.sup.th calibration period and obtaining the calibration error of the n.sup.th calibration period comprises: in the n.sup.th calibration period, converting the low-frequency clock into the system clock through multiplying the low-frequency clock by the calibration factor of the n.sup.th calibration period, so as to recover system timing; and obtaining the calibration error Δt of the n.sup.th calibration period according to the following formula:
Δt=T.sub.S−T.sub.C wherein T.sub.S is actual system timing, and T.sub.C is the system timing recovered through the calibration factor of the n.sup.th calibration period.

6. The method according to claim 1, wherein obtaining the calibration factor of the (n+1).sup.th calibration period according to the calibration error and calibration factor of the n.sup.th calibration period comprises: deriving the calibration factor f(n+1) of the (n+1).sup.th calibration period from the calibration error and calibration factor of the n.sup.th calibration period according to the following formula: $f\left(n+1\right)=f\left(n\right)+\frac{\Delta .Math..Math.t}{T_{\mathrm{Sleep}}}.Math.f\left(n\right)$ wherein f(n)is the calibration factor of the n.sup.th calibration period, Δt is the calibration error of the n.sup.th calibration period, and T.sub.Sleep is a sleep time period in a Discontinuous Reception, DRX, time period.

7. The method according to claim 1, wherein the calibration period is preset to be at least one DRX time period.

8. A terminal, comprising: a memory storing processor-executable instructions; and a processor arranged to execute the stored processor-executable instructions to perform steps of: in an n.sup.th calibration period, performing clock calibration according to a calibration factor of the n.sup.th calibration period, and obtaining a calibration error of the n.sup.th calibration period; and obtaining a calibration factor of an (n+1).sup.th calibration period according to the calibration error and calibration factor of the n.sup.th calibration period, wherein n is a positive integer.

9. The terminal according to claim 8, wherein the processor is arranged to execute the stored processor-executable instructions to further perform a step of: presetting a calibration factor of a first calibration period.

10. The terminal according to claim 9, wherein the processor is arranged to execute the stored processor-executable instructions to further perform a step of: obtaining a calibration factor according to a theoretical frequency value of a system clock and a theoretical frequency value of a low-frequency clock, and presetting the obtained calibration factor as the calibration factor of the first calibration period.

11. The terminal according to claim 9, wherein the processor is arranged to execute the stored processor-executable instructions to further perform a step of: in a preset time period, causing the system clock and the low-frequency clock to operate simultaneously and count respectively; after the preset time period, calculating a ratio of a count value of a system clock period to a count value of a low-frequency clock period to obtain a calibration factor; and presetting the obtained calibration factor as the calibration factor of the first calibration period.

12. The terminal according to claim 8, wherein the calibration period is preset to be at least one Discontinuous Reception, DRX, time period.

13. A non-transitory computer storage medium comprising a set of instructions, wherein the instructions, when being executed, cause at least one processor to execute a closed-loop clock calibration method, the method comprising: in an n.sup.th calibration period, performing clock calibration according to a calibration factor of the n.sup.th calibration period, and obtaining a calibration error of the n.sup.th calibration period; and obtaining a calibration factor of an (n+1).sup.th calibration period according to the calibration error and the calibration factor of the n.sup.th calibration period, wherein n is a positive integer.

14. The method according to claim 2, wherein the calibration period is preset to be at least one DRX time period.

15. The method according to claim 3, wherein the calibration period is preset to be at least one DRX time period.

16. The method according to claim 4, wherein the calibration period is preset to be at least one DRX time period.

17. The method according to claim 5, wherein the calibration period is preset to be at least one DRX time period.

18. The method according to claim 6, wherein the calibration period is preset to be at least one DRX time period.

19. The terminal according to claim 9, wherein the calibration period is preset to be at least one DRX time period.

20. The terminal according to claim 10, wherein the calibration period is preset to be at least one DRX time period.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0033] FIG. 1 is a schematic structure diagram of a DRX time period according to a related technology.

[0034] FIG. 2 is a schematic implementation flowchart of a closed-loop clock calibration method according to an embodiment of the disclosure.

[0035] FIG. 3 is a schematic structure diagram of a terminal according to an embodiment of the disclosure.

DETAILED DESCRIPTION

[0036] According to embodiments of the disclosure, in the n.sup.th calibration period, clock calibration is performed according to a calibration factor of an n.sup.th calibration period, and a calibration error of the n.sup.th calibration period is obtained; and a calibration factor of an (n+1).sup.th calibration period is obtained according to the calibration error and calibration factor of the n.sup.th calibration period, where n is a positive integer.

[0037] A specific implementations of the disclosure will be described below with reference to the drawings.

[0038] As shown in FIG. 2, a closed-loop clock calibration flow provided by an embodiment of the disclosure includes the following steps.

[0039] Step S201: in an n.sup.th calibration period, clock calibration is performed according to a calibration factor of the n.sup.th calibration period, and a calibration error of the n.sup.th calibration period is obtained, where n is a positive integer.

[0040] Here, the calibration period T is usually at least one a Discontinuous Reception (DRX) time period T.sub.DRX, T.sub.DRX=T.sub.Active+T.sub.Sleep, where T.sub.Active is an active time period in the DRX time period T.sub.DRX, and T.sub.Sleep is a sleep time period in the DRX time period T.sub.DRX.

[0041] Here, a calibration factor used in a first calibration period is an initial calibration factor, and the initial calibration factor may be preset in the following two manners.

[0042] A first manner a calibration factor f(1) is derived from a theoretical frequency value of a system clock and a theoretical frequency value of a low-frequency clock according to the following formula:

[00002]$f\left(1\right)=\frac{F_d}{F_g}$

[0043] where F.sub.d is the theoretical frequency value of the low-frequency clock, and F.sub.g is the theoretical frequency value of the system clock (high-frequency clock).

[0044] The obtained calibration factor f(1) is preset as the calibration factor of the first calibration period.

[0045] A second manner clock calibration of a preset time period is performed to obtain a calibration factor by virtue of the system clock. A specific implementation process includes the following steps.

[0046] The system clock and the low-frequency clock are caused to operate simultaneously and count respectively in the preset time period.

[0047] A ratio of a count value of a system clock period to a count value of a low-frequency clock period is calculated to obtain a calibration factor after the preset time period.

[0048] The obtained calibration factor is preset as the calibration factor of the first calibration period.

[0049] The step of within the n.sup.th calibration period performing clock calibration according to the calibration factor of the n.sup.th calibration period and obtaining the calibration error of the n.sup.th calibration period will be described below in detail.

[0050] In the n.sup.th calibration period, when an active stage is entered, the low-frequency clock of a sleep stage is converted into the system clock through multiplying the low-frequency clock of the sleep stage by the calibration factor of the n.sup.th calibration period, thereby recovering system timing in the n.sup.th calibration period. The calibration error Δt of the n.sup.th calibration period is derived according to the following formula:

Δt=T.sub.S−T.sub.C,

[0051] where T.sub.S is actual system timing, and T.sub.C is the system timing recovered through the calibration factor of the n.sup.th calibration period.

[0052] Here, the actual system timing T.sub.S may be obtained by a frequency and time synchronization process after the system timing is recovered. There is a conventional means to obtain the actual system timing T.sub.S, and the details thereof will not be elaborated.

[0053] It is should be noted that, when Δt>0, i.e., when the timing recovered through the calibration factor of the n.sup.th calibration period is earlier than the actual timing, the calibration factor of the n.sup.th calibration period should be decreased and the regulated calibration factor is adopted for clock calibration in a next calibration period. When Δt<0, i.e., when the timing recovered through the calibration factor of the n.sup.th calibration period is later than the actual timing, the calibration factor of the n.sup.th calibration period should be increased and the regulated calibration factor for clock calibration in the next calibration period.

[0054] Step S202: a calibration factor of an (n+1).sup.th calibration period is obtained according to the calibration error and calibration factor of the n.sup.th calibration period.

[0055] Specifically, before the (n+1).sup.th calibration period, the calibration factor f(n+1) of the (n+1).sup.th calibration period is derived from the calibration error and calibration factor of the n.sup.th calibration period according to the following formula:

[00003]$f\left(n+1\right)=f\left(n\right)+\frac{\Delta .Math..Math.t}{T_{\mathrm{Sleep}}}.Math.f\left(n\right),$

[0056] where f(n) is the calibration factor of the n.sup.th calibration period, Δt is the calibration error of the n.sup.th calibration period, and T.sub.Sleep is the sleep time period in the DRX time period.

[0057] According to the embodiment of the disclosure, before the (n+1).sup.th calibration period, the calibration factor of the n.sup.th calibration period is regulated according to the calibration error of the n.sup.th calibration period, so as to obtain the calibration factor of the (n+1).sup.th calibration period. The calibration factor of the (n+1).sup.th calibration period is adopted for clock calibration in the (n+1).sup.th calibration period, and so on, to implement closed-loop clock calibration. In this manner, closed-loop clock calibration is performed according to the calibration error, and thus clock calibration accuracy can be improved. Moreover, since the calibration method according to the embodiment of the disclose is independent of the system clock, the problem of excessively long calibration time in the conventional art is solved, and thus standby power consumption of a terminal is reduced.

[0058] In order to make the embodiment of the disclosure to be clearer, a data exchange flow in the embodiment of the disclosure will be described below in detail with a specific embodiment.

First Embodiment

[0059] A terminal presets a calibration period T to be a DRX time period T.sub.DRX, and presets a calibration factor of a first calibration period to be f(1).

[0060] In the first calibration period, when an active stage is entered, a low-frequency clock of a sleep stage is converted into a system clock through multiplying the low-frequency clock of the sleep stage by f(1), so as to recover system timing. Then, a calibration error Δt.sub.1 caused by clock calibration with f(1) is calculated from actual system timing T.sub.S1 and the system timing T.sub.C1 recovered through f(1), according to Δt.sub.1=T.sub.S1−T.sub.C1.

[0061] Then, before a second calibration period, f(1) is corrected to obtain f(2) according to the calibration error Δt.sub.1. The f(2) is adopted for clock calibration in the second calibration period.

[0062] In the second calibration period, when an active stage is entered, a low-frequency clock of a sleep stage is converted into a system clock through multiplying the low frequency clock of the sleep stage by f(2), so as to recover system timing. Then, a calibration error Δt.sub.2 caused by clock calibration with f(2) is calculated from actual system timing T.sub.S2 and the system timing T.sub.C2 recovered through f(2), according to Δt.sub.2=T.sub.S2−T.sub.C2.

[0063] Then, before a third calibration period, f(2) is corrected to obtain f(3) according to the calibration error Δt.sub.2. The f(3) is adopted for clock calibration in the third calibration period.

[0064] In this manner, clock calibration is performed according to a corrected calibration factor of a previous calibration period in an n.sup.th calibration period, and a calibration error of the n.sup.th calibration period is obtained. A calibration factor of the n.sup.th calibration period is corrected according to the calibration error of the n.sup.th calibration period, so as to obtain a corrected calibration factor. The corrected calibration factor is adopted for clock calibration in a next calibration period. In this way, the closed-loop clock calibration can be implemented.

[0065] In order to implement the abovementioned method, an embodiment of the disclosure provides a terminal. A principle of the terminal for solving the problem is similar to the method, so that an implementation process and implementation principle of the terminal may refer to descriptions about an implementation process and implementation principle of the method, and repeated parts will not be elaborated.

[0066] As shown in FIG. 3, the terminal provided by the embodiment of the disclosure includes: a calibration error extraction unit 301 and a calibration factor regulation unit 302.

[0067] The calibration error extraction unit 301 is arranged to perform clock calibration according to a calibration factor of an n.sup.th calibration period in the nth calibration period, and obtain a calibration error of the n.sup.th calibration period.

[0068] The calibration factor regulation unit 302 is arranged to obtain a calibration factor of an (n+1).sup.th calibration period according to the calibration error and calibration factor of the n.sup.th calibration period, where n is a positive integer.

[0069] The calibration period is preset to be at least one DRX time period.

[0070] The division of the above function units or modules is merely a preferred implementation provided by the embodiment of the disclosure, and is not intended to limit the disclosure.

[0071] Furthermore, the terminal may further include an initial value presetting unit 303.

[0072] The initial value presetting unit 303 is arranged to preset a calibration factor of a first calibration period.

[0073] Specially, the initial value presetting unit 303 is arranged to obtain a calibration factor according to a theoretical frequency value of a system clock and a theoretical frequency value of a low-frequency clock, and preset the obtained calibration factor as the calibration factor of the first calibration period.

[0074] Specially, the initial value presetting unit 303 is arranged to cause the system clock and the low-frequency clock to operate simultaneously and count respectively in a preset time period, calculate a ratio of a count value of a system clock period to a count value of a low-frequency clock period to obtain a calibration factor after the preset time period, and preset the obtained calibration factor as the calibration factor of the first calibration period.

[0075] In practice, the calibration error extraction unit 301, the calibration factor regulation unit 302 and the initial value presetting unit 303 may be implemented by a Central Processing Unit (CPU), Micro Processing Unit (MPU), Digital Signal Processor (DSP) or Field-Programmable Gate Array (FPGA) located in the terminal.

[0076] Those skilled in the art should know that the embodiment of the disclosure may be provided as a method, a system or a computer program product. Therefore, the disclosure may adopt a form of hardware embodiment, software embodiment or combined software and hardware embodiment. Moreover, the disclosure may adopt a form of computer program product implemented on one or more computer-available storage media (including, but not limited to, a disk memory, an optical memory and the like) including computer-available program codes.

[0077] The disclosure is described with reference to flowcharts and/or block diagrams of the method, equipment (system) and computer program product according to the embodiment of the disclosure. It should be understood that each flow and/or block in the flowcharts and/or the block diagrams and combinations of the flows and/or blocks in the flowcharts and/or the block diagrams may be implemented by computer program instructions. These computer program instructions may be provided for a universal computer, a dedicated computer, an embedded processor or a processor of other programmable data processing equipment to generate a machine, so that a device for realizing a function specified in one flow or more flows in the flowcharts and/or one block or more blocks in the block diagrams is generated by the instructions executed through the computer or the processor of the other programmable data processing equipment.

[0078] These computer program instructions may also be stored in a computer-readable memory capable of guiding the computer or the other programmable data processing equipment to work in a specific manner, so that a product including an instruction device may be generated by the instructions stored in the computer-readable memory, the instruction device realizing the function specified in one flow or many flows in the flowcharts and/or one block or many blocks in the block diagrams. These computer program instructions may further be loaded onto the computer or the other programmable data processing equipment, so that a series of operating steps are executed on the computer or the other programmable data processing equipment to generate processing implemented by the computer, and steps for realizing the function specified in one flow or many flows in the flowcharts and/or one block or many blocks in the block diagrams are provided by the instructions executed on the computer or the other programmable data processing equipment.

[0079] On such a basis, an embodiment of the disclosure further provides a computer storage medium, which includes a set of instructions, the instructions being executed to cause at least one processor to execute the abovementioned closed-loop clock calibration method.

[0080] The method of the disclosure is not limited to the embodiments in the detailed description, and other implementation modes obtained by those skilled in the art according to the technical solutions of the disclosure shall also fall within the scope of technical innovation of the disclosure.

[0081] Obviously, those skilled in the art may make various modifications and transformations to the disclosure without departing from the spirit and scope of the disclosure. Therefore, if these modifications and transformations of the disclosure fall within the scope of the claims of the disclosure and an equivalent technology thereof, the disclosure is also intended to include these modifications and transformations.