Fluorinated graphene passivated AlGaN/GaN-based HEMT device and manufacturing method

Abstract

An AlGaN/GaN HEMT based on fluorinated graphene passivation and a manufacturing method thereof. Monolayer graphene (108) is transferred to an AlGaN (104) surface, is treated by using fluoride ions and then is insulated to thereby replace a conventional nitride passivation layer. Then, a high-k material (109) is grown on the graphene (108), and the high-k material (109) and the graphene (108) are jointly used as a gate dielectric for preparing an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene (108) has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. The structure and the method are simple, the effect is remarkable and the application prospect in technical fields of microelectronics and solid-state electronics is wide.

Claims

1. An AlGaN/GaN HEMT based on fluorinated graphene passivation, characterized in that the HEMT comprises: a substrate; a GaN layer located above the substrate; an AlGaN layer bonded to the GaN layer, a two-dimensional electron gas surface formed by an interface between the AlGaN layer and the GaN layer; a source and a drain formed at two ends of the AlGaN layer; an insulated graphene passivation layer bonded to a surface of the AlGaN layer, wherein the insulated graphene passivation layer is fluorinated; a gate dielectric layer bonded to a surface of the insulated graphene passivation layer; and a gate metal layer bonded to a surface of the gate dielectric layer.

2. A method for manufacturing AlGaN/GaN HEMT based on fluorinated graphene passivation of claim 1, characterized in that the method comprises the following steps: 1) providing a substrate and sequentially forming a GaN layer and an AlGaN layer on a surface of the substrate, an interface between the GaN layer and the AlGaN layer forming a two-dimensional electron gas surface; 2) forming a source ohmic contact and a drain ohmic contact on the AlGaN layer; 3) covering a surface of the AlGaN layer with graphene and performing fluorination treatment to the graphene to form an insulated graphene passivation layer; and 4) forming a gate dielectric layer on a surface of the insulated graphene passivation layer and forming a gate metal layer on a surface of the gate dielectric layer.

3. The manufacturing method for the AlGaN/GaN HEMT based on fluorinated graphene passivation of claim 1 according to claim 2, characterized in that the method further comprises the following steps: 5) performing mesa isolation to a device region; 6) depositing an isolating layer on a surface of the device; 7) etching windows corresponding to the source ohmic contact, the drain ohmic contact and the gate metal layer in the isolating layer; and 8) manufacturing metal extraction electrodes based on each window.

4. The manufacturing method for the AlGaN/GaN HEMT based on fluorinated graphene passivation of claim 1 according to claim 2, characterized in that method for covering the surface of the AlGaN layer with graphene in step 3) is selected from: a. growing graphene on a Cu substrate and then transferring the graphene grown on the Cu substrate to the surface of the AlGaN layer; or b. directly growing graphene on the surface of the AlGaN layer.

5. The manufacturing method for the AlGaN/GaN HEMT based on fluorinated graphene passivation of claim 1 according to claim 2, characterized in that step 3) of performing fluorination treatment to the graphene comprises the following step: treating the graphene by using SF6 plasmas, treatment time being 60-120 s.

6. The manufacturing method for the AlGaN/GaN HEMT based on fluorinated graphene passivation of claim 1 according to claim 2, characterized in that step 1) further comprises a step of forming a buffer layer between the substrate and the GaN layer.

7. The manufacturing method for the AlGaN/GaN HEMT based on fluorinated graphene passivation of claim 1 according to claim 2, characterized in that the gate dielectric layer is a high-k gate dielectric layer.

8. The AlGaN/GaN HEMT based on fluorinated graphene passivation according to claim 1, characterized in that the substrate comprises a silicon substrate in a (111) crystal orientation.

9. The AlGaN/GaN HEMT based on fluorinated graphene passivation according to claim 1, characterized in that the gate dielectric layer is a high-k dielectric layer.

10. The AlGaN/GaN HEMT based on fluorinated graphene passivation according to claim 1, characterized in that a buffer layer is provided between the substrate and the GaN layer.

11. The AlGaN/GaN HEMT based on fluorinated graphene passivation according to claim 10, characterized in that a thickness range of the buffer layer is 2-10 m.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a flowchart of steps of a method for manufacturing an AlGaN/GaN HEMT based on fluorinated graphene passivation provided by the present invention.

(2) FIG. 2 to FIG. 5 illustrates structural schematic views in steps of a method for AlGaN/GaN HEMT based on fluorinated graphene passivation provided by the present invention.

(3) FIG. 6 and FIG. 7 illustrate I-V performance curve comparison charts of an AlGaN/GaN HEMT based on fluorinated graphene passivation provided by the present invention and a non-graphene passivated HEMT.

DESCRIPTION OF COMPONENT MARK NUMBERS

(4) 101 Substrate 102 Buffer layer 103 GaN layer 104 Two-dimensional electron gas surface 105 AlGaN layer 106 Source 107 Drain 108 Insulated graphene passivation layer 109 Gate dielectric layer 110 Gate metal layer S11-S18 Steps 1) to step 8)

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(5) The implementation modes of the present invention will be described below through specific examples. One skilled in the art can easily understand other advantages and effects of the present invention according to content disclosed in the description. The present invention may also be implemented or applied through other different specific implementation modes. Various modifications or variations may be made to all details in the description based on different points of view and applications without departing from the spirit of the present invention.

(6) Please refer to FIG. 1 to FIG. 7. It needs to be stated that the drawings provided in the following embodiments are just used for schematically describing the basic concept of the present invention, thus only illustrate components only related to the present invention and are not drawn according to the numbers, shapes and sizes of components during actual implementation, the configuration, number and scale of each component during actual implementation thereof may be freely changed, and the component layout configuration thereof may be more complex.

(7) As illustrated in FIG. 5, this embodiment provides an AlGaN/GaN HEMT based on fluorinated graphene passivation, and the HEMT comprises: a substrate 101; a GaN layer 103 located above the substrate 101; an AlGaN layer 104 bonded to the GaN layer 103, an interface between the AlGaN layer 104 and the GaN layer 103 forming a two-dimensional electron gas surface; a source 106 and a drain 107 formed at two ends of the AlGaN layer 104; an insulated graphene passivation layer 108 bonded to a surface of the AlGaN layer 104; a gate dielectric layer 109 bonded to a surface of the insulated graphene passivation layer 108; and a gate metal layer 110 bonded to a surface of the gate dielectric layer 109.

(8) As illustrated in FIG. 5, as an example, a buffer layer 102 is provided between the substrate 101 and the GaN layer 103. The buffer layer 102 can effectively buffer stress mismatch and lattice mismatch between the substrate 101 and the GaN layer 103, and thus greatly improve the growth quality of the GaN layer 103.

(9) As an example, the substrate 101 comprises a silicon substrate in a (111) crystal orientation. Of course, in other embodiments, the substrate 101 may also be a SiC substrate or the like and is not limited to the example here.

(10) As an example, a thickness range of the buffer layer 102 is 2-10 m. In this embodiment, the thickness of the buffer layer 102 is 3.9 m.

(11) As an example, the gate dielectric layer 109 is a high-k dielectric layer 109. The high-k dielectric layer 109 may be Al.sub.2O.sub.3, HfO.sub.2 or the like, and is not limited to the example here.

(12) In the present invention, the insulated graphene passivation layer 108 is used for replacing a conventional nitride passivation layer, then a high-k material is grown on the insulated graphene passivation layer 108, and the high-k material and the insulated graphene passivation layer 108 are jointly used as a gate dielectric for forming an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. Meanwhile, the monolayer graphenealso has very good isolation performance and can prevent the AlGaN surface from being oxidized in the growth process of the high-k material to produce surface traps, so as to achieve a passivation effect. In addition, the fluorinating process can introduce negative charges into the graphene, the positive shift of threshold voltage of the HEMT is facilitated and a possibility is provided for realizing an enhancement mode.

(13) As illustrated in FIG. 1 to FIG. 5, this invention further provides a method for manufacturing AlGaN/GaN HEMT based on fluorinated graphene passivation, and the method comprises the following steps:

(14) As illustrated in FIG. 1 and FIG. 2, firstly step 1) S11 is performed, i.e., a substrate 101 is provided and a GaN layer 103 and an AlGaN layer 104 are sequentially formed on a surface of the substrate 101, wherein an interface between the GaN layer 103 and the AlGaN layer 104 forms a two-dimensional electron gas surface.

(15) In this embodiment, the method further comprises a step of forming a buffer layer 102 between the substrate 101 and the GaN layer 103. The buffer layer 102 can effectively buffer stress mismatch and lattice mismatch between the substrate 101 and the GaN layer 103, and thus greatly improve the growth quality of the GaN layer 103.

(16) As illustrated in FIG. 1 and FIG. 3, then step 2) S12 is performed, i.e., a source ohmic contact and a drain ohmic contact are formed on the AlGaN layer 104.

(17) Specifically, firstly a photoresist pattern is manufactured, then Ti/Al/Ni/Au metal lamination layers (the thicknesses of which are respectively 20/100/50/100 nm) are evaporated by adopting electron beams, then excess metal lamination layers are removed by adopting a lift-off process, annealing is performed, and then a source ohmic contact and a drain ohmic contact are formed on the AlGaN layer 104.

(18) As illustrated in FIG. 1 and FIG. 4, then step 3) S13 is performed, i.e., graphene is formed on a surface of the AlGaN layer 104 and fluorination treatment is performed to the graphene to form an insulated graphene passivation layer 108.

(19) As an example, the step of forming the graphene on the surface of the AlGaN layer 104 comprises: growing graphene on a Cu substrate 101; and then transferring the graphene grown on the Cu substrate 101 to the surface of the AlGaN layer 104.

(20) As an example, the step of performing fluorination treatment to the graphene comprises the following step: treating the graphene by using SF6 plasmas, wherein treatment time is 60-120 s. In this embodiment, the treatment time is selected to be 90 s.

(21) As illustrated in FIG. 1 and FIG. 5, then step 4) S14 is performed, i.e., a gate dielectric layer 109 is formed on a surface of the insulated graphene passivation layer 108 and a gate metal layer 110 is formed on a surface of the gate dielectric layer 109.

(22) As an example, the gate dielectric layer 109 is a high-k dielectric layer 109. The high-k dielectric layer 109 may be Al2O3, HfO2 or the like, and is not limited to the example here. Specifically, in this embodiment, firstly Al.sub.2O.sub.3 is deposited to certain thickness by adopting hot-process ALD (Atomic Layer Deposition), then Al.sub.2O.sub.3 is continuously deposited by adopting plasma enhanced atomic layer deposition, and an Al.sub.2O.sub.3 layer with total deposition thickness of 14 nm is deposited, and the Al.sub.2O.sub.3 layer and the insulated graphene passivation layer 108 are jointly used as a gate dielectric layer 109.

(23) As an example, the step of forming a dielectric metal layer 110 on the surface of the gate dielectric layer 109 comprises the following steps: firstly a photoresist pattern is manufactured, then Ni/Au metal lamination layers (the thicknesses of which are respectively 30/100 nm) are evaporated by adopting electron beams, and finally excess metal lamination layers are removed by adopting a lift-off process, so as to complete the preparation of the gate metal layer 110.

(24) As illustrated in FIG. 1, then step 5) S15 is performed, i.e., mesa isolation is performed to a device region.

(25) Specifically, SiO.sub.2 which is used as a mask is deposited by adopting a PECVD process, the thickness thereof is 300 nm, then a non-device region is etched by adopting ICP, and the etching depth is 350 nm, so as to complete the mesa isolation to the device region.

(26) As illustrated in FIG. 1, then step 6) S16 is performed, i.e., an isolating layer is deposited on a surface of the device.

(27) As an example, a SiO.sub.2 thin film is deposited by adopting a PECVD process and is used as an isolating layer, and the thickness thereof is 100 nm.

(28) As illustrated in FIG. 1, then step 7) S17 is performed, i.e., windows corresponding to the source ohmic contact, the drain ohmic contact and the gate metal layer 110 are etched in the isolating layer.

(29) Specifically, firstly the ohmic contacts and the SiO.sub.2 thin film on the gate metal electrode are etched by adopting an RIE method, and then the Al.sub.2O.sub.3 layer on the source ohmic contact and the drain ohmic contact is etched to etch windows corresponding to the source ohmic contact, the drain ohmic contact and the gate metal layer 110 in the isolating layer.

(30) As illustrated in FIG. 1, finally step 8) S18 is performed, i.e., metal extraction electrodes are manufactured based on each window.

(31) Specifically, firstly a photoresist pattern is manufactured, then Ti/Au metal lamination layers (the thicknesses of which are respectively 20/200 nm) are evaporated by adopting electron beams, and finally excess metal lamination layers are removed by adopting a lift-off process, so as to manufacture metal extraction electrodes in each window and complete the manufacturing of the fluorinated graphene passivated AlGaN/GaN HEMT.

(32) FIG. 6 and FIG. 7 illustrate I-V performance curve comparison charts of an AlGaN/GaN HEMT based on fluorinated graphene passivation provided by the present invention and a non-graphene passivated HEMT. In FIG. 6, the transfer characteristics of a non-graphene passivated MIS HEMT are compared with that of the HEMT provided by the present invention, and it is found that off-state current of the graphene passivated device is decreased by three orders of magnitude, and the threshold voltage is positively shifted by 3.4V as illustrated in FIG. 7; and from FIG. 6 to FIG. 7, it can be seen that the performance of the HEMT provided by the present invention is obviously improved.

(33) As described above, the AlGaN/GaN HEMT based on fluorinated graphene passivation and the manufacturing method thereof provided by the present invention have the following beneficial effects: monolayer graphene is transferred to an AlGaN surface, and is treated by using fluoride ions, and then is insulated to thereby replace a conventional nitride passivation layer. After that, a high-k material is grown on the graphene, and the high-k material and the graphene are jointly used as a gate dielectric for preparing an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. Meanwhile, the single-layer graphene also has very good isolation performance and can prevent the AlGaN surface from being oxidized in the growth process of the high-k material to produce surface traps, so as to achieve a passivation effect. In addition, the fluorinating process can introduce negative charges into the graphene, the positive shift of threshold voltage of the HEMT is facilitated and a possibility is provided for realizing an enhancement device. The structure and the method are simple, the effect is remarkable and the application prospect in technical fields of microelectronics and solid-state electronics is wide. Therefore, the present invention effectively overcomes various disadvantages in the prior art and thus has a great industrial utilization value.

(34) The above-mentioned embodiments are just used for exemplarily describing the principle and effect of the present invention instead of limiting the present invention. One skilled in the art may make modifications or changes to the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those who have common knowledge in the art without departing from the spirit and technical thought disclosed by the present invention shall be still covered by the claims of the present invention.