Hybrid return-to-zero voltage-mode DAC driver

Abstract

A voltage-mode digital-to-analog converter (DAC) includes multiple bit processing circuits to generate an output voltage responsive to a binary input. Each of the multiple bit processing circuits includes a first switch circuit and a second switch circuit. The first switch circuit is to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. The second switch circuit is to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d).

Claims

1. A voltage-mode digital-to-analog converter (DAC), comprising: multiple bit processing circuits to generate an output voltage responsive to a binary input, each of the multiple bit processing circuits including a first switch circuit to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d, a second switch circuit to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load, and wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d).

2. The voltage-mode DAC according to claim 1, wherein the first and second switch circuits each comprise push-pull voltage-mode sub-drivers.

3. The voltage-mode DAC according to claim 1, wherein the scaling value d comprises a selectable value between 0 and 1 such that the first and second output loads cooperate to exhibit hybrid direct driver and split driver characteristics.

4. The voltage-mode DAC according to claim 1, wherein the first and second switching circuits are sequenced during the first and second bit times in accordance with a return-to-zero protocol.

5. The voltage-mode DAC according to claim 1, further comprising: a current-steering output stage coupled to the third output load.

6. The voltage-mode DAC according to claim 5, wherein the current-steering output stage includes tunable current source/sink circuitry to compensate for common-mode data signals.

7. The voltage-mode DAC according to claim 1, wherein the first and second switch circuits alternatingly activate during the first and second bit times.

8. A method of operation in a voltage-mode DAC, the method comprising: operating multiple bit processing circuits to generate an output voltage responsive to a binary input, the operating of each of the multiple bit processing circuits including selectively coupling one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d, selectively coupling one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load; and wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d).

9. The method according to claim 8, wherein the operating is carried out using a return-to-zero protocol.

10. The method according to claim 8, wherein the selectively coupling to the first and second output loads is carried out in response to alternatingly activating corresponding first and second switch circuits.

11. A voltage-mode driver, comprising: a first voltage-mode sub-driver to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d, a second voltage-mode sub-driver to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load, and wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d).

12. The voltage-mode driver according to claim 11, wherein the first and second voltage-mode sub-drivers each comprise push-pull voltage-mode sub-drivers.

13. The voltage-mode DAC according to claim 11, wherein the scaling value d comprises a selectable value between 0 and 1 such that the first and second output loads cooperate to exhibit hybrid direct driver and split driver characteristics.

14. The voltage-mode DAC according to claim 11, wherein the first and second switching circuits are sequenced during the first and second bit times in accordance with a return-to-zero protocol.

15. The voltage-mode DAC according to claim 11, further comprising: a current-steering output stage coupled to the third output load.

16. The voltage-mode DAC according to claim 15, wherein the current-steering output stage includes tunable current source/sink circuitry to compensate for common-mode data signals.

17. The voltage-mode DAC according to claim 11, wherein the first and second switch circuits alternatingly activate during the first and second bit times.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

(2) FIG. 1 illustrates a conventional digital-to-analog converter (DAC).

(3) FIG. 2A illustrates further detail of one embodiment of a conventional DAC.

(4) FIG. 2B illustrates further detail of a further embodiment of a conventional DAC similar to that of FIG. 2A.

(5) FIG. 3 illustrates one embodiment of an improved DAC architecture.

(6) FIG. 4 illustrates a further embodiment of an improved DAC similar to that of FIG. 3.

(7) FIG. 5 illustrates a further embodiment of an improved DAC similar to those of FIGS. 3 and 4.

(8) FIG. 6 illustrates an output waveform resulting from the input circuitry shown in the DAC embodiment of FIG. 5.

DETAILED DESCRIPTION

(9) Embodiments of apparatus and methods for digital-to-analog conversion are disclosed. For one embodiment, a voltage-mode digital-to-analog converter (DAC) is disclosed that includes multiple bit processing circuits to generate an output voltage responsive to a binary input. Each of the multiple bit processing circuits includes a first switch circuit and a second switch circuit. The first switch circuit is to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. The second switch circuit is to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d).

(10) In a further embodiment, A method of operation in a voltage-mode DAC is disclosed. The method includes operating multiple bit processing circuits to generate an output voltage responsive to a binary input. The operating of each of the multiple bit processing circuits including selectively coupling one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. One of the multiple reference voltages is selectively coupled to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d).

(11) In yet another embodiment, a voltage-mode driver is disclosed. The voltage-mode driver includes a first voltage-mode sub-driver and a second voltage-mode sub-driver. The first voltage-mode sub-driver is to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. The second voltage-mode sub-driver is to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d).

(12) FIG. 3 illustrates a block diagram of one embodiment of a voltage-mode DAC architecture, generally designated 300, that provides for power-efficient switching operations. The architecture includes multiple bit processing circuits 302.sub.0-302.sub.n-1 corresponding to the number of bits n in each DAC codeword. Each bit processing circuit includes respective even and odd sub-drivers 304 and 306 that interface with an output impedance network 308 such that only one sub-driver is active per codeword and this alternates per codeword update. As more fully described below, the output impedance network is tunable to exhibit reduced crowbar currents, clock-dependent switching current, and minimal parasitic capacitance characteristics.

(13) Further referring to FIG. 3, for one embodiment, the even and odd sub-drivers 304 and 306 generally take the form of push-pull drivers. Such drivers generally push current into an output node in response to an input signal of a first value, and pull current from the node in response to the input signal having a second value. In this case a sub-driver 304 receives independent input signals b.sub.even-push for the push leg P1 and b.sub.even-pull for the pull leg N1. This way the sub-driver can not only be controlled as a push-pull driver by turning either b.sub.even-push or b.sub.even-pull on but it can also be turned off by turning both b.sub.even-push and b.sub.even-pull off. In this case the fourth state where both b.sub.even-push and b.sub.even-pull are turned on is a forbidden state since it would lead to a short-circuit between V.sub.DD and V.sub.SS. The input signals to sub-drivers 304 and 306 are now configured such that one sub-driver is off while the other is in push-pull mode and this alternates for each next input signal. Thus, during an even (even being arbitrary, just different than odd) bit time, a first code word is only applied to the even sub-drivers of the multiple bit processing circuits, while during an odd bit time, a second code word is only applied to the odd sub-drivers across the multiple bit processing circuits. As a result an individual sub-driver now always follows the pattern . . . -off-data-off-data- . . . such that it always starts from an off-state before being activated. This is typically called a return-to-zero (RTZ) pattern. This way even a temporary short-circuit can be avoided which could otherwise occur when one sub-driver would switch directly from push- to pull state or vise versa. Furthermore, the embodiment shown in FIG. 3 reflects a single-ended configuration for purposes of clarity, but a more practical application would be differential, involving twice the single-ended structure with inverse data for the second structure. In this case the RTZ nature would lead to clock-dependent switching currents instead of data-dependent switching currents because in the combined differential structure for each slice and at each clock cycle exactly one sub-driver turns from off to push-state, one from off to pull-state, one from push-state to off and also one from pull-state to off. And this repeats itself for every clock-cycle while the DAC is active. For some embodiments, the bitline input for each sub-driver couples to an n-channel transistor (shown as a switch, at N1) and a p-channel transistor (shown as a switch, at P1) that are disposed in series to form a push-pull switch configuration. A first supply voltage reference V.sub.DD is fed to the P-channel transistor, while the N-channel transistor couples to a ground voltage source V.sub.SS. Each sub-driver includes an output node at 310 and 312.

(14) With continued reference to FIG. 3, the output nodes at 310 and 312 connect to the output impedance network 308 via respective first and second output resistances R.sub.OUT1 and R.sub.OUT2. The resistance loads are intended to be of a same resistance value and are both proportional to a scaling value d. For one embodiment, the scaling value d ranges from 0 to 1, such as 0.40. The resistances R.sub.OUT1 and R.sub.OUT2 may differ slightly due to manufacturing variations. Also shown is a capacitance C.sub.PAR at each node 310 and also at 312 which represents the distributed parasitic capacitance at this node. When a sub-driver is active (push/pull-mode) this capacitance is irrelevant because it will be short-circuited to either V.sub.DD or V.sub.SS because one of the switches will be closed. In off-mode however, both switches are open and this will therefore lead to a certain capacitance which influences the total driver-impedance as seen from the output node 316. To reduce this effect, R.sub.OUT1 and R.sub.OUT2 are not directly connected to the DAC output node 316. Instead both resistances are tied in parallel to a driver output node at 314 that also connects to one end of a third output resistance R.sub.OUT3 that is proportional to the value (1-d), such as 0.60. The other end of the third resistance R.sub.OUT3 is tied to an aggregated DAC output node, at 316. The resulting output impedance is thus based on the scaling factor d, and a relative frequency error based on the clock frequency f, the load R.sub.OUT and the parasitic capacitance CPA of the push-pull sub-driver transistors. The output impedance may be represented by the relationship:
Z.sub.A(f.sub.REL,d)=R.sub.OUT(1d/2(if.sub.RE/d)/(1+if.sub.REL/d))
where f.sub.REL is 4f(R.sub.OUT)(C.sub.PAR). Thus, by varying or tuning the scaling factor value d, one may achieve a DAC output stage that provides benefits associated with both direct and split-driver DAC architectures. The resulting hybrid DAC architecture minimizes crowbar currents, parasitic capacitance, and provides clock-dependent switching current.

(15) In operation, as a given bit, such as b.sub.0, is received by a sub-driver, the push-pull configuration results in either V.sub.DD (in the case of b.sub.0-push being a logic 1) or V.sub.SS (in the case of b.sub.0-pull being a logic 1) being fed to the output load (d)R.sub.OUT. A switching current is thus either pushed to the output node or pulled from the output load to ground. Moreover, the sub-drivers in each bit processing circuit alternate in an even and odd fashion, such that for a first bit time, the even sub-driver is active while the odd sub-driver is inactive. For a subsequent bit time, the even sub-driver is inactive while the odd sub-driver is active. This works well for a return-to-zero (RTZ) switching sequence or protocol, where the DAC output is forced to start from zero, reach its final analog value, and return to zero all within a single bit clock period. Utilizing an RTZ switching protocol prevents the switching current from being data-dependent, and instead, becoming clock-dependent. A clock-dependent switching current is less susceptible to data distortion, such as inter-symbol interference (ISI).

(16) As noted above, the multiple bit processing circuits are configured and aggregated such that a multi-bit codeword having, for example, a 12-bit resolution (thus twelve bit processing circuits provided in parallel to an aggregated output), can be processed during a given bit time to produce a corresponding analog voltage at the aggregated output.

(17) FIG. 4 illustrates a voltage-mode DAC architecture similar to that of FIG. 3, with the addition of current-steering circuitry in the output stage to address common mode-related noise and/or distortion. The current steering circuitry may be implemented on each bit processing circuit and includes respective even and odd current-mode sub-drivers 402 and 404 that correspond to the voltage-mode sub-drivers 302 and 304 of FIG. 3. Each of the current-mode sub-drivers 402 and 404 includes a high current source I.sub.H coupled to the supply voltage VDD, and a low current source I.sub.L, coupled to ground V.sub.SS. Multiple switches 406, 408, 410, and 412 in the form of transistors selectively couple I.sub.H and I.sub.L to the DAC output, depending on the input data logic value. Although slightly more power may be consumed during operation, use of the tunable currents provides significant elimination of common-mode effects.

(18) FIG. 5 illustrates an embodiment of a voltage-mode DAC architecture, generally designated 500, that incorporates an analog interpolated Zero-order-Hold circuit. The architecture includes circuitry that addresses excessive power consumption for out-of-band filtering of the DAC driver output signal. Similar to the architecture shown in FIG. 3, multiple bit processing circuits 502.sub.0-502.sub.n-1 are provided, each tasked with generating an analog output in response to receiving a digital input. Each bit processing circuit includes delay logic 504 having a first flip-flop stage 506 that receives a current bit value D(n+1) in response to a clock signal clock. A second flip-flop stage 508 receives the output (a preceding bit value D(n)) of the first flip-flop 506 in response to a delayed version of the clock signal via delay element 510, and generates an output D(n) in response to the delayed clock. For one embodiment, the clock delay is half a clock cycle.

(19) Further referring to FIG. 5, the preceding bit value D(n) is fed to a first DAC circuit 512 that may be formed similarly to the DAC described with respect to FIG. 3. The first DAC may be configured with an output resistance 2R.sub.OUT. A second DAC circuit 514 formed similarly to the first DAC receives the delayed version of the previous bit D(n). The resulting output alternatingly generates a first analog value based on the value of D(n) during a first half of a bit time T.sub.S, and a second analog value based on the value of D(n) during a second half of the bit time T.sub.S. The resulting interpolated waveform is shown in FIG. 6.

(20) Generally speaking, the architecture described above provides a 2 up-sampler with a mid-point filter by using DAC structures similar to those described herein. As a result, basic data-interpolation and filtering may be achieved with little to no additional driver power consumption. Moreover, the clock can remain at the same rate as the input data. For embodiments that employ voltage-mode drivers as the sub-drivers, the output impedance is constrained to be a maximum of twice the nominal impedance during switching, rather than potentially infinite. Lastly, errors in either the clock duty-cycle or amplitude mismatch between the phase-offset data paths will not lead to distortion, but rather a reshaping of the linear filter.

(21) When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

(22) In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be asserted when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be deasserted to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to output a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be activated when a signal is asserted on the signal line, and deactivated when the signal is deasserted. Additionally, the prefix symbol / attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., <signal name>) is also used to indicate an active low signal. The term coupled is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device programming may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term exemplary is used to express an example, not a preference or requirement.

(23) While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.