Method for electromagnetic energy sensing and a circuit arrangement
10760963 ยท 2020-09-01
Assignee
Inventors
Cpc classification
International classification
Abstract
A circuit arrangement comprises a photo detector (2) for detecting electromagnetic energy and a signal generating means (4, 6, 12, 16) being suitable for generating a sequence of events wherein an event interval of the sequence depends on the detected electromagnetic energy. The signal generating means (4, 6, 12, 16) is coupled downstream of the photo detector (2). A counting means (30, 32, 34, 36) for measuring a time period until a given number of events has been generated is coupled downstream of the signal generating means (4, 6, 12, 16).
Claims
1. A method for electromagnetic energy sensing comprising: detecting electromagnetic energy, wherein detecting electromagnetic energy comprises converting the electromagnetic energy into a current, generating a sequence of events, wherein successive events of the sequence of events are separated in time by an event interval, wherein the event interval depends on the detected electromagnetic energy, and wherein generating the sequence of events comprises: integrating the current by charging a capacitor, and responsive to the integrated current reaching or exceeding a given threshold: generating one event, and discharging the capacitor, measuring a time period until a given number of events has been generated, wherein measuring the time period comprises counting a number of the events and comparing the counted number with the given value stored in a register, wherein the given number of events is greater than one, and providing the time period as an output value.
2. The method according to claim 1, wherein measuring the time period comprises: incrementing a time value in dependence of a clock signal, while incrementing the time value, counting the number of the events and comparing the counted number with the given number, evaluating the time value when the counted number has reached or exceeded the given number, and providing the evaluated time value as an output value.
3. The method according to claim 1, wherein the event is a signal pulse.
4. A circuit arrangement comprising: a photo detector operable to detect electromagnetic energy, wherein detecting electromagnetic energy comprises converting the electromagnetic energy into a current, a signal generating circuit operable to generate a sequence of events, wherein successive events of the sequence of events are separated in time by an event interval, wherein the event interval depends on the detected electromagnetic energy, wherein the signal generating circuit is coupled downstream of the photo detector, and wherein generating the sequence of events comprises: integrating the current by charging a capacitor, and responsive to the integrated current reaching or exceeding a given threshold: generating one event, and discharging the capacitor, and a counting circuit operable to measure a time period until a given number of events has been generated, wherein measuring the time period comprises counting a number of the events and comparing the counted number with the given value stored a register.
5. The circuit arrangement according to claim 4, wherein the photo detector comprises a photodiode.
6. The circuit arrangement according to claim 4, wherein the signal generating circuit comprises: an integrator amplifier, a comparator having a first input coupled to the integrator amplifier and a second input operable to apply a reference voltage, and a signal event generator coupled downstream of an output of the comparator, the signal event generator being operable to generate an event when being triggered by the comparator.
7. The circuit arrangement according to claim 6, further comprising a resetting circuit operable to reset the integrator amplifier, the resetting circuit being coupled to the signal event generator in such a way that the integrator amplifier is reset when one event is generated.
8. The circuit arrangement according to claim 6, wherein the counting circuit comprises: an event counter having an input coupled to the signal event generator, and a further comparator having a first input coupled to an output of the event counter and a second input coupled to the register.
9. The circuit arrangement according to claim 8, wherein the counting circuit comprises an incrementing counter having an enable input coupled to an output of the further comparator, the incrementing counter being operable to count time pulses of a clock signal applied to a clock input and evaluate and provide the amount of counted time pulses when triggered at the enable input.
10. The circuit arrangement according to claim 9, further comprising a clock generator connected to the clock input of the incrementing counter.
11. The circuit arrangement according to claim 9, wherein the event counter, the incrementing counter and the further comparator are embodied as digital electronic circuits.
12. The circuit arrangement according to claim 4, wherein an event is a signal transfer between two logical levels forming a signal pulse.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Non-limiting, exemplary embodiments of the invention will now be described with reference to the accompanying drawings, in which:
(2)
(3)
(4)
REFERENCE NUMERALS
(5) 2 photo detector 4 capacitor 6 operational amplifier 8, 14 voltage source 10 switch 12 differential amplifier 16 flip-flop 18, 24, 30, 36 counter 20, 32 register 22, 34 comparator 25, 37, Q output 26 clock generator 51, 53, 55, 61, 63, 65, 67 step CLK, D INC, EN input FB, REF voltage
DETAILED DESCRIPTION
(6)
(7) The circuit arrangement comprises a photo detector 2 that may be embodied as a photodiode. The photo detector 2 is a sensor of light or other electromagnetic energy which provides a current in dependence of the light intensity or the electromagnetic energy. The photo detector 2 may be considered as a light-to-current converter. The circuit arrangement further comprises an operational amplifier 6 and an integrating capacitor 4; the latter is coupled between an input and an output of the operational amplifier 6. Another input of the operational amplifier 6 is connected to ground GND. The photo detector 2 is connected to the same input as the integrating capacitor 4. The operational amplifier 6 and the integrating capacitor 4 form an integrator amplifier, where the integrating capacitor 4 may be charged by the current of the photo detector 2.
(8) A feedback mechanism comprises a voltage source 8 and a switch 10 coupled in series between ground GND and the input of the operational amplifier 6 to which the integrating capacitor 4 is connected. The feedback mechanism allows discharging the integrating capacitor 4 if the switch 10 is in a conducting state; thereby a given feedback voltage VB provided by a voltage source 8 is applied to the integrating capacitor 4. If the switch 10 is in a non-conducting state, the integrating capacitor 4 may be charged by the current of the photo detector 2.
(9) A comparator 12 is connected downstream of the integrator amplifier 4, 6. The comparator 12, which may be embodied as a differential amplifier, has a first input coupled to the output of the operational amplifier 6 and a second input for applying a reference voltage REF which is provided by a reference voltage source 14. The voltage at the first input depends on the voltage across the integrating capacitor 4. When the voltage reaches or exceeds a given threshold value, which is the reference voltage REF, there is a signal transition at the comparator's output. This may be a signal transition from a low voltage level to a high voltage level.
(10) A flip-flop 16, preferably a D flip-flop, is connected downstream of the comparator 12. The flip-flop 16 serves as a signal generating means and allows clock-controlled direct transfer of data from an input D to an output Q of the flip-flop 16. The output Q provides either a first state LOW, which may indicate a low voltage level, or a second state HIGH, which may indicate a high voltage level. A clock generator 26 applies a clock signal to the flip-flop 16. The clock frequency may be 730 kHz, for example.
(11) Once the signal at the comparator's output has changed, the state at the output Q of the flip-flop 16 also changes. Since the output Q is connected to the switch 10, the latter also switches, thereby discharging the capacitor 4. Then the voltage at the output of the operator amplifier 6 changes as well as the voltage at the output of the comparator 12, which causes again a state transition at the output Q of the flip-flop 16. Thus a pulse at the flip-flop's output Q is generated when a certain amount of light has been detected. During light detection a sequence of pulses is generated; the frequency of the sequence depends on the intensity of the detected light. The higher the intensity, the higher is the frequency. In other words, the lower the intensity, the larger is the interval between the pulses.
(12) The number of pulses within a given time interval is detected by the following digital circuit arrangement comprising a first counter 18, a second counter 24, a further comparator 22 and an integer time register 20. The first counter 18 and the integer time register 20 are connected to inputs of the further comparator 22. The first counter 18 is an incrementing counter that counts up with every cycle of the clock signal applied to a clock input CLK of the first counter 18.
(13) The output of the further comparator 22 is connected to an enable input EN of the second counter 24 serving as an event counter. The output Q of the flip-flop 16 is connected to an increment input INC of the second counter 24. The clock signal is applied to a clock input CLK of the second counter 24. The second counter 24 counts up when triggered at the increment input INC and stops and evaluates the count value when triggered at the enable input EN.
(14) The first counter 18 counts up in dependence of the clock signal during a given time interval; thus it serves as a timer. The further comparator 22 compares whether the first counter 18 has reached a given time value provided by the integer time register 20. If this happens, the further comparator 22 triggers the enable input EN of the second counter 24. While the first counter 18 counts up, the second counter 24 counts the number of pulses generated by the flip-flop 16. When the second counter 24 is triggered at the enable input EN at the end of the given time interval, the number of pulses counted so far, which is provided at the output 25 of the second counter 24, indicates the intensity of the detected light. The higher the light intensity, the higher is the count.
(15)
(16) Pulse generation by means of the flip-flop 16 and its upstream components forming the analog front-end is performed in the same manner as described in connection with
(17) However, the digital circuit is different. The invention changes the digital circuit to count the amount of time needed to produce a fixed number of pulses.
(18) The digital circuit arrangement serving as a counting means comprises a first counter 30 that serves as an event counter, a terminal count register 32, a further comparator 34 and a second counter 36 which is an incrementing counter serving for simple time keeping.
(19) The amount of circuitry added by this additional digital configuration is minimal because there already is a counter for the count number in the conventional approach. A comparator 34 needs to be added. A register 32 also needs to either be added or repurposed for the terminal count.
(20) An increment input INC of the first counter 30 is connected downstream of the output Q of the flip-flop 16. An output of the first counter 30 and the terminal count register 32 are connected to inputs of the further comparator 34. An output of the further comparator 34 is connected to an enable input EN of the second counter 36. The clock signal provided by the clock generator 26, which has already been described in connection with
(21) The second counter 36 counts up in dependence of the clock signal; thereby it serves as a time keeper measuring the time until the enable input is triggered.
(22) Once a triggering event, i.e. a pulse, is applied to the increment input INC of the first counter 30, it counts up; thereby the pulses generated by the flip-flip 16 are counted. The further comparator 34 compares whether the first counter 30 has reached a given number of pulses that is provided by the terminal count register 32. If this happens, the further comparator 34 triggers the enable input EN of the second counter 36. Its current value is provided as an output value at the output 37. The output value indicates the time period until the given number of events has been generated. The higher the intensity, the lower the output value.
(23) The circuit arrangement in
(24) Detecting electromagnetic energy comprises converting the electromagnetic energy into a current. Generating the sequence of events comprises integrating the current by charging the capacitor 4 of the integrator amplifier 4, 6 and generating one event and discharging the capacitor 4 if the integrated current reaches or exceeds a given threshold. When generating a sequence of events by means of the integrator amplifier 4, 6, the comparator 12 and the signal event generator 16, an event interval of the sequence depends on the detected electromagnetic energy.
(25) Measuring the time period comprises the following steps.
(26) A time value is incremented in dependence of the clock signal, as illustrated in step 61, which is performed by the up-counting second counter 36. While incrementing the time value, the events are counted and the count value is compared with the given number, as illustrated in step 63, which is performed by the first counter 30, the register 32 and the further comparator 34. The time value is evaluated when the count value has reached or exceeded the given number, as illustrated in step 65, which is performed by the second counter 36 when triggered by the comparator 34. The evaluated time value is provided as an output value at the second counter's output 37, as illustrated in step 67.
(27) The following calculations show the benefit of the above-mentioned way of electromagnetic energy or light sensing.
(28) Considering the conventional measurement, for an exemplary programmed integration time of 179.3 S the integration counter will count for (2{circumflex over ()}161) or 65536 clock cycles. An average of 648.87 to 655.36 clocks per feedback event will produce a pulse count of 100. An average of less than 648.87 would produce a final pulse count of 101 and an average of greater than 655.36 would produce a final pulse count of 99. The point at which the count reaches 100 could be 64887 and 65536 or in between, given a constant diode current. The difference in average diode current to produce a final count of 100 being reached at 64887 and 65536 clocks is (6553664887)/65536 or 1.0%.
(29) Coming to the inventive measurement, if we know the number of clock cycles at which 100 counts is achieved, we can realize an increase in resolution of 1/649 (6553664887) since the exact time value of the integration counter is taken into account. It is important to note that the increased resolution is not linear. As the average current increases, the resolution gain decreases.
(30) In the case of multiple channels additional logic would have to be added if the light had to be sampled by all sensors over the same period. Alternatively, light sampling for multiple channels could be done sequentially.
(31) The scope of protection is not limited to the examples given herein above. The invention is embodied in each novel characteristic and each combination of characteristics, which particularly includes every combination of any features which are stated in the claims, even if this feature or this combination of features is not explicitly stated in the claims or in the examples.