Method for manufacturing electronic package

Abstract

The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

Claims

1. A method for manufacturing an electronic package, comprising: providing an electronic component and a carrier structure, with a plurality of conductive bumps formed on the electronic component and a solder tip formed on each of the conductive bumps; pre-heating the carrier structure to allow the carrier structure to become warped; and after pre-heating the carrier structure, bonding the electronic component to the carrier structure via the solder tips with the solder tips being brought into contact with the carrier structure and free from going through a reflow process.

2. The method of claim 1, wherein the electronic component is a semiconductor chip.

3. The method of claim 1, wherein the electronic component is a flip chip semiconductor chip.

4. The method of claim 1, further comprising, after the solder tips are brought into contact with the carrier structure, performing a cooling process.

5. The method of claim 1, further comprising, after the solder tips are brought into contact with the carrier structure, heating the electronic component to allow the solder tips to become melted.

6. The method of claim 1, wherein at least one of the conductive bumps and the solder tips is formed by electroplating.

7. The method of claim 1, wherein at least one of the conductive bumps and the solder tips is formed by screen printing.

8. The method of claim 1, wherein the solder tips have a thickness greater than or equal to 15 m.

9. The method of claim 1, wherein the solder tips are cylindrical or cubic.

10. The method of claim 1, wherein the solder tips have planar, arc or irregular surfaces.

11. The method of claim 1, wherein the carrier structure is a package substrate with a core layer and circuit structures.

12. The method of claim 1, wherein the carrier structure is a coreless circuit structure, a lead frame, or a silicon interposer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for manufacturing a flip chip semiconductor package;

(2) FIGS. 2A to 2C are cross-sectional views illustrating a method for manufacturing an electronic package in accordance with the present disclosure; and

(3) FIG. 2B is a cross-sectional view illustrating a subsequent step following FIG. 2A in accordance with another embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(4) The technical content of present disclosure is described by the following specific embodiments. One of ordinary skill in the art can readily understand the advantages and effects of the present disclosure upon reading the disclosure of this specification. The present disclosure may also be practiced or applied with other different implementations. Based on different contexts and applications, the various details in this specification can be modified and changed without departing from the spirit of the present disclosure.

(5) It should be noted that the structures, ratios, sizes shown in the drawings appended to this specification are to be construed in conjunction with the disclosure of this specification in order to facilitate understanding of those skilled in the art. They are not meant, in any ways, to limit the implementations of the present disclosure, and therefore have no substantial technical meaning. Without affecting the effects created and objectives achieved by the present disclosure, any modifications, changes or adjustments to the structures, ratio relationships or sizes, are to be construed as fall within the range covered by the technical contents disclosed herein. Meanwhile, terms, such as above, below, first, second, one, a, an, and the like, are for illustrative purposes only, and are not meant to limit the range implementable by the present disclosure. Any changes or adjustments made to their relative relationships, without modifying the substantial technical contents, are also to be construed as within the range implementable by the present disclosure.

(6) Referring to FIGS. 2A to 2C, cross-sectional views illustrating a method for manufacturing an electronic package 2 in accordance with the present disclosure are shown.

(7) As shown in FIG. 2A, an electronic component 21 and a carrier structure 20 including a plurality of electrical contact pads 200 are provided. A plurality of conductive bumps 22 are formed on the electronic component 21. A solder tip 23 is formed on each of the conductive bumps 22. The carrier structure 20 then undergoes a pre-heating process, such that the carrier structure 20 may appear to be warped, and, thus, its left and right sides are upturned (as indicated by arrows B in FIG. 2A).

(8) In an embodiment, the electronic component 21 can be an active component, a passive component, or a combination thereof. The active component can be, for example, a semiconductor chip. The passive component can be, for example, a resistor, a capacitor or an inductor. In an embodiment, the electronic component 21 is a semiconductor chip having an active face 21a and a non-active face 21b opposite to the active face 21a. A plurality of electrode pads are provided on the active face 21a. The conductive bumps 22, such as copper pillars, are disposed on the electrode pads. The solder tips 23 are not reflowed.

(9) Moreover, the conductive bumps 22 or the solder tips 23 are formed by electroplating or screen printing, for example, and the thickness t of the solder tips 23 is greater than or equal to 15 m.

(10) Furthermore, the solder tip 23 may be, for example, cylindrical, cubic, or some other shapes with a generally planar, arc or irregular surface.

(11) In an embodiment, the carrier structure 22 can be, for example, a package substrate with a core layer and circuit structures, or a coreless circuit structure, which forms circuit layers, such as a fan-out redistribution layer (RDL), on a dielectric material. It can be appreciated that the carrier structure 20 can also be other types of carrier for carrying an electronic component (e.g., a chip), such as a lead frame and a silicon interposer, and the present disclosure is not limited as such.

(12) As shown in FIG. 2B, heat is provided to the electronic component 21 (a pre-heating process) to allow the solder tips 23 to be melted, and the melted solder tips 23 are directly bonded with the electrical contact pads 200 on the carrier structure 20 afterwards, such that the solder tips 23 did not go through a reflow process before coming into contact with the carrier structure 20 (or the electrical contact pads 200).

(13) In an embodiment, the electronic component 21 and the carrier structure 20 can undergo the pre-heating process at different (or the same) locations simultaneously.

(14) As shown in FIG. 2C, a cooling process is performed to allow the carrier structure 20 to gradually flatten.

(15) In another embodiment, the electronic component 21 and the carrier structure 20 are not pre-heated. The solder tips 23 are directly brought into contact with the electrical contact pads 200 (as shown in FIG. 2B) followed by heating of the electronic component 21 (e.g., a heating process) in order to allow the solder tips 23 to become melted, such that the melted solder tips 23 are bonded onto the electrical contact pads 200 (as shown in FIG. 2C).

(16) As described above, the electroplating thickness of the prior-art solder tips is limited in that, when the thickness of the solder tips is less than 15 m, solder cracks may occur in the reflowed bullet-shaped solder balls owing to the inability to sustain the deformation of the carrier structure, whereas when the thickness of the solder tips is greater than or equal to 15 reflowed solder balls are more likely to collapse. On the contrary, the method for manufacturing the electronic package 2 in accordance with the present disclosure allows the solder tips 23 to come into contact with the carrier structure 20 without the reflow process. As a result, sufficient amount of solder tips 23 can be provided on the conductive bumps 22 without having to worry about the risk of solder collapsing at the solder tips 23 and covering the side walls of the conductive bumps 22. Therefore, compared to the prior art, the method for manufacturing the electronic package 2 according to the present disclosure eliminates unbalanced stress in the subsequent processes, thereby preventing solder cracks from forming in the conductive bumps 22 or the solder tips 23.

(17) Moreover, a sufficient amount of solder in the solder tips 23 provides better bonding during thermal cycling (e.g., the pre-heating or heating process) to preclude the problem of cracking during the cooling process due to insufficient amount of solder used in the solder tips 23.

(18) The above embodiments are only used to illustrate the principles of the present disclosure, and should not be construed as to limit the present disclosure in any way. The above embodiments can be modified by those with ordinary skill in the art without departing from the scope of the present disclosure as defined in the following appended claims.