Circuit substrate

Abstract

The present invention discloses a circuit substrate, including a first signal end, a second signal end, a first circular capacitor structure, and a second circular capacitor structure. The first circular capacitor structure is electrically connected to the first signal end. The second circular capacitor structure is electrically connected to the second signal end. The first circular capacitor structure and the second circular capacitor structure are located in different planes of the circuit substrate.

Claims

1. A circuit substrate capable of reducing a quantity of capacitance value variations caused by positive and negative tolerance of processes, comprising: a first signal end; a second signal end; a first circular capacitor structure, electrically connected to the first signal end; and a second circular capacitor structure, overlapped with the first circular capacitor structure and electrically connected to the second signal end, wherein the first circular capacitor structure and the second circular capacitor structure are located in different planes of the circuit substrate.

2. The circuit substrate according to claim 1, wherein the areas of the first circular capacitor structure and the second circular capacitor structure are the same.

3. The circuit substrate according to claim 1, wherein the areas of the first circular capacitor structure and the second circular capacitor structure are not the same.

4. The circuit substrate according to claim 1, further comprising: a third signal end; a third circular capacitor structure, electrically connected to the third signal end; and a fourth circular capacitor structure, electrically connected to the second signal end, wherein the third circular capacitor structure and the fourth circular capacitor structure are located in different planes of the circuit substrate.

5. The circuit substrate according to claim 4, wherein the areas of the third circular capacitor structure and the fourth circular capacitor structure are the same.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A to FIG. 1C are curved charts of capacitance value variations of a conventional square capacitor;

(2) FIG. 2A is a three-dimensional diagram of an embodiment of a circuit substrate applicable to an electrical connector according to the present invention;

(3) FIG. 2B is an exploded view of the embodiment in FIG. 2A;

(4) FIG. 3 is a three-dimensional diagram of an embodiment of a circuit substrate according to the present invention;

(5) FIG. 4A is a schematic diagram of an embodiment of a circuit substrate according to the present invention;

(6) FIG. 4B to FIG. 4D are simulation diagrams of the embodiment in FIG. 4A;

(7) FIG. 5A is a simulation diagram of a capacitance value of a conventional square capacitor and that of a circuit substrate of the present invention;

(8) FIG. 5B is a simulation diagram of a conventional square capacitor to which a positive/negative tolerance is added; and

(9) FIG. 5C is a simulation diagram of circuit substrate of the present invention to which a positive/negative tolerance is added.

DETAILED DESCRIPTION

(10) The following describes a plurality of implementations of the present invention with reference to the accompany drawings and words. For clarity, many practical details are described together in the following description. However, it should be understood that, the practical details should not be applied to limit the present invention. In addition, for simplicity, some known structures and elements are drawn in the accompanying drawings in simple and exemplary manners.

(11) Referring to FIG. 2A and FIG. 2B, a circuit substrate 11 in this embodiment is applicable to an electrical connector 1, for example, an electrical connector and a communication connector. This is not specially limited. The electrical connector 1 includes the circuit substrate 11, a mating portion 12, and a circuit board 13. Both the circuit substrate 11 and the circuit board 13 are electrically connected to metal contacts 121 to 128 on the mating portion 12.

(12) Referring to FIG. 3 and FIG. 4A to FIG. 4D. That the circuit substrate 11 in this embodiment is a flexible circuit board is used as an example, but this is not limited thereto. As shown in FIG. 2 to FIG. 3, the circuit substrate 11 preferably includes signal ends 111, 113, 114, 115, 116 and 118, a first circular capacitor structure 11a, and a second circular capacitor structure 11b. The signal ends 111, 113, 114, 115, 116 and 118 are respectively electrically connected to the metal contacts 121 to 128 on the mating portion 12. For example, the first signal end 111 is connected to the metal contact 121, the second signal end 113 is connected to the metal contact 123, and so on.

(13) The first circular capacitor structure 11a is located at an upper layer of the circuit substrate 11, and is electrically connected to the first signal end 111 by using a signal line S1. The second circular capacitor structure 11b is preferably located at a layer different from the layer at which the first circular capacitor structure 11a is located, for example, the second circular capacitor structure 11b is located at a bottom layer, and is electrically connected to the second signal end 113 by using a signal line S3. Based on this design, an electric field may be stored by using the two circular capacitor structures: the upper circular capacitor structure 11a and the lower circular capacitor structure 11b, to further form capacitive coupling.

(14) In this embodiment, that the areas of the first circular capacitor structure 11a and the second circular capacitor structure 11b are the same is used as an example, but this is not limited thereto. However, for ease of recognition, the two circular capacitor structures in the figure are still presented in different sizes.

(15) Referring to FIG. 4B to FIG. 4D, in this embodiment, the radii of both the first circular capacitor structure 11a and the second circular capacitor structure 11b are 20.684 mil (which is learned through conversion of the area of the square capacitor in FIG. 1A), and a vertical distance between the two capacitor boards is also 0.02 mm. When simulation is performed based on this condition, the capacitance values of the circuit substrate are approximately 2.895E.sup.14 F, 2.893E.sup.14 F, 2.892E.sup.14 F, and 2.891E.sup.14 F at different frequencies.

(16) As shown in FIG. 4C and FIG. 4D, FIG. 4C and FIG. 4D are simulation data respectively obtained by adding a negative tolerance and a positive tolerance on the circular capacitor in FIG. 4B (where radii are respectively 20.184 mil and 21.184 mil).

(17) In an embodiment, the circuit substrate may alternatively include a plurality of circular capacitor structures, for example, a third circular capacitor structure 12a and a fourth circular capacitor structure 12b. A third signal end 115 is electrically connected to the third circular capacitor structure 12a by using a signal line S5. The fourth circular capacitor structure 12b is electrically connected to the second signal end 113 by sharing the signal line S3, and the fourth circular capacitor structure 12b is capacitively coupled to the third circular capacitor structure 12a. In this embodiment, that the areas of the two circular capacitor structures are the same is also used as an example.

(18) Based on the foregoing embodiments and referring to FIG. 5A to FIG. 5C, FIG. 5A and FIG. 5B are statistical graphics of simulation capacitance values of a conventional normal square capacitance value and that when a process error occurs. As shown in the figure, by using a conventional square capacitor board as an example (where the areas are the same and a positive tolerance and a negative tolerance are respectively added), capacitance value errors obtained at different frequencies approximately fall between 4.84% and 8.16%.

(19) FIG. 5A also includes a statistical graphic of simulation capacitance values of a normal circular capacitance value and that when a process error occurs according to the present invention. As shown in FIG. 5A and FIG. 5C, by using a circular capacitor board in the present invention as an example (where the areas are the same and a positive tolerance and a negative tolerance are respectively added), capacitance value errors obtained at different frequencies approximately fall between 2.00% and 6.40%.

(20) In conclusion, it can be clearly learned through comparison that the circular capacitor structure of the present invention can effectively reduce a quantity of capacitance value variations caused by positive and negative tolerance of the process. That is, the circular plate capacitor structure has a relatively good efficacy of anti-process error.

(21) The areas of the circuit substrate and the upper and lower boards of the circular capacitor structure of the present invention may be the same or may be different. This is not specifically limited, as described herein.

(22) The circuit substrate of the present invention may also be a hard circuit board, a double-layer board, and a multi-layer board. This is not specifically limited, as described herein.

(23) Compared with the conventional art, the circuit substrate of the present invention reduces, by using a structure of an upper circular capacitor board and a lower circular capacitor board, a capacitance value variation caused by a process error.

LIST OF REFERENCE NUMERALS

(24) TABLE-US-00001 1 Electrical connector 11 Circuit substrate 12 Mating portion 13 Circuit board 111 First signal end 113 Second signal end 114 Signal end 115 Third signal end 116 Signal end 118 Signal end 121 Metal contact 122 Metal contact 123 Metal contact 124 Metal contact 125 Metal contact 126 Metal contact 127 Metal contact 128 Metal contact 11a First circular capacitor 11b Second circular capacitor structure structure 12a Third circular capacitor 12b Fourth circular capacitor structure structure S1 Signal line S3 Signal line S5 Signal line