Method for reducing common mode current in power electronic equipment

Abstract

The present invention relates to a method for reducing common mode current in power electronic equipment comprising two or more active front end (AFE) components (1) coupled in parallel between an AC supply grid (2) and a DC-link (3). A duty cycle of pulse width modulation (PWM) for the AFE components (1) is determined, and an error signal is derived based on the determined duty cycle of PWM and on a common mode current of the AFE components (1). A correction voltage is derived, based on the error signal, and a DC voltage control signal is derived based on the derived correction voltage and a measured DC voltage of the DC-link (3) and/or a DC voltage reference. The power electronic equipment is controlled in accordance with the derived DC voltage control signal. The present invention also relates to a method for starting active front end (AFE) components (1) of power electronic equipment comprising two or more AFE components (1) coupled in parallel between an AC supply grid (2) and a DC-link (3).

Claims

1. A method for reducing common mode current in power electronic equipment comprising two or more active front end (AFE) components coupled in parallel between an AC supply grid and a DC-link, the method comprising the steps of: determining a duty cycle of pulse width modulation (PWM) for the AFE components, deriving an error signal based on the determined duty cycle of PWM and on a common mode current of the AFE components, deriving a correction voltage, based on the error signal, deriving a DC voltage control signal based on the derived correction voltage and a measured DC voltage of the DC-link and/or a DC voltage reference, and controlling the power electronic equipment in accordance with the derived DC voltage control signal.

2. The method according to claim 1, wherein the step of determining the duty cycle of PWM comprises deriving the duty cycle of PWM based on the common mode current of the AFE components.

3. The method according to claim 2, further comprising a step of measuring the common mode current of the AFE components.

4. The method according to claim 3, wherein the step of deriving the duty cycle of PWM based on the common mode current comprises filtering the common mode current by means of one or more filters.

5. The method according to claim 4, wherein the step of deriving the DC voltage control signal comprises adding the derived correction voltage and the measured DC voltage of the DC-link and/or the DC voltage reference.

6. The method according to claim 3, wherein the step of deriving the DC voltage control signal comprises adding the derived correction voltage and the measured DC voltage of the DC-link and/or the DC voltage reference.

7. The method according to claim 2, wherein the step of deriving the DC voltage control signal comprises adding the derived correction voltage and the measured DC voltage of the DC-link and/or the DC voltage reference.

8. The method according to claim 1, wherein the step of deriving the DC voltage control signal comprises adding the derived correction voltage and the measured DC voltage of the DC-link and/or the DC voltage reference.

9. The method according to claim 1, wherein the step of deriving the correction voltage comprises feeding the error signal to an integral controller.

10. The method according to claim 1, further comprising the steps of: identifying an AFE component being in stop state, determining a duty cycle of PWM of the AFE components which are already running, deriving an adjustment to a control period for the AFE component being in stop state, based on the determined duty cycle of PWM, and starting the AFE component being in stop state, and operating said AFE component in accordance with the derived adjustment to the control period.

11. The method according to claim 10, wherein the step of deriving the adjustment to the control period comprises deriving an error signal based on the determined duty cycle of PWM.

12. The method according to claim 11, wherein the step of deriving the adjustment to the control period further comprises feeding the error signal to a proportional (P) controller or to a proportional integral (PI) controller.

13. The method according to claim 11, wherein the step of determining the duty cycle of PWM of the AFE components, which are already running comprises determining a duration of an on-time of the AFE components, which are already running.

14. The method according to claim 1, wherein the step of deriving the error signal is based on the common mode current of the AFE components at a peak of a modulation carrier wave.

15. A non-volatile computer readable medium encoded with a computer program for reducing common mode current in power electronic equipment comprising two or more active front end (AFE) components coupled in parallel between an AC supply grid and a DC-link, the computer program comprising computer executable instructions for controlling a programmable processor to: determining a duty cycle of pulse width modulation (PWM) for the AFE components, deriving an error signal based on the determined duty cycle of PWM and on a common mode current of the AFE components, deriving a correction voltage, based on the error signal, deriving a DC voltage control signal based on the derived correction voltage and a measured DC voltage of the DC-link and/or a DC voltage reference, and controlling the power electronic equipment in accordance with the derived DC voltage control signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will now be described in further detail with reference to the accompanying drawings in which

(2) FIG. 1 is a diagram showing paralleled AFEs being controlled in accordance with an embodiment of the invention,

(3) FIG. 2 are plots of common mode currents originating from PWM carrier misalignment and DC voltage error in paralleled AFEs being controlled in accordance with a prior art method,

(4) FIG. 3 is a block diagram illustrating a prior art control method for reducing common mode current originating from carrier misalignment,

(5) FIG. 4 is a block diagram illustrating a method according to an embodiment of the invention,

(6) FIG. 5 are plots of common mode currents originating from PWM carrier misalignment and DC voltage error in paralleled AFEs being controlled in accordance with a method according to an embodiment of the invention,

(7) FIG. 6 is a block diagram illustrating a method according to an alternative embodiment of the invention, and

(8) FIG. 7 are plots of common mode currents in paralleled AFEs being controlled in accordance with a method according to an embodiment of the invention, during start-up.

DETAILED DESCRIPTION

(9) The specific examples provided in the description below should not be construed as limiting the scope and/or the applicability of the accompanied claims. Lists and groups of examples provided in the description below are not exhaustive unless otherwise explicitly stated.

(10) FIG. 1 is a diagram showing a number of AFEs 1, four of which are shown, coupled in parallel between an AC supply grid 2 and a DC-link 3. The AFEs 1 are in the form of converters. Each AFE is coupled to the AC supply grid 2 via a filter 4 comprising a first inductance 5 and a capacitance 6, and a second inductance 7. Furthermore, each AFE 1 can be connected to and disconnected from the AC supply grid 2 by means of a switch 8. This will be described in further detail below.

(11) Due to rapid changes in voltages and currents within a switching converter, the AFEs 1 are a source of noise with other components as well as with its own operation. One type of noise is the common mode current, which is measured along the normal power connections, through inductors, cables, bus bars etc. A way of reducing this type of noise on the power lines is to design a filter that can take this into account, such as filter 4 in FIG. 1. These stray capacitances exist between various system components and ground. Due to safety reasons the majority of power electronic equipment has a grounded cabinet. Thus the noise appearing on the ground line will contribute most to the total common mode current. Moreover, PWM carrier misalignment and DC voltage measurement error also effects the common mode current.

(12) The PWM carrier misalignment arises due to the lack of centralized control, which changes the position of the PWM carrier of the respective AFEs 1. The PWM carriers start with random phase with respect to each other. The phase shift denotes the position of a point on the PWM carrier in time. A misalignment in the PWM carrier would result in the generated common mode voltage generated to be of different phase angle. This will cause a common mode current to flow. Thus the total generated common mode current can vary due to this.

(13) The DC voltage measurement error is an error between a measured voltage between two AFE 1 components. For the DC voltage measurement error, it can be assumed that the error is specific to particular production unit due to component tolerances.

(14) FIG. 2 are plots of common mode currents originating from PWM carrier misalignment and DC voltage error in paralleled AFEs being controlled in accordance with a prior art method. The AFEs could, e.g., be the AFEs 1 illustrated in FIG. 1. Two different modulation schemes are illustrated, i.e. space vector PWM (SVPWM) in the four left plots 9, 11, 13, 15 and discontinuous PWM (DPWM1) in the four right plots 10, 12, 14, 16. All the plots of FIG. 2 show common mode current as a function of time under one period of the fundamental frequency.

(15) The plots 9 and 10 show common mode current originating from PWM carrier misalignment for a PWM carrier misalignment of 90.

(16) The plots 11 and 12 show common mode current originating from PWM carrier misalignment for a PWM carrier misalignment of 180.

(17) It can be seen from the plots 9, 10, 11 and 12 that PWM carrier misalignment results in a common mode current with high frequency. It can further be seen from the plots 9, 10, 11 and 12 the frequency and the amplitude of the common mode current at a PWM carrier misalignment of 180 are higher than the frequency and the amplitude of the common mode current at a PWM carrier misalignment of 90.

(18) The plots 13 and 14 show common mode current originating from a DC voltage error of 1%. It can be seen that DC voltage error results in a common mode current with low frequency and with a substantially triangular characteristic.

(19) The plots 15 and 16 show the total common mode current originating from PWM carrier misalignment of 90 and DC voltage error of 1%. It can be seen that the total common mode current comprises a high frequent part originating from the PWM carrier misalignment and a low frequent part originating from the DC voltage error.

(20) The plots of FIG. 2 all illustrate a prior art situation where it has not been attempted to reduce the common mode currents originating from either PWM carrier misalignment or DC voltage error.

(21) FIG. 3 is a block diagram illustrating a prior art control method for reducing common mode current originating from PWM carrier misalignment. The method is used to synchronise multiple PWM carriers using a common mode current, i.sub.cm,pk, computed from three-phase current sampled at the peak of the PWM carrier.

(22) A TopFlag value is supplied to a point of summation 17. The TopFlag value is a variable which is assumed to be one (true) when the PWM carrier is at the so called top update and zero (false) when at bottom update. At the point of summation 17 0.5 is subtracted from the TopFlag value in order to obtain an alternating sign behaviour. The resulting sign alternating TopFlag value is supplied to a point of multiplication 18.

(23) The peak common mode current, i.sub.cm,pk, is also supplied to the point of multiplication 18. At the point of multiplication 18 the high frequent common mode current, i.sub.cm,pk, caused by PWM carrier misalignment is demodulated by multiplying the common mode current, i.sub.cm,pk, with sign alternating TopFlag value.

(24) The demodulated common mode current is supplied to a finite impulse response (FIR2) filter 19, where the remaining high frequency content is filtered out, and the signal is then inverted through a gain 20 of 1.

(25) Next, the signal is supplied to a proportional (P) controller 21, which is used to adjust the carrier through a variable, T.sub.sw/2,add. The variable, T.sub.sw/2,add, denotes the time that has to be added to a control period, T.sub.sw/2, prior to being supplied to a modulator (not shown). The control period, T.sub.sw/2, defines the PWM half cycle time.

(26) It should be noted that instead of the P controller, a proportional-integral (PI) controller could be used.

(27) As mentioned, this control method only deals with the PWM carrier misalignment, and thus can only solve this issue. Accordingly, applying this method would reduce the common mode currents illustrated in plots 9, 10, 11 and 12 of FIG. 2, but would not affect the common mode currents illustrated in plots 13 and 14 of FIG. 2. Thus, even when applying this method, common mode currents are not fully eliminated, since the common mode current originating from DC voltage error is still present. As described above, this results in reduced efficiency of the AFEs.

(28) FIG. 4 is a block diagram illustrating a method according to an embodiment of the invention. The method is used to reduce the DC voltage error measurement between paralleled AFEs using a peak common mode current, i.sub.cm,pk, computed from three-phase current sampled at the PWM carrier.

(29) A duty cycle, D.sub.uvw, value is supplied to a mathematical block 22. The duty cycle, D.sub.uvw, is the common mode of the duty cycles, which is the output of the modulator ranging between 0 and 1.

(30) A zero sequence of the duty cycle of PWM, D.sub.cm, is supplied to a point of summation 23. The zero sequence is calculated in the following: Dcm=1/3*Du+1/3*Dv+1/3*Dw. At the point of summation 23, 0.5 is subtracted from the duty cycle, D.sub.cm, value in order to obtain an alternating sign behaviour. The resulting sign alternating duty cycle, D.sub.uvw, value is supplied to a point of multiplication 24.

(31) The peak common mode current, i.sub.cm,pk, is also supplied to the point of multiplication 24. At the point of multiplication 24 the common mode current, i.sub.cm,pk, is demodulated by multiplying the common mode current, i.sub.cm,pk, with sign alternating duty cycle, D.sub.cm, value.

(32) The demodulated common mode current is supplied to a low pass filter 25, where the remaining high frequency content is filtered out, and the signal is then inverted through a gain 26 of 1.

(33) Next, the signal is supplied to an integral (I) controller 27, which is used to adjust the DC voltage, u.sub.dc,avg, through a DC voltage, u.sub.dc,corr. The DC voltage, udc,corr, is supplied to a point of summation 28.

(34) A DC voltage, u.sub.dc,ADC, is also supplied to the point of summation 28. The DC voltage, u.sub.dc,ADC, is the measured DC voltage voltage of the AFE 1 component.

(35) A DC voltage, u.sub.dc,avg, is supplied to a DC voltage controller (not shown). The DC voltage, u.sub.dc,avg, is the sum of the DC voltages, u.sub.dc,corr and u.sub.dc,ADC, and denotes the DC voltage value for the paralleled AFEs.

(36) For common mode inductances that are pure inductive (no resistive part), the common mode current may comprise a DC component. In this case, it is necessary to augment the integral controller 27 used in the DC voltage adjustment.

(37) The peak common mode current is supplied to a finite impulse response (FIR2) filter 29, where the remaining high frequency content is filtered out. Thereafter, the signal is supplied to a low pass filter (30), and the signal is further filtered.

(38) Next, the signal is then inverted through a gain 31 of 1, before it is supplied to a P controller 32.

(39) The output of the P controller 32 is a duty cycle value, D.sub.cm,add, which is supplied to a modulator (not shown). The duty cycle value, D.sub.cm,add, is used to adjust the modulated common mode voltage in order to drive any DC current to zero.

(40) Since the DC voltage, u.sub.dc,avg, which is supplied to the DC voltage controller (not shown) is a corrected DC voltage signal, it is ensured that all AFE units will converge towards the same steady-state DC voltage, u.sub.dc,avg, value. Thereby the common mode current originating from the DC voltage error, illustrated in plots 13 and 14 of FIG. 2, is reduced.

(41) For pure inductive common mode inductances, the common mode current may comprise a DC component. This issue is solved by supplying duty cycle value, D.sub.cm,add, to the modulator (not shown).

(42) FIG. 5 are plots of common mode currents originating from PWM carrier misalignment and DC voltage error in paralleled AFEs being controlled in accordance with a method according to an embodiment of the invention, in which the control method illustrated by the block diagram of FIG. 3 as well as the control method illustrated by the block diagram of FIG. 4 are applied. The AFEs could, e.g., be the AFEs 1 illustrated in FIG. 1. Two different modulation schemes are illustrated, i.e. space vector PWM (SVPWM) in the three left plots and discontinuous PWM (DPWM1) in the three right plots. All the plots of FIG. 5 show common mode current as a function of time under one period of e.g. 1.6 seconds, where the paralleling control is enabled at time 0.5 s.

(43) The plots 33 and 34 show common mode current originating from PWM carrier misalignment for a PWM carrier misalignment of 180. The plots 35 and 36 show common mode current originating from a DC voltage error of 1%. Finally, the plots 37 and 38 show the total common mode current originating from PWM carrier misalignment of 90 and DC voltage error of 1%.

(44) When comparing the plots of FIG. 5 to the plots of FIG. 2, it is clear that applying the control method illustrated by the block diagram of FIG. 3 as well as the control method illustrated by the block diagram of FIG. 4 results in a significant reduction of the common mode current. It is noted that the common mode current originating from PWM carrier misalignment, and shown in plots 33 and 34, is reduced by means of the control method illustrated by the block diagram of FIG. 3, and the common mode current originating from DC voltage error, and shown in plots 35 and 36, is reduced by means of the control method illustrated by the block diagram of FIG. 4.

(45) FIG. 6 is a block diagram illustrating a method according to an embodiment of the invention. The method is used to synchronise the PWM carrier of an AFE during start-up to one that is already running by monitoring the voltage seen at the inverter terminals. The AFE being started could, e.g., be started by closing a switch, illustrated by reference numeral 8 in FIG. 1.

(46) A variable, T.sub.uvw, value is supplied to a point of division 39. The time variable, T.sub.uvw, is the voltage state feedback averaged over a control period.

(47) A variable, T.sub.sw/2, value is also supplied to a point of division 39. The variable, T.sub.sw/2, is the control period length.

(48) The output of the point of division 39 is a duty cycle, D.sub.uvw, value. The duty cycle, D.sub.uvw, value is supplied to a mathematical block 40. The duty cycle, D.sub.uvw, is the common mode of the duty cycles.

(49) A TopFlag value is supplied to a point of summation 41. The TopFlag value is a variable which is assumed to be one (true) when the PWM carrier is at the so called top update and zero (false) when at bottom update. At the point of summation 41 0.5 is subtracted from the TopFlag value in order to obtain an alternating sign behaviour. The resulting sign alternating TopFlag value is supplied to a point of multiplication 42.

(50) The output of the mathematical block is a common mode duty cycle, D.sub.cm, which is also supplied to the point of multiplication 42.

(51) The output of the point of multiplication is a demodulated signal, which is a function of PWM carrier misalignment.

(52) The demodulated signal is supplied to a finite impulse response (FIR2) filter 43, where the remaining high frequency content is filtered out, and the signal is then inverted through a gain 44 of 1.

(53) Next, the signal is supplied to a P controller 45, which is used to adjust the carrier through a variable, T.sub.sw/2,add. The variable, T.sub.sw/2,add, denotes the time that has to be added to a control period, T.sub.aw/2, prior being supplied to a modulator (not shown). The control period, T.sub.sw/2, defines the PWM half cycle time.

(54) Since the variable, T.sub.sw/2,add, which is supplied to the modulator (not shown) is used to adjust the control period, T.sub.sw/2, it is ensured that the PWM carrier of an AFE unit during start-up can be synchronised with an AFE that is already running.

(55) FIG. 7 are plots of common mode currents originating from PWM carrier synchronisation during start-up in paralleled AFEs being controlled in accordance with a method according to an embodiment of the invention, in which the control method illustrated by the block diagram of FIG. 3 as well as the control method illustrated by the block diagram of FIG. 4, and the control method illustrated by the block diagram of FIG. 6 are applied. The AFEs could, e.g., be the AFEs 1 illustrated in FIG. 1. Two different modulation schemes are illustrated, i.e. space vector PWM (SVPWM) in the two left plots and discontinuous PWM (DPWM1) in the two right plots. All the plots of FIG. 7 show common mode current as a function of time under one period of the fundamental frequency.

(56) The plots 46 and 47 show common mode current originating from PWM carrier synchronisation for a PWM carrier misalignment of 180, when the control method illustrated by the block diagram of FIG. 6 is not applied. The plots 48 and 49 show common mode current originating from PWM carrier synchronisation for a PWM carrier misalignment of 180, when the control method illustrated by the block diagram of FIG. 6 is applied.

(57) In the plots of FIG. 7, a second AFE is started at time 0.5 s. The plots 46 and 47 of FIG. 7 show that the common mode current fluctuates rapidly and with a high amplitude immediately after starting the second AFE at time 0.5 s, when the carrier synchronisation is disabled. On the other hand, the plots 48 and 49 of FIG. 7 show that the common mode current is substantially reduced immediately after starting the second AFE at time 0.5 s, when the carrier synchronisation is enabled.

(58) When comparing the plots of FIG. 7, it is clear that applying the control method illustrated by the block diagram in FIG. 6 results in a reduction of the common mode current when starting a second AFE.

(59) Following computer programs according to an exemplifying and non-limiting embodiment comprises computer executable instructions for controlling a programmable processor to carry out actions related to a method according to any of the above-described exemplifying and non-limiting embodiments.

(60) A computer program for reducing common mode current in power electronic equipment comprising two or more active front end (AFE) components (1) coupled in parallel between an AC supply grid (2) and a DC-link (3), the computer program comprising computer executable instructions for controlling a programmable processor to: determining a duty cycle of pulse width modulation (PWM) for the AFE components (1), deriving an error signal based on the determined duty cycle of PWM and on a common mode current of the AFE components (1), deriving a correction voltage, based on the error signal, deriving a DC voltage control signal based on the derived correction voltage and a measured DC voltage of the DC-link (3) and/or a DC voltage reference, and controlling the power electronic equipment in accordance with the derived DC voltage control signal.

(61) A computer program for starting active front end (AFE) components (1) of power electronic equipment comprising two or more AFE components (1) coupled in parallel between an AC supply grid (2) and a DC-link (3), the computer program comprising computer executable instructions for controlling a programmable processor to: starting a first AFE component (1), determining a duty cycle of pulse width modulation (PWM) of the first AFE component (1), deriving an adjustment to a control period for an AFE component (1) being in stop state, based on the determined duty cycle of PWM, and starting the AFE component (1) being in stop state, and operating said AFE component (1) in accordance with the derived adjustment to the control period.

(62) The above-mentioned computer programs can be e.g. subroutines and/or functions implemented with a programming language suitable for the programmable processor under consideration.

(63) A computer program product according to an exemplifying and non-limiting embodiment comprises a computer readable medium, e.g. a compact disc CD, encoded with a computer program according to an exemplifying embodiment.

(64) The non-limiting, specific examples provided in the description given above should not be construed as limiting the scope and/or the applicability of the appended claims. Furthermore, any list or group of examples presented in this document is not exhaustive unless otherwise explicitly stated.