Frequency-multiplying direct digital synthesizer

Abstract

A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (MB), and the n-bit accumulator accumulates by a step size of the digital product (MB), at a rate of a low-speed reference clock of frequency f.sub.CLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2.sup.n)2 radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate f.sub.CLK, to produce a full-speed serialized digital output having 2.sup.n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency f.sub.OUT=(M/2.sup.n)f.sub.CLK.

Claims

1. A direct digital synthesizer (DDS), comprising: a digital multiplier configured to multiply a digital tuning word of value M by a digital multiplier of value B and produce a digital product (MB); an n-bit accumulator configured to accumulate by a step size of the digital product (MB), at a rate of a reference clock of frequency f.sub.CLK/B; and a post-accumulator digital processing section including a plurality of branches configured to synthesize a plurality of digital waveforms from a sequence of n-bit accumulator output numbers produced by the n-bit accumulator.

2. The DDS of claim 1, wherein the plurality of branches includes B branches, and the post-accumulator digital processing section synthesizes B digital waveforms.

3. The DDS of claim 2, wherein the post-accumulator digital processing section is configured to rotate each synthesized digital waveform with respect to an adjacent digital waveform by (M/2.sup.n)2 radians.

4. The DDS of claim 1, further comprising: a serializer configured to serialize digital samples of the plurality of digital waveforms and produce an output digital waveform; and a digital-to-analog converter (DAC) configured to convert the output digital waveform to a final output analog waveform.

5. The DDS of claim 4, wherein the serializer is configured to serialize the digital samples of the plurality of digital waveforms at a rate f.sub.CLK, the output digital waveform produced by the serializer has 2.sup.n/M samples per cycle, and the final output analog waveform has a frequency f.sub.OUT=(M/2.sup.n)f.sub.CLK.

6. The DDS of claim 4, wherein the serializer and DAC together comprise a single interleaved radio frequency DAC (RF-DAC).

7. The DDS of claim 1, further comprising: a plurality of digital-to-analog converters (DACs) configured to convert the plurality of digital waveforms to a plurality of analog waveforms; and a serializer that samples the plurality of analog waveforms to produce a final output analog waveform.

8. The DDS of claim 7, wherein the serializer samples the plurality of analog waveforms at a rate f.sub.CLK, and the final output analog waveform has a frequency f.sub.OUT=(M/2.sup.n)f.sub.CLK.

9. The DDS of claim 1, wherein the plurality of branches of the post-accumulator digital processing section comprise: a zero-offset digital adder in a first branch configured to add, on each cycle of the reference clock, each n-bit number from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator to an n-bit digital word of value zero; and one or more step-offset digital adders, each of the one or more step-offset digital adders configured to add, on each cycle of the reference clock, each n-bit number from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator to an n-bit digital word that is an integer multiple of the tuning word.

10. The DDS of claim 9, wherein: the plurality of the of the post-accumulator digital processing section branches includes B branches that synthesize B waveforms; the one or more step-offset digital adders includes (B1) branches; a first digital sum produced by a first step-offset adder in a first one of the (B1) branches is a first digital number representing a first phase; and a second digital sum produced by a second step-offset adder in a second one of the (B1) branches adjacent the first one of the (B1) branches is a second digital number representing a second phase that is offset from the first phase by (M/2.sup.n)2 radians.

11. The DDS of claim 10, wherein the B branches of the post-accumulator digital processing section comprises a plurality of phase-to-amplitude (-to-p) converters configured to convert a plurality of sequences of digital sums produced by the zero-offset and step-offset digital adders to the B digital waveforms.

12. The DDS of claim 6, wherein the B branches of the post-accumulator digital processing section further comprise B digital-to-analog converters (DACs) configured to convert the B digital waveforms to B analog waveforms.

13. The DDS of claim 12, further comprising a serializer that samples and serializes the B analog waveforms to produce a final output analog waveform.

14. The DDS of claim 13, wherein the serializer samples the B analog waveforms at a rate f.sub.CLK, and the final output analog waveform has a frequency f.sub.OUT=(M/2.sup.n)f.sub.CLK.

15. The DDS of claim 1, wherein the n-bit accumulator comprises an n-bit pipelined accumulator.

16. A method of synthesizing a periodic waveform, comprising: multiplying a digital tuning word of value M by a digital multiplier of value B to produce a digital product MB; accumulating an n-bit digital number by a step size of the digital product (MB), at a rate of a slow-speed reference clock of frequency f.sub.CLK/B, to produce a sequence of n-bit accumulator output numbers; generating a first digital waveform from the sequence of n-bit accumulator output numbers; adding the digital tuning word M to each n-bit number in the sequence of n-bit accumulator output numbers to produce a modified sequence of n-bit accumulator output numbers; and while the first digital waveform is being generated, generating a second digital waveform from the modified sequence of n-bit accumulator output numbers, the second digital waveform leading the first digital waveform by (M/2.sup.n)2 radians.

17. The method of claim 16, further comprising: serializing samples of the first and second digital waveforms to produce a full-speed serialized digital waveform; and converting the full-speed serialized digital waveform to a final output analog waveform.

18. The method of claim 17, wherein the samples of the first and second digital waveforms are serialized at a rate of a full-speed reference clock of frequency f.sub.CLK, the full-speed serialized digital waveform has 2.sup.n/M samples per cycle, and the final output analog waveform has a frequency f.sub.OUT=(M/2.sup.n)f.sub.CLK.

19. The method of claim 16, further comprising: converting the first digital waveform to a first analog waveform; converting the second digital waveform to a second analog waveform; and sampling and serializing the first and second analog waveforms, to produce a final output analog waveform.

20. The method of claim 19, wherein the first and second analog waveforms are sampled and serialized at a rate of a full-speed reference clock f.sub.CLK, and the final output analog waveform has a frequency f.sub.OUT=(M/2.sup.n)f.sub.CLK.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a drawing depicting the principal elements of a conventional direct digital synthesizer (DDS);

(2) FIG. 2 is a drawing of a phase wheel, illustrating how the accumulator in the conventional DDS depicted in FIG. 1 operates;

(3) FIG. 3 is a drawing depicting a frequency-doubling DDS, according to one embodiment of the present invention;

(4) FIG. 4 is a drawing of a phase wheel, illustrating the operation of the accumulator and a portion of the post-accumulator digital processing section of the frequency-doubling DDS depicted in FIG. 3;

(5) FIG. 5 includes timing diagrams of the outputs of the phase-to-amplitude (-to-p) converters and digital-to-analog converters (DACs) in the post-accumulator digital processing section of the frequency doubling DDS depicted in FIG. 3, and a timing diagram of the full-speed serialized DAC output produced at the output of the frequency-doubling DDS;

(6) FIG. 6 is a drawing depicting a frequency-multiplying DDS, according to another embodiment of the present invention;

(7) FIG. 7 is a drawing of a phase wheel, illustrating the operation of the accumulator and the post-accumulator digital processing section of the frequency-multiplying DDS depicted in FIG. 6;

(8) FIG. 8 includes timing diagrams of the outputs of the -to-p converters of the post-accumulator digital processing section of the frequency-multiplying DDS depicted in FIG. 6, a timing diagram of the final DDS's output analog waveform, and intermediate DAC output timing diagrams illustrating how, effectively, the low-speed samples produced by the post-accumulator digital processing section are serialized by the DDS's interleaved radio frequency DAC (RF-DAC);

(9) FIG. 9 is a drawing illustrating one way that the accumulators in the DDSs depicted in FIGS. 3 and 6 can be implemented; and

(10) FIG. 10 is a drawing illustrating another way that the accumulators in the DDSs depicted in FIGS. 3 and 6 can be implemented.

DETAILED DESCRIPTION

(11) Referring to FIG. 3, there is shown a direct digital synthesizer (DDS) 300, according to one embodiment of the present invention. The DDS 300 comprises a digital multiplier 302; a phase accumulator 304 (or accumulator for short); a post-accumulator digital processing section 306; and a serializer 308. The digital multiplier 302 multiplies a digital tuning word M, which serves as the multiplicand, by a digital multiplier B=2 (decimal). The resulting product (MB) is applied to a first input of an n-bit adder 310 in the accumulator 304, and the accumulator 304 is configured so that it accumulates at a rate of fixed precision reference clock of frequency f.sub.CLK/B=f.sub.CLK/2. The accumulator 304 thus accumulates by a step size of (MB), at a rate of f.sub.CLK/B=f.sub.CLK/2.

(12) The post-accumulator digital processing section 306, which is also clocked at f.sub.CLK/B=f.sub.CLK/2, includes two branches within which two waveforms (e.g., sinusoids) are synthesized. The first branch includes an n-bit zero-offset adder 314; a first phase-to-amplitude (-to-p) converter 316; and a first digital-to-analog converter (DAC) 318, and the second branch includes an n-bit step-offset adder 320; a second -to-p converter 322; and a second DAC 324. The output of the accumulator 304 is fed to both branches of the post-accumulator digital processing section 306, specifically, to the zero-offset adder 314 in the first branch and the step-offset adder 320 in the second branch. Accordingly, each n-bit output of the accumulator 304 serves as the augend to both the zero-offset adder 314 and the step-offset adder 320. Whereas the augends to the zero-offset adder 314 and the step-offset adder 320 are the same, the addends are not. In particular, the addend to the zero-offset adder 314 is zero and the addend to the step-offset adder 320 is the tuning word M. In terms of phase, the output of the step-offset adder 320 thus leads the output of the zero-offset adder 314 by (M/2.sup.n)2 radians, or, in terms of time, by t=(M/2.sup.n)/f.sub.OUT seconds. This can be more readily visualized by referring to the phase wheel in FIG. 4, where, for purpose of example: n=5, M=4 and B=2. Phasor 0 in the phase wheel represents the instantaneous phase of a first waveform (i.e., first phase) synthesized in the first branch, and phasor 1, which leads phasor 0 by (M/2.sup.n)2 radians, represents the instantaneous phase of a second waveform (i.e., second phase) synthesized in the second branch. Note that due to the multiplier B=2, both phasors rotate around the phase wheel by steps of (MB)/2.sup.n2 radians, on each tick of the half-speed clock (f.sub.CLK/2). However, beneficially, and as will be discussed in more detail below, both phasors rotate at a rate of only f.sub.CLK/B=f.sub.CLK/2.

(13) The two sequences of summed samples produced at the outputs of the zero-offset and step-offset adders 314 and 320 are directed to the inputs of the first and second -to-p converters 316 and 322. In one embodiment of the invention the first and second -to-p converters 316 and 322 comprise first and second look-up table (LUT) stored in a read-only memory (ROM), and the sequences of summed samples produced at the outputs of the step-offset and zero-offset adders 314 and 320 are used to address the LUTs to determine the appropriate magnitude p (e.g., voltage or current magnitude) to be assigned for each input sample. The left-most timing diagrams in FIG. 5 show the first and second digital sinusoids produced at the outputs of the -to-p converters 316 and 322. As can be seen, for this example of n=5, M=4, B=2, the first and second digital sinusoids each has 2.sup.n/(MB)=32/8=4 samples per cycle, and a frequency of: [(MB)/2.sup.n](f.sub.CLK/B)=(M/2.sup.n)f.sub.CLK.

(14) It should be mentioned that although the -to-p converters in the exemplary embodiments disclosed herein are described and illustrated as being configured to produce sinusoidal waveforms, they and the DDSs can be alternatively configured to produce other types of waveforms (e.g., square, triangular etc.), as will be appreciated by those of ordinary skill in the art. It should also be mentioned that although multiple -to-p converters (two in the exemplary DDS 300 depicted in FIG. 3) are used to complete the -to-p conversion, a single, shared LUT could be used, instead. Still further, it should be mentioned that, although a ROM-based -to-p conversion is used in this exemplary embodiment of the DDS 300, a ROM-less -to-p conversion process, for example, one that computes or approximates the first and second waveforms on-the-fly, could be employed, instead.

(15) The middle timing diagram in FIG. 5 shows the quantized analog sinusoidal waveforms after having been converted by the first and second DACs 318 and 324. In one embodiment of the invention the serializer 308 comprises a switch or multiplexer that simply toggles the two outputs from the post-accumulator digital processing section 306 at full-speed, i.e., at a rate of f.sub.CLK, to produce the final DDS output OUT. In a different embodiment of the invention, the digital-to-analog conversion and serialization are subsumed into a single interleaved radio frequency DAC (RF-DAC). In either approach, once the samples have been serialized into the full-speed serialized output OUT, they can then be passed through a low-pass filter to remove aliasing images and quantization noise.

(16) One significant advantage the DDS 300 has over the prior art DDS 100 is that the DDS 300 can produce an output OUT having the same output frequency f.sub.OUT and same frequency tuning resolution as the prior art DDS 100 but while clocking the accumulator 304 at only half the reference clock frequency, i.e., f.sub.CLK/2. The post-accumulator digital processing section 306 also operates at half-speed. In fact, the only component of the DDS 300 that operates at full speed (f.sub.CLK) is the serializer 308 (or the interleaved DAC, if it is used, instead). Viewed another way, for the same accumulator width n and same tuning word M, when the accumulator 304 is configured to accumulate at the same rate as the accumulator 102 in the prior art DDS 100, i.e., at a reference clock frequency f.sub.REF=f.sub.CLK/B=f.sub.CLK/2, the DDS 300 synthesizes an output waveform having a frequency f.sub.OUT that is two times (i.e., double) the output frequency of the prior art DDS 100. Accordingly, when viewed from this perspective, the DDS 300 may be aptly referred to as a frequency-doubling or frequency-multiplying DDS 300.

(17) The frequency-multiplying attribute of the present invention is not limited to a DDS having a multiplier of B=2. FIG. 6 shows, for example, how frequency multiplying can be extended to a multiplier of B=8. According to this exemplary DDS 600, the accumulator 602 and post-accumulator digital processing section 604 operate slowly, at a clock rate of f.sub.CLK/8. Only the interleaved RF-DAC 606 needs to operate at full speed (f.sub.CLK). For the same reference clock frequency, the frequency-multiplying property of the DDS 600 thus affords the ability to produce an output frequency f.sub.OUT eight times that produced by the prior art DDS 100.

(18) FIG. 7 is a drawing of a phase wheel for the DDS 600, where, for purpose of example it is assumed that n=6, M=2 and B=8. Phasor 0 in the phase wheel represents the instantaneous phase of a first sinusoid being synthesized in the first branch of the eight-branch post-accumulator digital processing section 604; phasor 1 represents the instantaneous phase of a second sinusoid being synthesized in the second branch, and so on. The phase wheel further shows that phasor 7 leads phasor 6 by (M/2.sup.n)2 radians, phasor 6 leads phasor 5 by the same by (M/2.sup.n)2 radians, etc. Since in this example B=8 and M=2, all eight phasors rotate around the phase wheel in steps of (MB)/2.sup.n2 radians, one step per each tick of the slow-speed clock (f.sub.CLK/8). FIG. 8 shows timing diagrams of the digital sinusoids produced at the outputs of the -to-p converters 608-0, 608-1, . . . 608-7 (left-most column of timing diagrams); the quantized analog waveforms produced by the digital-to-analog conversion process (middle column of timing diagrams); and the full-speed serialized output OUT produced by the interleaved RF-DAC 606 (right-most diagram). The timing diagrams illustrate: 1) how each of the eight digital sinusoids (i.e., phases) synthesized in the eight branches of the post-accumulator digital processing section 604 (i.e., each of the eight DDS phases) is offset from an adjacent phase by t=(M/2.sup.n)1/f.sub.OUT=(1/32)1/f.sub.OUT seconds; 2) how each digital phase has 2.sup.n/(MB)=64/16=4 samples per cycle 1/f.sub.OUT; 3) how the serialized DAC output OUT has B2.sup.n/(MB)=32 samples per cycle 1/f.sub.OUT; and 4) how the final serialized DAC output OUT has an output frequency f.sub.OUT=(M/2.sup.n)f.sub.CLK. The first thirty-two samples of the first period of the output OUT are labeled 1 to 32 in the DAC outputs timing diagram (middle column of timing diagrams), to illustrate how (effectively) the low-speed samples produced by the post-accumulator digital processing section 604 are scanned and serialized by the interleaved RF-DAC 606. As with the DDS 300 described above, if necessary or desired, the final output analog waveform OUT produced by the DDS 600 can be passed through a low-pass filter to remove aliasing images and quantization noise.

(19) From the foregoing description it should be clear that the output frequency f.sub.OUT of the DDSs 300 and 600 can be increased not only by increasing the value of the multiplier B but also by increasing the value of f.sub.CLK. There is, however, a fundamental limit on how fast the accumulators 304 and 602 can accumulate and, consequently, how fast their reference clocks can be. This limit can be more readily understood by referring to FIG. 9, which depicts in more detail one way the accumulators 304 and 602 can be constructed. The accumulator 900 comprises n registers (in this case, n delay or D flip-flops ((DFFs)) and n full adders, and the carry-out of each lower-significant-bit full adder is connected to the carry-in of its adjacent and next-significant-bit full adder. The bottleneck that constrains the maximum possible reference clock frequency f.sub.CLK/B relates to the carry logic of the full adders. Specifically, the DFFs cannot be triggered until the carry bits from the full adders have propagated through the entire n-bit carry propagation path. This propagation delay can be significant if n is large.

(20) To mitigate this problem, in one embodiment of the invention, instead of employing an accumulator 900 like that depicted in FIG. 9, a pipelined accumulator 1000 similar to that depicted in FIG. 10 is used. (For ease in illustration, only a 4-bit example is provided in the drawing. In an actual implementation, the width n would normally be much wider than 4.) Partitioning the n-bit carry propagation path with registers (DFFs) 1002-0, 1002-1, 1002-2 retimes the system to effectively reduce the n-bit carry propagation delay to that of just a single one-bit adder. This provides the accumulator 1000 the time it needs to update its output on every cycle of the reference clock. (Note that, in addition to the partitioning registers 1002-0, 1002-1, 1002-3, the pipelined accumulator 1000 further includes ancillary pre-skewing and de-skewing registers 1004 and 1006. These additional registers are included so that coherency is maintained between the accumulator input (m.sub.3, m.sub.2, m.sub.1, m.sub.0) and accumulator output (s.sub.3, s.sub.2, s.sub.1, s.sub.0).

(21) By using a pipelined accumulator, the maximum possible reference clock frequency f.sub.CLK(max) and, consequently, the maximum output frequency f.sub.OUT(max) can be increased above that which is possible using a non-pipelined accumulator, albeit at the expense of increased latency. A similar pipelining approach can be used for the n-bit adders in the post-accumulator digital processing sections 306 and 604 of the DDSs 300 and 600. For example, with respect to the DDS 300 described above in reference to FIG. 3, the n-bit zero-offset and step-offset adders 314 and 320 could be partitioned in a manner similar to how the pipelined accumulator 1000 in FIG. 10 is partitioned.

(22) While various embodiments of the present invention have been described, they have been presented by way of example and not limitation. Persons skilled in the relevant art will appreciate and understand that various changes in form and detail may be made to the exemplary embodiments of the invention, as presented, without departing from the true spirit and scope of the invention. Accordingly, the scope of the invention should not be limited by the specifics of the exemplary embodiments but, instead, should be determined by the appended claims, including the full scope of equivalents to which such claims are entitled.