METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT, AND OPTOELECTRONIC COMPONENT

Abstract

A method for producing an optoelectronic component by providing a semiconductor layer sequence on a substrate where the semiconductor layer sequence is configured to emit radiation. The method may further include applying a contact layer to the semiconductor layer sequence where the contact layer has a layer thickness of at most 10 nm. The method may further include applying a reflective layer to the contact layer and applying a barrier layer directly to the reflective layer.

Claims

1. A method for producing an optoelectronic component; wherein the method comprises: providing a semiconductor layer sequence on a carrier, the semiconductor layer sequence configured for radiation emission, the semiconductor layer sequence comprising at least one n-doped semiconductor layer, at least one p-doped semiconductor layer, and an active layer arranged between the n- and p-doped semiconductor layers; applying a contact layer directly onto the semiconductor layer sequence, the contact layer having a layer thickness of at most 10 nm, wherein the contact layer reduces diffusion of the material of a mirror layer to the semiconductor layer sequence; applying the mirror layer directly onto the contact layer, and applying a barrier layer directly onto the mirror layer; wherein: the contact layer comprises zinc or zinc oxide, the mirror layer comprises silver, the contact layer being used as a growth layer for the mirror layer and therefore influencing the grain size distribution and orientation of the silver mirror layer; and the contact layer and the barrier layer having have different material compositions, wherein the barrier layer comprises a conductive metal nitride.

2. The method as claimed in claim 1, wherein the contact layer is used as a growth layer for the mirror layer .

3. The method as claimed in claim 1, wherein the layer thickness of the contact layer is less than the layer thickness of the barrier layer.

4. The method as claimed in claim 1, wherein the layer thickness of the contact layer is less than the layer thickness of the barrier layer at least by the factor 1/20.

5. The method as claimed in claim 1, wherein the layer thickness of the contact layer ranges from 0.05 nm to 3 nm.

6. The method as claimed in claim 1, wherein the contact layer comprises a transparent conductive oxide or a metal.

7. The method as claimed in claim 1, wherein the contact layer comprises zinc oxide.

8. The method as claimed in claim 1, wherein the contact layer comprises zinc.

9. The method as claimed in claim 1, wherein the contact layer is configured as a surface-wide monolayer.

10. The method as claimed in claim 1, wherein the contact layer is applied directly onto the p-doped semiconductor layer, the contact layer being directly followed by the mirror layer and the mirror layer having the same structuring as the contact layer.

11. The method as claimed in claim 1, wherein the mirror layer comprises a reflective metal.

12. The method as claimed in claim 1, wherein the semiconductor layer sequence comprises indium gallium nitride or gallium nitride.

13. The method as claimed in claim 1, wherein the mirror element at the same time forms the p-terminal contact for contacting of the p-doped semiconductor layer.

14. The method as claimed in claim 1, wherein the contact layer and barrier layer comprise different materials.

15. The method as claimed in claim 1, claims, wherein applying the contact layer occurs by sputtering.

16. An optoelectronic component obtainable by a method as claimed in claim 1.

17. A method for producing an optoelectronic component, wherein the method comprises: providing a semiconductor layer sequence on a carrier, the semiconductor layer sequence configured for radiation emission, the semiconductor layer sequence comprising at least one n-doped semiconductor layer, at least one p-doped semiconductor layer, and an active layer arranged between the n- and p-doped semiconductor layers; applying a mirror layer onto the semiconductor layer sequence; applying a barrier layer directly onto the mirror layer, the barrier layer comprising a transparent conductive oxide to form an arrangement; heat-treating the arrangement, the transparent conductive oxide diffusing at least partially through the mirror layer and being deposited as a layer on the semiconductor layer sequence, so that a contact layer is formed, wherein: the contact layer has a layer thickness of at most 10 nm; and the layer thickness of the contact layer is less than the layer thickness of the barrier layer.

18. The method as claimed in claim 17, wherein the contact layer is configured as a surface-wide monolayer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Further advantages, advantageous embodiments and refinements may be found by way of non-limiting examples described below in connection with the figures.

[0052] FIGS. 1A to 1D show a method for producing an optoelectronic component according to one embodiment,

[0053] FIGS. 2A to 2Z show a method for producing an optoelectronic component, and

[0054] FIGS. 3A to 3D show a method for producing an optoelectronic component according to one embodiment.

DETAILED DESCRIPTION

[0055] In the exemplary embodiments and figures, elements which are the same or of the same type, or which have the same effect, may respectively be provided with the same references. The elements represented and their size proportions with respect to one another are not to be regarded as true to scale. Rather, individual elements, for example layers, component parts, components and regions, may be represented exaggeratedly large for better representability and/or for better understanding.

[0056] FIGS. 1A to 1D show a method for producing an optoelectronic component 100 according to one embodiment.

[0057] According to FIG. 1A, a carrier 7 is provided. The carrier 7 may, for example, be made of sapphire.

[0058] A semiconductor layer sequence 1 is applied on the carrier 7. The semiconductor layer sequence 1 is adapted for radiation emission. The semiconductor layer sequence emits radiation from the IR, UV and/or visible wavelength range. The semiconductor layer sequence 1 comprises at least one n-doped semiconductor layer 11, at least one p-doped semiconductor layer 12 and an active layer 13 arranged between the n- and p-doped semiconductor layers 11, 12.

[0059] According to FIG. 1B, a contact layer 3 may be applied on the semiconductor layer sequence 1. In particular, the contact layer 3 is applied directly onto the semiconductor layer sequence 1. In particular, the contact layer is applied in a structured fashion. This structuring may be carried out by flat application of the contact layer 3 onto the semiconductor layer sequence 1 and subsequent structuring, for example by means of etching, a photoresist mask or wet chemical liftoff.

[0060] The contact layer 3 prevents or reduces diffusion of the material of a mirror layer 4, which is applied according to FIG. 1C onto the contact layer 3, such as directly. The contact layer 3 may, for example, be formed from zinc oxide. The mirror layer 4 may, for example, be formed from silver.

[0061] As an alternative or in addition, instead of preventing or reducing diffusion of the material of a mirror layer, the contact layer may on the one hand influence the growth behavior and the crystal orientation of further layers, and on the other modify the species involved in contact in their composition.

[0062] In a subsequent method step, as shown in FIG. 1D, a barrier layer 5 may be applied directly onto the mirror layer 4. The contact layer and the barrier layer may comprise the same material or different materials. For example, the contact layer and barrier layer may be formed from zinc oxide. As an alternative, the contact layer may be formed from zinc oxide and the barrier layer from titanium-tungsten. The contact layer 3, the mirror layer 4 and the barrier layer 5 form a first mirror element 9.

[0063] FIGS. 2A to 2Z show a method for producing an optoelectronic component. The method for p-contact deposition, for example the method of FIGS. 1A to 1D or the method of FIGS. 3A to 3D, may be integrated into this method. As an alternative, the method for p-contact deposition may also be integrated into other process flows, such as a method of thin-film technology.

[0064] FIG. 2A shows the provision of a carrier 7, on which an n-doped semiconductor layer 11, an active layer 13 (not shown here) and a p-doped semiconductor layer 12 are applied.

[0065] Subsequently, photostructuring may be carried out with a first mask 19, shown in FIG. 2B.

[0066] Subsequent to this, as shown in FIG. 2C, a first mirror element 9 may be applied in regions which are not covered by the first mask 19 on the p-doped semiconductor layer 12. The first mirror element 9 may, for example, be produced by the method according to FIGS. 1B to 1D.

[0067] In the subsequent method step, as shown in FIG. 2D, the first mask 19 may be removed by means of a removal method, such as a resist strip or wet chemical liftoff.

[0068] Subsequently, as shown in FIG. 2E, a second photomask 23 may be applied. The second photomask 23 may be used to produce the first metallization 401 (p-metallization).

[0069] FIG. 2F shows the application of the first metallization 401, which may in particular comprise platinum, gold and titanium. The first metallization 401 is applied between the second mask 23 and the first mirror element 9.

[0070] In the subsequent method step, as shown in FIG. 2G, the second mask 23 may be removed by means of a removal method, such as a resist strip or wet chemical liftoff.

[0071] Subsequently, as shown in FIG. 2H, a first insulation layer 2 may be applied surface-wide onto the p-doped semiconductor layer 12. The first insulation layer 2 in this case typically corresponds to a double layer consisting of two insulation materials, such as silicon oxide and silicon nitride.

[0072] Subsequently, as shown in FIG. 2I, a next photostructuring step may be carried out. To this end, a third mask 25 may be applied.

[0073] Subsequently, as shown in FIG. 2J, the regions not covered by the third photomask 25 may be removed. The p-doped semiconductor layer 12 and the n-doped semiconductor layer 11 are therefore exposed by means of plasma etching.

[0074] Subsequently, the third mask 25 may be removed by means of a removal method, such as a resist strip or wet chemical liftoff (see FIG. 2K).

[0075] Subsequently, as shown in FIG. 2L, a second insulation layer 301 is applied surface-wide. The second insulation layer 301 may be multiple layers and consist of three layer sequences, each layer consisting of silicon nitride and silicon oxide.

[0076] In FIG. 2M, it is shown that a further photostructuring step may be carried out. To this end, a fourth photomask 27 may be applied. This is used to produce the second mirror element 10 for the n-doped semiconductor layer 11.

[0077] FIG. 2N shows the structuring step by means of etching, and FIG. 2O shows the application of the second mirror element 10 in the previously structured regions.

[0078] The second mirror element 10 may typically be formed from zinc oxide and silver.

[0079] Subsequently, as shown in FIG. 2P, the fourth mask 27 may be removed.

[0080] Subsequently, as shown in FIG. 2Q, a further photostructuring step may be carried out by means of a fifth mask 31. The structuring is used to apply a so-called combo mirror 32 (see FIGS. 2R and 2S). The combo mirror 32 may, for example, be of TiAgPtTi. The combo mirror 32 is applied in the previously structured regions onto the second mirror element 10.

[0081] Subsequently, the fifth mask may be removed, as shown in FIG. 2S. The removal may be carried out by means of a removal method, such as a resist strip or wet chemical liftoff.

[0082] In a subsequent method step, shown in FIG. 2T, the third metallization 60 for contacting the n-doped semiconductor layer 11 may be applied surface-wide. The third metallization 60 may comprise titanium, platinum, gold and nickel.

[0083] Subsequently, the contact metallization 16 as is shown in FIG. 2U, may be applied.

[0084] The contact metallization may consist of a layer structure, which comprises for example a first layer of titanium, nickel, tin and gold, a second layer of titanium, tungsten and nickel, a third layer of gold and a fourth layer of platinum.

[0085] The component may comprise a substrate 8, as shown in FIG. 2U. The substrate 8 may be formed from silicon.

[0086] FIG. 2V differs from FIG. 2U by its spatial orientation.

[0087] Subsequently, as shown in FIG. 2W, the carrier 7 may be removed.

[0088] Subsequently, as likewise shown in FIG. 2W, a mesa trench 15 may be introduced inside the n-doped semiconductor layer 11.

[0089] FIG. 2X shows the roughening 17 of the n-doped semiconductor layer 11 and the application of a passivation layer 18. The passivation layer 18 may be opened again (see FIG. 2Y). A contact pad 30 (pad metallization) (see FIG. 2Z) may be introduced into this opening 29.

[0090] The result is a component which is also known as a so-called UX3 chip.

[0091] FIGS. 3A to 3D show a method for producing an optoelectronic component according to one embodiment.

[0092] According to FIG. 3A, a carrier 7, for example consisting of sapphire, is provided, on which a semiconductor layer sequence 1 is arranged. With regard to the semiconductor layer sequence 1, reference is made to the comments above.

[0093] According to FIG. 3B, the mirror layer 4 may be applied directly onto the semiconductor layer sequence 1. In particular, the mirror layer 4 is applied directly and in a structured fashion onto the semiconductor layer sequence 1. Subsequently, a barrier layer 5, for example of zinc oxide, may be applied directly onto the mirror layer 4. The barrier layer 5 comprises a transparent conductive oxide, for example zinc oxide.

[0094] Subsequently, a heat-treatment step may be carried out so that the arrangement shown in method step C) or in FIG. 3C is heated. The heating may, for example, be carried out at temperatures of more than 200 C. with or without addition of O.sub.2.

[0095] By heat-treatment, the transparent conductive oxide of the barrier layer 5 diffuses through the mirror layer 4 and accumulates as a layer on the semiconductor layer sequence 1, in particular directly on the semiconductor layer sequence 1.

[0096] A contact layer 3 is therefore formed, as is shown 3D.

[0097] The contact layer 3 comprises, in particular, the same material as the barrier layer 5. The concentration of the material of the contact layer 3 and of the barrier layer 5 may be the same or different.

[0098] The contact layer 3 has a layer thickness of at most 10 nm. In a non-limiting embodiment, the contact layer 3 is configured as a monolayer. The surface-wide monolayer may be formed in a structured fashion. A surface-wide monolayer is in this case intended to mean that the monolayer which is formed below the mirror element is arranged surface-wide below the mirror element. In other words, the monolayer is formed continuously and homogeneously below the mirror element.

[0099] In particular, the layer thickness of the contact layer is less than the layer thickness of the barrier layer. In a non-limiting embodiment, the layer thickness of the contact layer differs from the layer thickness of the barrier layer by the factor 1/20.

[0100] The exemplary embodiments described in connection with the figures and their features may also be combined with one another according to further exemplary embodiments, even if such nominations are not explicitly shown in the figures. Furthermore, the exemplary embodiments described in connection with the figures may comprise additional or alternative features according to the description in the general part.

[0101] This patent application claims the priority of German Patent Application 10 2017 123 154.4, the disclosure content of which is incorporated here by back reference.

[0102] The description with the aid of the exemplary embodiments does not restrict the invention to these exemplary embodiments. Rather, the invention comprises any new feature and any combination of features, which includes in particular any combination of features in the patent claims, even if this feature or this combination is not itself explicitly indicated in the patent claims or the exemplary embodiments.

LIST OF REFERENCES

[0103] 100 optoelectronic component

[0104] 1 semiconductor layer sequence

[0105] 2 first insulation layer

[0106] 3 contact layer

[0107] 5 mirror layer

[0108] 5 barrier layer

[0109] 6 diffusion

[0110] 7 carrier

[0111] 8 substrate

[0112] 9 first mirror element

[0113] 10 second mirror element

[0114] 11 n-doped semiconductor layer

[0115] 12 p-doped semiconductor layer

[0116] 13 active layer

[0117] 15 trench or mesa trench

[0118] 16 contact metallization

[0119] 17 roughening

[0120] 18 passivation layer

[0121] 19 first mask

[0122] 20 dielectric

[0123] 23 second mask

[0124] 25 third mask

[0125] 27 fourth mask

[0126] 29 structuring/opening

[0127] 30 pad-metallization

[0128] 31 fifth mask

[0129] 32 combo mirror

[0130] 60 third metallization

[0131] 301 second insulation layer

[0132] 401 first metallization (p-metallization)