CONTROL METHOD AND DEVICE EMPLOYING PRIMARY SIDE REGULATION IN A QUASI-RESONANT AC/DC FLYBACK CONVERTER WITHOUT ANALOG DIVIDER AND LINE-SENSING

Abstract

A primary-side controlled high power factor, low total harmonic distortion, quasi resonant converter converts an AC mains power line input to a DC output for powering a load, such as a string of LEDs. The AC mains power line input is supplied to a transformer that is controlled by a power switch. A device for controlling a power transistor of a power stage includes a shaper circuit including a first current generator configured to output a first current responsive to a bias voltage signal and to generate a reference voltage signal based on the first current. A bias circuit includes a second current generator configured to output a second current responsive to a compensation voltage signal and to generate the bias voltage based on the second current. An error detection circuit includes a third current generator configured to output a third current responsive to the reference voltage signal and to generate the compensation voltage signal based on the third current. A driver circuit has a first input configured to receive the reference voltage signal and having an output configured to drive the power transistor.

Claims

1. A device for controlling a power transistor of a power stage, comprising: a shaper circuit including a first current generator configured to receive a bias voltage signal and configured to generate a first current that is proportional to the bias voltage signal, and configured to generate a reference voltage signal based on the first current; a bias circuit including a second current generator configured to receive a compensation voltage signal and configured to output a second current responsive to the compensation voltage signal, and configured to generate the bias voltage signal based on the second current; an error detection circuit including a third current generator configured to receive the reference voltage signal and configured to output a third current responsive to the reference voltage signal, and configured to generate the compensation voltage signal based on the third current; and a driver circuit having a first input configured to receive the reference voltage signal and having an output configured to provide a drive signal to drive the power transistor based on the reference voltage signal.

2. The device of claim 1, wherein the shaper circuit comprises: a first capacitor coupled between a first node and a reference voltage node, the first current generator coupled to the first node to charge the first capacitor and thereby generate the reference voltage on the first node; and a first switch coupled in series with a first resistive circuit between the first node and the reference voltage node, the first switch being configured to couple the resistive circuit in parallel with the first capacitor to discharge the first capacitor when the drive signal turns on the power transistor.

3. The device of claim 2, wherein the bias circuit further comprises: the second current generator configured to generate the second current that is proportional to the compensation voltage signal; a second capacitor coupled between a second node and the reference voltage node; a second switch coupled in series with a second resistive circuit between the second node and the reference voltage node, the second switch being configured to couple the second resistive circuit in parallel with the second capacitor to discharge the second capacitor when the drive signal turns on the power transistor; and a third switching circuit coupled between the second current generator and the second node, the third switching circuit configured to couple the second current generator to the second node to charge the second capacitor and thereby generate the bias voltage signal responsive to a freewheeling signal being active to indicate a demagnetization mode of operation, and the third switching circuit further configured isolate the second current generator from the second node and to couple the second node to the reference voltage node responsive to the freewheeling signal being inactive.

4. The device of claim 3, wherein the error detection circuit comprises: the third current generator configured to generate the third current that is proportional to the reference voltage signal; a third resistive circuit coupled between a third node and the reference voltage node; a fourth switching circuit coupled between the third current generator and the third node, the fourth switching circuit configured to couple the third current generator to the third node to provide the third current through the third resistive circuit to generate a comparison voltage signal responsive to the freewheeling signal being active, and the fourth switching circuit further configured isolate the third current generator from the third node and to couple the third node to the reference voltage node responsive to the freewheeling signal being inactive; and an error amplifier having a first input coupled to the third node and a second input coupled to receive an internal reference voltage signal, the error amplifier configured to generate on an output the compensation voltage signal responsive to the difference between the comparison voltage signal and the internal reference voltage signal.

5. The device of claim 4, wherein the driver circuit further comprises a zero current detection circuit configured to detect that a primary current through a primary winding of a transformer being driven by the power switch is less than a threshold value, the zero current detection circuit configured to activate the freewheeling signal responsive to the primary current being less than the threshold value and to deactivate the freewheeling signal responsive to the primary current being equal to or greater than the threshold value.

6. The device of claim 5, wherein the error detection circuit further comprises a third capacitor coupled between the third node and a reference voltage node.

7. The device of claim 5, wherein the error amplifier comprises a transconductance error amplifier having a compensation capacitor coupled between an output of the transconductance error amplifier and a reference voltage node.

8. The device of claim 5, wherein the shaper circuit, bias circuit, error detection circuit and drive circuit are formed in an integrated circuit.

9. A converter system, comprising: a rectifier configured to receive an AC input voltage signal and to output a rectified input voltage signal; a transformer having a primary winding having first and second nodes, the first node of the primary winding being coupled to the rectifier to receive the rectified input voltage signal and the transformer having a secondary winding configured to be coupled to drive a load; a power switch coupled having a first signal node coupled to the second node of the primary winding and having a second signal node coupled to a reference voltage node, the power transistor further including a control node; a controller coupled to the driver circuit, the controller comprising: a driver circuit configured to generate a drive signal that is applied the control node of the power switch to control the turning on and turning off of the power switch, the driver circuit generating the drive signal in response to a reference voltage signal; a shaper circuit including a first current generator configured to receive a bias voltage signal and configured to generate a first current that is proportional to the bias voltage signal, and configured to generate the reference voltage signal based on the first current; a bias circuit including a second current generator configured to receive a compensation voltage signal and configured to output a second current responsive to the compensation voltage signal, and configured to generate the bias voltage based on the second current; an error detection circuit including a third current generator configured to receive the reference voltage signal and configured to output a third current responsive to the reference voltage signal, and configured to generate the compensation voltage signal based on the third current.

10. The converter system of claim 9, wherein the power switch comprises a power MOSFET transistor.

11. The converter system of claim 9 further comprising a sense resistor coupled in series between the second signal node of the power switch and the reference voltage node, the sense resistor generating a sense voltage responsive to current through the primary winding and power switch and the driver circuit generating the drive signal responsive to the sense voltage.

12. The converter system of claim 9, wherein the secondary of the transformer is coupled to drive a load comprising at least one light emitting diode.

13. The converter system of claim 12, wherein the transformer further comprises an auxiliary winding configured to generate an auxiliary voltage signal indicating a zero current condition through the primary winding, the drive circuit configured to generate the drive signal based on the auxiliary voltage signal.

14. The converter system of claim 9, wherein the controller is formed in a single integrated circuit.

15. The converter system of claim 14 wherein the controller controls the power switch to operate the converter system as a quasi-resonant flyback converter.

16. The converter system of claim 9, wherein the shaper circuit comprises: a first capacitor coupled between a first node and a reference voltage node, the first current generator coupled to the first node to charge the first capacitor and thereby generate the reference voltage on the first node; and a first switch coupled in series with a first resistive circuit between the first node and the reference voltage node, the first switch being configured to couple the resistive circuit in parallel with the first capacitor to discharge the first capacitor when the drive signal turns on the power transistor.

17. The converter system of claim 16, wherein the bias circuit comprises: the second current generator configured to generate the second current that is proportional to the compensation voltage signal; a second capacitor coupled between a second node and the reference voltage node; a second switch coupled in series with a second resistive circuit between the second node and the reference voltage node, the second switch being configured to couple the second resistive circuit in parallel with the second capacitor to discharge the second capacitor when the drive signal turns on the power transistor; and a third switching circuit coupled between the second current generator and the second node, the third switching circuit configured to couple the second current generator to the second node to charge the second capacitor and thereby generate the bias voltage signal responsive to a freewheeling signal being active to indicate a demagnetization mode of operation, and the third switching circuit further configured isolate the second current generator from the second node and to couple the second node to the reference voltage node responsive to the freewheeling signal being inactive.

18. The converter system of claim 17, wherein the error detection circuit comprises: the third current generator configured to generate the third current that is proportional to the reference voltage signal; a third resistive circuit coupled between a third node and the reference voltage node; a fourth switching circuit coupled between the third current generator and the third node, the fourth switching circuit configured to couple the third current generator to the third node to provide the third current through the third resistive circuit to generate a comparison voltage signal responsive to the freewheeling signal being active, and the fourth switching circuit further configured isolate the third current generator from the third node and to couple the third node to the reference voltage node responsive to the freewheeling signal being inactive; and an error amplifier having a first input coupled to the third node and a second input coupled to receive an internal reference voltage signal, the error amplifier configured to generate on an output the compensation voltage signal responsive to the difference between the comparison voltage signal and the internal reference voltage signal.

19. The converter system of claim 18, wherein the driver circuit further comprises a zero current detection circuit configured to detect that a primary current through a primary winding of a transformer being driven by the power switch is less than a threshold value, the zero current detection circuit configured to activate the freewheeling signal responsive to the primary current being less than the threshold value and to deactivate the freewheeling signal responsive to the primary current being equal to or greater than the threshold value.

20. The converter system of claim 9, wherein the error amplifier comprises a transconductance error amplifier having a compensation capacitor coupled between an output of the transconductance error amplifier and a reference voltage node.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0009] FIG. 1 is a schematic of a primary-controlled Hi-PF QR Flyback converter implementing a prior art primary-side control method.

[0010] FIGS. 2A and 2B are timing diagrams illustrating key waveforms in the flyback converter of FIG. 1 during operation of the converter.

[0011] FIG. 3 is a schematic of a primary-controlled Hi-PF QR flyback converter according to one embodiment of the present disclosure.

[0012] FIGS. 4A and 4B are timing diagrams illustrating key waveforms in the flyback converter of FIG. 3 during operation of the converter.

[0013] FIG. 5 is a timing diagram showing simulation results for the flyback converter of FIG. 3 for an input voltage Vac=115Vac.

[0014] FIG. 6 is a timing diagram showing simulation results for the flyback converter of FIG. 3 for an input voltage Vac=230Vac.

[0015] FIGS. 7A and 7B are graphs showing simulation results comparing the total harmonic distortion (THD) of the flyback converters of FIGS. 1 and 3 in FIG. 7A and comparing the power factor PF of the two converters FIG. 7B.

[0016] FIG. 8 is a graph showing simulation results comparing regulation of the average output current provided by the flyback converters of FIGS. 1 and 3.

DETAILED DESCRIPTION

[0017] FIG. 1 is a schematic of a conventional hi-PF QR flyback converter 100 that will now be described to provide a better understanding of such a converter before discussing hi-PF QR flyback converters according to embodiments of the present disclosure. On the primary side, the QR flyback converter 100 includes a controller 102, a bridge rectifier 104 having inputs 106 coupled to an AC mains power line that supplies an AC mains input voltage V.sub.ac (θ), an input capacitor C.sub.in, a voltage divider R.sub.a-R.sub.b coupled to the bridge rectifier 104, a primary winding L.sub.p and an auxiliary winding L.sub.aux of a transformer 108, a power switch M coupled to the transformer 108 and controlled by controller 102, a sensing resistor R.sub.s coupled in series with the power switch M to provide a sensed voltage to the controller indicating a current flowing through the power, a zero-crossing detection resistor R.sub.ZCD coupled to the auxiliary winding L.sub.aux, and a clamp circuit 109 connected across the primary winding L.sub.p to clamp a leakage inductance of the primary winding.

[0018] On the secondary side of the converter 100, secondary winding L.sub.s of the transformer 108 has one end connected to a secondary ground GND2 and the other end connected to the anode of a diode D having the cathode connected to the positive plate of a capacitor C.sub.out that has its negative plate connected to the secondary ground. The converter 100 provides an output voltage V.sub.out that supplies power to a load 110, which in FIG. 1 is a set of series-connected LEDs, although other loads could be supplied with electrical power by the converter 100.

[0019] The controller 102 has a reference voltage estimation circuit 116 that is configured to produce a reference voltage Vcs.sub.REF (θ) and includes a bias circuit 118 and a shaper circuit 120. The controller 102 also includes a driver circuit 121 having a PWM comparator 122, a set-reset (SR) flip-flop 124, an OR gate 126, and driver 127 configured to drive the power switch M. The PWM comparator 122 includes an inverting input that receives the reference voltage V.sub.CSREF (θ), a non-inverting input that receives a sense voltage V.sub.CS from the sense resistor R.sub.s, and an output that provide a reset signal to a reset input R of the flip-flop 124. The flip-flop 124 also includes a set input S coupled to an output of the OR gate 126, and an output that is coupled to an input of the driver 127. The OR gate 126 also has first and second inputs coupled to respective outputs of a starter block 128 and a zero current detection (ZCD) block 130. The OR gate 126 provides a set signal to the set input S of the SR flip flop when the ZCD block 130 detects that a falling edge of an auxiliary voltage V.sub.aux as applied through a resistor R.sub.ZCD goes below a threshold, or when the starter block 128 produces a start signal to initiate a switching cycle. The transformer 108 includes an auxiliary coil as shown in FIG. 1 which generates the auxiliary voltage V.sub.aux. The starter block 128 outputs a signal at power-on when no signal is available on the input of the ZCD block 130 and prevents the converter 100 from getting “stuck” in the event the signal on the input of the ZCD block 130 is lost for any reason. The ZCD block 130 also generates a freewheeling signal FW that is high during demagnetization of the transformer 108, as shown in FIG. 2A, and is used by the reference voltage estimation circuit 116 to generate a B(θ) signal, as will be described in more detail below.

[0020] FIGS. 2A and 2B are timing diagrams illustrating key waveforms in the flyback converter 100 of FIG. 1 during operation, with the waveforms in FIG. 2A being on a switching period time scale and the waveforms in FIG. 2B being on an AC mains power line cycle time scale. The freewheeling signal FW is high during demagnetization (i.e., energy stored in the primary winding L.sub.p is transferred to the secondary winding L.sub.s) of the transformer 108 and is low otherwise. Thus, as seen in FIG. 2A, the FW signal is low during a delay time T.sub.R during which a secondary current I.sub.s (t,θ) through the secondary winding Ls has gone to zero. This delay time T.sub.R in the quasi-resonant (QR) flyback converter 100 is the delay between the instant the transformer 108 demagnetizes (i.e. a secondary current I.sub.s (t,θ) equals zero) and the turning ON of the power switch M. The FW signal stays low during the magnetic energy storage phase when the power switch M is turned ON and a primary current I.sub.p (t,θ) flows through the primary winding L.sub.p to thereby store magnetic energy in the primary winding.

[0021] The shaper circuit 120 has a first current generator 140, a resistor R.sub.t1 coupled to an output of the first current generator 140, a switch 132 that switchably couples the resistor R.sub.t1 to ground, and a capacitor C.sub.t1 coupled between the output of the current generator 140 and ground. The first current generator 140 has an input coupled to a supply voltage terminal Vcc and a control terminal coupled to the voltage divider R.sub.a-R.sub.b via a pin MULT. The first current generator 140 produces a current I.sub.CH1 (θ) based on a value of the voltage generated by the voltage divider R.sub.a-R.sub.b and present on the MULT pin. The switch 132 is controlled by the output Q of the flip-flop 124 and thereby connects the capacitor C.sub.t1 in parallel with the switched resistor R.sub.t1 when the power switch M is ON.

[0022] The bias circuit 118 includes a second current generator 142 having an input coupled to the supply terminal Vcc, a control terminal coupled to the output of the first current generator 140, and an output at which the second current generator produces a current I.sub.CH (θ). A second switched resistor R.sub.t is switchably coupled to the output of the second current generator 142 by a switch 134 configured to connect the resistor R.sub.t to the second current generator 142 under the control of the signal FW provided by the ZCD block 130. The signal FW is high when the current is flowing in the secondary winding L.sub.s. Another switch 144 is coupled to the output of the second current generator 142 and is configured to connect the output of the second current generator 142 to ground when the ZCD block 130 drives a signal FW, which is the complement or inverted version of the signal FW, high, indicating no current is flowing in the secondary winding L.sub.s as seen in FIG. 2A.

[0023] The reference voltage estimation circuit 116 also includes a divider block 146 having a first input that receives a signal A(θ) from the shaper circuit 120, a second input that receives the signal B(θ) from the bias circuit 118, and an output at which the divider provides the reference voltage Vcs.sub.REF (θ). The signal A(θ) is generated by the first current generator 140 acting on the switched resistor Rt1 and capacitor Ct1. The current Ich1 (θ) produced by the current generator 140 is proportional to a rectified input voltage Vin(θ) produced at the voltage divider Ra-Rb and supplied to the current generator 140 through the MULT pin. The divider ratio Rb/(Ra+Rb) of the voltage divider Ra-Rb will be denoted as Kp herein. The resistor Rt1 is connected in parallel to the capacitor Ct1 by the switch 132 when the signal Q of the SR flip flop 124 is high, i.e. during the on-time of the power switch M, and is disconnected when the signal Q is low, i.e. during the off-time of the power switch M. The voltage developed across the capacitor C.sub.t1 is A(θ) and is fed to the first input of the divider block 146. The current generator 140, capacitor C.sub.t1, resistor R.sub.t1 and switch 132 collectively form the shaper circuit 120, which is termed a “shaper” circuit because the circuit changes the shape of the current programming signal.

[0024] In the flyback converter 100 of FIG. 1, a capacitor C.sub.T is coupled to a pin CT of the controller 102 and is assumed to be large enough so that the AC component (at twice the AC mains input line frequency f.sub.L) of the B(θ) signal is negligible, at least to a first approximation, with respect to the DC component B0 of the B(θ) signal. As a result, the divider block 146 provides the reference voltage Vcs.sub.REF (θ) that is the division of the A(θ) signal generated by the shaper circuit 120 by the B(θ) signal generated by the bias circuit 118.

[0025] The inverting input of the PWM comparator 122 receives the reference voltage Vcs.sub.REF (θ) the non-inverting input receives the voltage Vcs(t, θ), which is the voltage sensed across the sense resistor Rs that is a voltage proportional to the instantaneous current Ip(t, θ) flowing through the primary winding Lp and the power switch M when the power switch is turned ON. Assuming the power switch M is initially turned ON, the current through the primary winding Lp will be ramping up and so will the voltage across the resistor Rs. When the voltage Vcs(t, θ) across the sense resistor Rs equals the reference voltage Vcs.sub.REF (θ), the PWM comparator 122 drives its output to reset the PWM latch or SR flip-flop 124, causing the SR flip-flop to drive its output Q low to thereby turn OFF the power switch M. Therefore, the reference voltage Vcs.sub.REF (θ) provided by the divider block 146 determines the peak value of the primary current Ip(t, θ) that, as a result, will be enveloped as the A(θ) signal.

[0026] After the power switch M is switched OFF, the energy stored in the primary winding Lp is transferred by magnetic coupling to the secondary winding Ls and then transferred to the output capacitor Cout and the load 110 until the secondary winding Ls is completely demagnetized. At this point, the diode D opens (i.e., turns OFF) and the drain node of the power switch M, which while the secondary winding Ls and the diode D were conducting was fixed at a voltage Vin(θ)+VR, is in a floating or high impedance state. The voltage VR is the reflected voltage, which is the output voltage Vout across the secondary winding Ls times the primary-to-secondary turns ratio n=Np/Ns of the transformer 108. The reflected voltage VR would tend to eventually reach the instantaneous input voltage Vin(θ) through a damped ringing due to a parasitic capacitance that starts resonating with the primary winding Lp. The quick fall of the drain voltage of the power switch M that follows demagnetization of the transformer 108 is coupled through the auxiliary winding Laux and the resistor R.sub.ZCD to the pin ZCD of the controller 102. The ZCD block 130 is coupled to the ZCD pin and generates a pulse every time the ZCD block detects a negative-going edge falling below a threshold, and this pulse is applied through the OR gate 126 to set the PWM latch 124 and thereby turn ON the power switch M, starting a new switching cycle of the flyback converter 100. The OR gate 126 allows the output of the “STARTER” block to also initiate a switching cycle by applying a signal through the OR gate to set the PWM latch 124. As previously described, this serves at power-on when no signal is available on the ZCD pin input and prevents the converter 100 from getting stuck in case the signal on the ZCD input is lost for any reason.

[0027] As shown in FIG. 2A the OFF-time of the power switch M is the sum of the time T.sub.FW (θ) during which the primary winding Lp is discharged and a time T.sub.R during which the secondary winding Ls current has gone to zero. As a result, the switching period T(θ) of the flyback converter 100 is therefore given by:

T(θ)=T.sub.ON(θ)+T.sub.FW(θ)+T.sub.R   (Eqn. 1)

where θ can be considered ∈ (0, π).

[0028] A fundamental assumption for the following analysis is that T(θ)<<(R.sub.t1×C.sub.t1)<<1/f.sub.L. In this way, on the one hand the switching frequency ripple across capacitor C.sub.t1 is negligible while on the other hand the current I.sub.ch1 (θ) can be considered constant within each switching cycle. This being assumed, it is possible to find the A(θ) signal or voltage developed across capacitor C.sub.t1 by charge balance according to:

[00001]$\begin{array}{cc}{I}_{\mathrm{ch}.Math..Math.1}\left(\theta \right).Math.T\left(\theta \right)=\frac{A\left(\theta \right)}{R_{t.Math..Math.1}}.Math.T_{\mathrm{ON}}\left(\theta \right)& \left(\mathrm{Eqn}..Math.2\right)\end{array}$

[0029] The current I.sub.ch1 (θ) is provided by the current generator 140 and it can be expressed as:

I.sub.ch1(θ)=g.sub.m1K.sub.p(V.sub.PK sinθ)   (Eqn. 3)

where g.sub.m1 is the current-to-voltage gain of the current generator 140 that generates the current I .sub.ch1(θ).

[0030] Solving for A(θ) voltage and considering Eqn. 3:

[00002]$\begin{array}{cc}A\left(\theta \right)=R_{t.Math..Math.1}.Math.I_{\mathrm{ch}.Math..Math.1}\left(\theta \right).Math.\frac{T\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}=R_{t.Math..Math.1}.Math.g_{m.Math..Math.1}.Math.K_p\left(V_{\mathrm{PK}}.Math.\sin .Math..Math.\theta \right).Math.\frac{T\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}& \left(\mathrm{Eqn}..Math.4\right)\end{array}$

[0031] The current I.sub.CH(θ) provided by the current generator 140 that is used to generate the B(θ) signal can be expressed as:

I.sub.CH(θ)=G.sub.MA(θ)   (Eqn. 5)

where G.sub.M is the current-to-voltage gain of the current generator 142 that generates the current I.sub.CH(θ).

[0032] Now considering the capacitor C.sub.T by charge balance, it is possible to find the voltage B(θ) developed across the capacitor C.sub.T as follows:

[00003]$\begin{array}{cc}{I}_{\mathrm{CH}}\left(\theta \right).Math.T_{\mathrm{FW}}\left(\theta \right)=\frac{B\left(\theta \right)}{R_T}.Math.T\left(\theta \right)& \left(\mathrm{Eqn}..Math.6\right)\end{array}$

[0033] Solving the previous expression for B(θ) and considering Eqns. (4) and (5):

[00004]$\begin{array}{cc}B\left(\theta \right)=G_M.Math.R_T.Math.g_{m.Math..Math.1}.Math.R_{t.Math..Math.1}.Math.K_p\left(V_{\mathrm{PK}}.Math.\sin .Math..Math.\theta \right).Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}& \left(\mathrm{Eqn}..Math.7\right)\end{array}$

[0034] The capacitor C.sub.T is assumed to be large enough so that the AC component (at twice the AC mains input line frequency f.sub.L) of the voltage B(θ) is negligible with respect to its DC component B.sub.0, which is defined as:

[00005]$\begin{array}{cc}{B}_0=\stackrel{\_}{B\left(\theta \right)}=\frac{1}{\pi }.Math.G_M.Math.R_T.Math.g_{m.Math..Math.1}.Math.R_{t.Math..Math.1}.Math.K_p.Math.{\int }_0^{\pi }.Math.\left(V_{\mathrm{PK}}.Math.\sin .Math..Math.\theta \right).Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}.Math.d.Math..Math.\theta & \left(\mathrm{Eqn}..Math.8\right)\end{array}$

[0035] Considering the voltage-second balance for the Flyback converter's transformer, the primary on time T.sub.ON(θ) and secondary on time T.sub.FW(θ) can be expressed by the following relationship:

V.sub.IN(θ)T.sub.ON(θ)=n(V.sub.OUT+V.sub.F)T.sub.FW(θ)   (Eqn. 9)

where V.sub.F is the forward drop on the diode D.

[0036] Solving Eqn. 9 and considering that Kv=V.sub.PK/VR, where V.sub.R=n(V.sub.OUT=V.sub.F), the ratio between T.sub.FW(θ) and T.sub.ON(θ) times results in the following:

[00006]$\begin{array}{cc}\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}=K_v.Math.\sin .Math..Math.\theta & \left(\mathrm{Eqn}..Math.10\right)\end{array}$

[0037] Combining Eqns. (8) and (10) the DC component of the signal B(θ) results as follows:

[00007]$\begin{array}{cc}{B}_0=\frac{G_M.Math.R_T.Math.g_{m.Math..Math.1}.Math.R_{t.Math..Math.1}.Math.K_p.Math.V_{\mathrm{PK}}.Math.K_v}{2}& \left(\mathrm{Eqn}..Math.11\right)\end{array}$

[0038] Combining Eqns. (11) and (4) the expression for the voltage reference Vcs.sub.REF(θ) results as follows:

[00008]$\begin{array}{cc}{\mathrm{Vcs}}_{\mathrm{REF}}\left(\theta \right)=K_D.Math.\frac{A\left(\theta \right)}{B\left(\theta \right)}\approx K_D.Math.\frac{A\left(\theta \right)}{B_0}=K_D.Math.\frac{2}{G_M.Math.R_T.Math.K_v}.Math.\sin .Math..Math.\theta .Math.\frac{T\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}& \left(\mathrm{Eqn}..Math.12\right)\end{array}$

where K.sub.D is the voltage divider gain and it is dimensionally a voltage.

[0039] Considering that the peak primary current I.sub.pkp(θ) can be expressed as:

[00009]$\begin{array}{cc}{I}_{\mathrm{pkp}}\left(\theta \right)=\frac{{\mathrm{Vcs}}_{\mathrm{REF}}\left(\theta \right)}{\mathrm{Rs}}& \left(\mathrm{Eqn}..Math.13\right)\end{array}$

[0040] then the peak secondary current I.sub.pks(θ) can be calculated by combing Eqns. (13) and (12) and considering that the secondary current is n=Np/Ns times the primary current:

[00010]$\begin{array}{cc}{I}_{\mathrm{pks}}\left(\theta \right)={\mathrm{nI}}_{\mathrm{pkp}}\left(\theta \right)=n.Math..Math.K_D.Math.\frac{2}{G_M.Math.R_T.Math.K_v}.Math.\sin .Math..Math.\theta .Math.\frac{T\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}.Math.\frac{1}{R_S}& \left(\mathrm{Eqn}..Math.14\right)\end{array}$

[0041] Since the cycle-by-cycle secondary current I.sub.s(t, θ) is the series of triangles shown for this waveform in FIG. 2A, the average value of the secondary current I.sub.s(t, θ) in a switching cycle is:

[00011]$\begin{array}{cc}{I}_o\left(\theta \right)=\frac{1}{2}.Math.I_{\mathrm{pks}}\left(\theta \right).Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T\left(\theta \right)}=\frac{{\mathrm{nK}}_D}{G_M.Math.R_T.Math.K_v}.Math.\sin .Math..Math.\theta .Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}.Math.\frac{1}{R_S}& \left(\mathrm{Eqn}..Math.15\right)\end{array}$

[0042] The dc output current Iout is the average of Io(θ) over a line half-cycle:

[00012]$\begin{array}{cc}{I}_{\mathrm{out}}=\stackrel{\_}{I_o\left(\theta \right)}=\frac{1}{\pi }.Math.{\int }_0^{\pi }.Math.\frac{{\mathrm{nK}}_D}{G_M.Math.R_T.Math.{\mathrm{KvR}}_S}.Math.\sin .Math..Math.\theta .Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}.Math.d.Math..Math.\theta & \left(\mathrm{Eqn}..Math.16\right)\end{array}$

[0043] Finally, combining Eqns. (16) and (10), the average output current I.sub.out from the converter 100 is given as:

[00013]$\begin{array}{cc}{I}_{\mathrm{out}}=\frac{{\mathrm{nK}}_D}{2.Math.G_M.Math.R_T.Math.R_S}& \left(\mathrm{Eqn}..Math.17\right)\end{array}$

[0044] Equation (17) states that the DC output current I.sub.out from the converter 100 depends only on external, user-selectable parameters (n, Rs) and on internally fixed parameters (G.sub.M, R.sub.T, K.sub.D) and does not depend on the output voltage Vout, or on the root mean square (RMS) input voltage V.sub.in(θ) or on the switching frequency f.sub.SW(θ)=1/T(θ).

[0045] The input current I.sub.in(θ) to the converter 100 is found by averaging the primary current I.sub.p(t, θ), which is the series of triangles for the I.sub.p(t, θ) current in FIG. 2A over a switching cycle of the converter. From Eqns. (12) and (13), the input current I.sub.in(θ) is given by:

[00014]$\begin{array}{cc}{I}_{i.Math..Math.n}\left(\theta \right)=\frac{1}{2}.Math.I_{\mathrm{pkp}}\left(\theta \right).Math.\frac{T_{\mathrm{ON}}}{T\left(\theta \right)}=\frac{1}{R_S}.Math.\frac{K_D}{G_M.Math.R_T.Math.K_v}.Math.\sin .Math..Math.\theta & \left(\mathrm{Eqn}..Math.18\right)\end{array}$

[0046] Equation (18) shows that the input current I.sub.in(θ) is a pure sinusoid in all operating conditions so the converter 100 has ideally a unity power factor and zero harmonic distortion of the input current (i.e., PF=1 and THD=0).

[0047] From the above description of the hi-PF QR flyback converter 100, it is seen that this converter is hi-PF and low THD converter and utilizes a control algorithm that is able to regulate the DC output current and voltage using primary-side control (i.e., using only operational quantities available on the primary side of the converter. This is opto-less control, as previously discussed. Thus, while this control scheme advantageously provides QR operation mode with opto-less primary-side control and a hi-PF and low THD, the control scheme utilizes the line-sensing circuitry formed by the voltage divider including resistors Ra and Rb, which has a relatively significant power consumption, and also utilizes the analog divider block 146, which occupies a relatively large portion or area of an integrated circuit in which the controller 102 is formed. The flyback converter 100 of FIG. 1 is described in detail in U.S. patent application Ser. No. 14/572,627, which is incorporated herein by reference in its entirety to the extent the disclosure of this application is not inconsistent with the disclosure of the present application.

[0048] As a result of these drawbacks of the flyback converter 100 as described above with reference to FIGS. 1 and 2, the present disclosure is directed to primary-side control techniques for a QR flyback converter that do not require such line-sensing circuitry and analog divider circuitry while still providing hi-PF and low THD operation, as will now be described in more detail.

[0049] Referring to Eqn. (16) above, the DC output current I.sub.out if a QR flyback converter can be expressed, by combining Eqns. (16), (15), (13) and (14), as follows:

[00015]$\begin{array}{cc}{I}_{\mathrm{out}}=\stackrel{\_}{I_o\left(\theta \right)}=\frac{n}{2.Math..Math.\pi .Math..Math.\mathrm{Rs}}.Math.{\int }_0^{\pi }.Math.{\mathrm{Vcs}}_{\mathrm{REF}}\left(\theta \right).Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T\left(\theta \right)}.Math.d.Math..Math.\theta & \left(\mathrm{Eqn}..Math.19\right)\end{array}$

[0050] Equation (19) shows that the DC output current L.sub.out can be regulated using only quantities available on the primary side of the flyback converter and without an analog divider block 146 (FIG. 1) if the quantity on the right-hand side of Eqn. (19) is constant, which means independent of the output voltage V.sub.out, the RMS input voltage V.sub.in(θ) and from the switching frequency f.sub.SW(θ)=1/T(θ)). The second consideration is based on the transformer voltage-second balance as set forth in Eqn. (9) that can be expressed as:

[00016]$\begin{array}{cc}\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}=\frac{V_{\mathrm{in}}\left(\theta \right)}{n\left(V_{\mathrm{OUT}}+V_F\right)}& \left(\mathrm{Eqn}..Math.20\right)\end{array}$

which shows that the shape of the input voltage V.sub.in(θ) needed to achieve high-PF and low-THD can be estimated without using line-sensing circuitry by generating a voltage proportional to the ratio between the free-wheeling time T.sub.FW(θ) and the ON-time T.sub.ON(θ) of the power switch M, as will now be described in detail with reference to FIGS. 3-8.

[0051] FIG. 3 is a schematic of a primary-controlled Hi-PF QR flyback converter 300 including a controller 302 for controlling the converter without line-sensing circuitry or an analog divider circuit according to one embodiment of the present disclosure. FIGS. 4A and 4B are timing diagrams illustrating key waveforms generated in the flyback converter 300 during operation and will be discussed in more detail below. In FIG. 4A the designated waveforms or signals are on a switching period time scale along the horizontal axis while in FIG. 4B the waveforms are on an AC mains line cycle time scale on the horizontal axis.

[0052] In the flyback converter 300 of FIG. 3, components 304-310 correspond to the components 104-110 previously described with reference to the converter 100 of FIG. 1. Thus, for the sake of brevity, the detailed operation of these components 304-310 will not again be discussed in detail with reference to the converter 300 of FIG. 3. Other components of the converter 300 are also the same as those in the converter 100 of FIG. 1, such as zero current detection resistor R.sub.ZCD, input capacitor C.sub.in, power switch M and sense resistor Rs, for example. The detailed individual operation of all such components will also not again be provided with reference to FIG. 3. Finally, the same is even true of some components of the controller 302, which executes a different control method to control the operation of the converter 300 than does the controller 102 of FIG. 1. For example, the controller 302 includes a driver circuit 312 including components 314-324 having the same structure and functionality as corresponding components in the driver circuit 121 of FIG. 1. The individual operation of these components 314-324 has thus effectively been described with reference to the driver circuit 121 of FIG. 1 and will not again be described in detail with reference to the driver circuit 312 of FIG. 3. In FIG. 3, all the components external to the controller 302 may be considered the power stage of the flyback converter 300.

[0053] While the driver circuit 312 of the controller 302 has the same structure and operation as the driver circuit 121 of the controller 102 of FIG. 1, the controller 302 further includes a reference voltage estimation circuit 326 having a different structure and different operation than the voltage reference circuit 116 in the controller 102 of FIG. 1, as will now be described in more detail. In operation, the reference voltage estimation circuit 326 generates a first reference voltage Vcs.sub.REF(θ) that is supplied to the inverting input of the PWM comparator 314 of the driver circuit 312. The reference voltage estimation circuit 326 includes a shaper circuit 328 having the same structure as the shaper circuit 120 of FIG. 1. More specifically, the shaper circuit 328 includes a first current generator 330 that supplies a first current I.sub.ch1(θ) to a node 332 on which the first reference voltage Vcs.sub.REF(θ) is generated. This first current I.sub.ch1(θ) has a value that is based on a voltage V.sub.G(θ) generated by a bias circuit that will be described in more detail below. A resistor R.sub.G is coupled in series with a switch SW1 between the node 332 and ground, with the switch being controlled by the output signal Q provided by the PWM latch 316. A capacitor C.sub.t1 is also coupled between the node 332 and ground and is charged by the current I.sub.ch1(θ) from the first current generator 330 to generate the reference voltage Vcs.sub.REF(θ) on the node 332. When the output signal Q is activated or turned ON to thereby turn ON the power switch M, the Q signal also closes the switch SW1 to thereby discharge the capacitor C.sub.t1 through the resistor R.sub.t1 and reduce the reference voltage Vcs.sub.REF(θ).

[0054] The reference voltage estimation circuit 326 further includes a bias circuit 334 that generates the voltage V.sub.G(θ) that is supplied to the current generator 330 to set the value of the first current I.sub.ch1(θ). The bias circuit 334 includes a second current generator 336 that generates a second current a current I.sub.ch2(θ) that is supplied through one of a pair of complementary switches SW3 to a node 338. The second current I.sub.ch2(θ) has a value that is based on a compensation signal V.sub.COMP(θ) generated by other circuitry in the controller 302 that will be described in more detail below. A resistor R.sub.t2 is coupled in series with a switch SW4 between the node 338 and ground, with the switch SW4 being controlled by the output signal Q from the PWM latch 316.

[0055] A capacitor C.sub.t2 is also coupled between the node 338 and ground and is charged by the current I.sub.ch2(θ) from the second current generator 336 when the FW signal generated by the ZCD block 322 closes the one of the complementary switches SW3 connected between the second current generator 336 and the node 338. In this situation, the current I.sub.ch2(θ) from the second current generator 336 charges the capacitor C.sub.t2 to generate the voltage V.sub.G(θ) on the node 338. When the output signal Q is activated or turned ON to thereby turn ON the power switch M, the Q signal also closes the switch SW4 to thereby discharge the capacitor C.sub.t2 through the resistor R.sub.t2 and reduce the voltage V.sub.G(θ). The other one of the complementary switches SW3 is coupled between the second current generator 336 and ground and is controlled by the FW signal, namely the inverted version or complement of the FW signal generated by the ZCD block 322). The FW signal goes high when no current is flowing in the secondary winding L.sub.s, which is seen through the FW signal illustrated in FIG. 4A.

[0056] Finally, the controller 302 includes other circuitry that generates the compensation signal V.sub.COMP(θ) as previously mentioned. This other circuitry includes a third current generator 340 having a control terminal coupled to the node 332 to receive the reference voltage Vcs.sub.REF(θ). The third current generator 340 generates a third current I.sub.ch3(θ) having a value based on the value of the reference voltage Vcs.sub.REF(θ). The third current I.sub.ch3(θ) is supplied through one of a pair of complementary switches SW2 to charge a node 342, with this switch being controlled by the FW signal from the ZCD block 322. A resistor R.sub.t3 is coupled between the node 342 and ground and generates a comparison voltage V.sub.CT(θ) on the node 342 responsive to the third current I.sub.ch3(θ) when the corresponding one of the complementary switches SW2 is closed, which occurs when the FW signal is high indicating current is flowing in the secondary winding L.sub.s. The other one of the complementary switches SW2 is coupled between the third current generator 340 and ground and, when the signal FW is active high, which occurs when FW is low when no current is flowing through the secondary winding L.sub.s, this switch sinks the current I.sub.ch3(θ) from the third current generator to ground.

[0057] A transconductance error amplifier 344 has an inverting input coupled to the node 342 which, in turn, is also coupled to a CT pin of the controller 302. A capacitor C.sub.t3 is coupled to the CT pin and thus to the node 342 and is assumed to be large enough so that an AC component at twice the AC mains line frequency f.sub.L of the comparison voltage V.sub.CT(θ) on the node 342 is negligible with respect to a DC component this voltage, as will be described in more detail below. A non-inverting input of the transconductance error amplifier 344 receives an internal reference voltage V.sub.REF and generates an output current based on the differential voltage across the inverting and non-inverting inputs of the amplifier. Thus, the transconductance error amplifier 344 generates an output current having a value based on the difference between the voltage on the node 342 and the reference voltage V.sub.REF. The output current from the transconductance amplifier 344 charges a compensation capacitor C.sub.COMP to thereby generate the compensation signal V.sub.COMP(θ) on the output the transconductance amplifier. The compensation capacitor C.sub.COMP is coupled to a COMP pin of the controller 302, with the COMP pin being coupled to the output of the transconductance amplifier 344 as seen in FIG. 3.

[0058] In the embodiment of FIG. 3, the controller 302 is formed in an integrated circuit having the pins CT, COMP, GND, GD, and ZCD coupled to the circuitry of the controller as shown, some of which have been discussed in the above description. Within the controller 302, the transconductance error amplifier 344, current generator 340, switches SW2 and resistor R.sub.t3 may collectively be considered an error detection circuit 346. The capacitors C.sub.t3 and C.sub.COMP, although external to the integrated circuit in the embodiment of FIG. 3, may also be considered to be part of the error detection circuit 346. The same is true for the sense resistor Rs, which may be considered part of the driver circuit 312 that was previously described above.

[0059] The theory of operation of the controller 302 in controlling the overall operation of the flyback converter 300 will now be described in more detail with reference to FIGS. 3, 4A and 4B. Considering the voltage V.sub.COMP(θ) generated on the output of the transconductance error amplifier 344, the capacitor C.sub.COMP is assumed to be large enough so that the AC component at twice the line frequency f.sub.L of the voltage V.sub.COMP(θ) is negligible with respect to the DC component V.sub.COMP0, at least to a first approximation. The DC component V.sub.COMP0 of the voltage V.sub.COMP(θ) is defined as:

V.sub.COMP0=g.sub.mC[V.sub.REF−V.sub.CT(θ)]  (Eqn. 21)

where g.sub.mC is the current-to-voltage gain of the transconductance error-amplifier 344, the voltage V.sub.REF is the internal voltage reference, and the comparison voltage V.sub.CT(θ) is the voltage developed across the capacitor C.sub.t3.

[0060] The capacitor C.sub.t2 is charged through the current I.sub.ch2(θ) from the second current generator 336 when the signal FW is high, i.e. during transformer's demagnetization, and the capacitor C.sub.t2 is discharged through the resistor R.sub.t2 resistor when the signal Q is high, i.e. during the on-time of the power switch M. A fundamental assumption for the present analysis is that T(θ)<<R.sub.t2×C.sub.t2>>1/f.sub.L. In this way, on the one hand the switching frequency ripple across the capacitor C.sub.t2 is negligible and on the other hand the current I.sub.ch2(θ) can be considered constant within each switching cycle. Using these assumptions, it is possible to find the voltage V.sub.G(θ) developed across the capacitor C.sub.t2 by charge balance as follows:

[00017]$\begin{array}{cc}{I}_{\mathrm{ch}.Math..Math.2}\left(\theta \right).Math.T_{\mathrm{FW}}\left(\theta \right)=\frac{V_G\left(\theta \right)}{R_{t.Math..Math.2}}.Math.T_{\mathrm{ON}}\left(\theta \right)& \left(\mathrm{Eqn}..Math.22\right)\end{array}$

The current I.sub.ch2(θ) provided by the current generator 336 can be expressed as:

I.sub.ch2(θ)=g.sub.m2V.sub.COMP0   (Eqn. 23)

where g.sub.m2 is the current-to-voltage gain of the current generator 336. Solving Eqn. (22) for the voltage V.sub.G(θ), and considering the Eqns. (10) and (23), it can be shown that the voltage V.sub.G(θ) is given by the following:

V.sub.G(θ)=gm.sub.2R.sub.t2V.sub.COMPOK.sub.V sin θ  (Eqn. 24)

[0061] The resistor R.sub.t1 is connected in parallel to the capacitor C.sub.t1 when the signal Q is high, i.e. during the on-time of the power switch M, and is disconnected when the signal Q is low, i.e. during the off-time of the power switch M. The voltage developed across the capacitor C.sub.t1 is the current sensed reference voltage Vcs.sub.REF(θ) and is supplied to the inverting input of the PWM comparator 314. The current generator 330 that generates current I.sub.ch1(θ), capacitor C.sub.t1, resistor R.sub.t1 plus the switch SW1 is referred to as the shaper circuit 328 as mentioned above since the circuit changes the shape of the current programming signal.

[0062] The current I.sub.ch1(θ) provided by the current generator 330 can be expressed as:

I.sub.ch1(θ)=g.sub.m1V.sub.G(θ)   (Eqn. 25)

where g.sub.m1 is the current-to-voltage gain of the current generator 330 that generates the current I.sub.ch1(θ) and the voltage V.sub.G(θ) is the voltage developed across the capacitor C.sub.t2.

[0063] The same previous assumption is also considered to apply to the shaper circuit 328, namely T(θ)<<R.sub.t1×C.sub.t1>>1/f.sub.L. In this way, on the one hand the switching frequency ripple across the capacitor C.sub.t1 is negligible while on the other hand the current I.sub.ch1(θ) can be considered constant within each switching cycle. Using these assumptions, it is possible to find the voltage Vcs.sub.REF(θ) developed across the capacitor C.sub.t1 by charge balance as follows:

[00018]$\begin{array}{cc}{I}_{\mathrm{ch}.Math..Math.1}\left(\theta \right).Math.T\left(\theta \right)=\frac{V_{{\mathrm{CS}}_{\mathrm{REF}}}\left(\theta \right)}{R_{t.Math..Math.1}}.Math.T_{\mathrm{ON}}\left(\theta \right).& \left(\mathrm{Eqn}..Math.26\right)\end{array}$

Solving for the voltage Vcs.sub.REF(θ) in Eqn. (26) and considering Eqns. (24) and (25), it can shown that:

[00019]$\begin{array}{cc}{V}_{\mathrm{CS},\mathrm{REF}}\left(\theta \right)={\mathrm{gm}}_1.Math.R_{t.Math..Math.1}.Math.{\mathrm{gm}}_2.Math.R_{t.Math..Math.2}.Math.V_{\mathrm{COMP}.Math..Math.0}.Math.K_V.Math.\sin .Math..Math.\theta .Math.\frac{T\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}.& \left(\mathrm{Eqn}..Math.27\right)\end{array}$

[0064] The input current I.sub.IN(θ) of the flyback converter 300 can be found by averaging the primary current I.sub.p(t, θ) through the primary winding L.sub.p and switch M, where this primary current has a peak value expressed by

[00020]$I_{\mathrm{pkp}}\left(\theta \right)=\frac{V_{\mathrm{CS},\mathrm{REF}}\left(\theta \right)}{R_S}$

[0065] and, taking into consideration Eqn. (27), the input current may be expressed as:

[00021]$\begin{array}{cc}{I}_{\mathrm{IN}}\left(\theta \right)=\frac{1}{2}.Math.I_{\mathrm{pkp}}\left(\theta \right).Math.\frac{T_{\mathrm{ON}}}{T\left(\theta \right)}=V_{\mathrm{COMP}.Math..Math.0}.Math.{\mathrm{gm}}_1.Math.R_{t.Math..Math.1}.Math.{\mathrm{gm}}_2.Math.R_{t.Math..Math.2}.Math.\frac{K_V}{2.Math..Math.R_S}.Math.\sin .Math..Math.\theta & \left(\mathrm{Eqn}..Math.28\right)\end{array}$

The Eqn. (28) shows that the controller 302 of FIG. 3 implements a control method that achieves a sinusoidal input current I.sub.IN(θ), which as previously discussed means that the converter 300 ideally has a power factor PF=1 and distortion THD=0 in the constant-current primary-controlled Hi-PF QR flyback converter 300 without using the line-sensing circuitry (e.g., the voltage divider formed by the resistors Ra, Rb in FIG. 1).

[0066] In the controller 302, the current generator 340 that generates the current I.sub.ch3(θ) that is used to generate the comparison voltage V.sub.CT(θ) signal, and this current can be expressed as:

I.sub.ch3(θ)=G.sub.MV.sub.CS,REF(θ)   (Eqn. 29)

where G.sub.M is the current-to-voltage gain of the current generator 340. Now considering the capacitor C.sub.t3 by charge balance, it is possible to find the comparison voltage V.sub.CT(θ) developed across the capacitor C.sub.t3 as follows:

[00022]$\begin{array}{cc}{I}_{\mathrm{ch}.Math..Math.3}\left(\theta \right).Math.T_{\mathrm{FW}}\left(\theta \right)=\frac{V_{\mathrm{CT}}\left(\theta \right)}{R_{t.Math..Math.3}}.Math.T\left(\theta \right)& \left(\mathrm{Eqn}..Math.30\right)\end{array}$

Solving Eqn. (30) for the comparison voltage V.sub.CT(θ) and then considering Eqn. (27), it can be shown that:

[00023]$\begin{array}{cc}{V}_{\mathrm{CT}}\left(\theta \right)=G_M.Math.R_{t.Math..Math.3}.Math.{\mathrm{gm}}_1.Math.R_{t.Math..Math.1}.Math.{\mathrm{gm}}_2.Math.R_{t.Math..Math.2}.Math.K_V.Math.V_{\mathrm{COMP}.Math..Math.0}.Math.\sin .Math..Math.\theta .Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}& \left(\mathrm{Eqn}..Math.31\right)\end{array}$

[0067] Similar to the prior approach of FIG. 1, the capacitor C.sub.t3 is assumed to be large enough so that the AC component at twice the AC mains input line frequency f.sub.L of the comparison voltage V.sub.CT (θ) is negligible with respect to its DC component V.sub.CT0, at least to a first approximation. The DC component V.sub.CT0 is then given by:

[00024]$\begin{array}{cc}{V}_{\mathrm{CT}.Math..Math.0}=\stackrel{\_}{V_{\mathrm{CT}}\left(\theta \right)}=\frac{1}{\pi }.Math.G_M.Math.R_{t.Math..Math.3}.Math.{\mathrm{gm}}_1.Math.R_{t.Math..Math.1}.Math.{\mathrm{gm}}_2.Math.R_{t.Math..Math.2}.Math.V_{\mathrm{COMP}.Math..Math.0}.Math.K_V.Math.{\int }_0^{\pi }.Math.\sin .Math..Math.\theta .Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}.Math.d.Math..Math.\theta & \left(\mathrm{Eqn}..Math.32\right)\end{array}$

[0068] Now considering the voltage-second balance for the transformer 308 of the flyback converter as expressed in Eqn. (10), the DC component V.sub.CT0 can be shown to be given by:

[00025]$\begin{array}{cc}{V}_{\mathrm{CT}.Math..Math.0}=\frac{1}{\pi }.Math.G_M.Math.R_{t.Math..Math.3}.Math.{\mathrm{gm}}_1.Math.R_{t.Math..Math.1}.Math.{\mathrm{gm}}_2.Math.R_{t.Math..Math.2}.Math.V_{\mathrm{COMP}.Math..Math.0}.Math.K_V^2.Math.{\int }_0^{\pi }.Math.\sin .Math..Math.{\theta }^2.Math.d.Math..Math.\theta =\frac{G_M.Math.R_{t.Math..Math.3}.Math.{\mathrm{gm}}_1.Math.R_{t.Math..Math.1}.Math.{\mathrm{gm}}_2.Math.R_{.Math.t.Math..Math.2}}{2}.Math.K_V^2.Math.V_{\mathrm{COMP}.Math..Math.0}& \left(\mathrm{Eqn}..Math.33\right)\end{array}$

Assuming the low-frequency “loop gain”>>1, then the DC component V.sub.CT0 is equal to the internal reference V.sub.REF:

V.sub.CT0=V.sub.REF   (Eqn. 34)

Combining Eqn. (34) with Eqns. (33) and (27), the current reference voltage is shown to be:

[00026]$\begin{array}{cc}{V}_{\mathrm{CS},\mathrm{REF}}\left(\theta \right)=\frac{2}{G_M.Math.R_{t.Math..Math.3}}.Math.\frac{V_{\mathrm{REF}}}{K_V}.Math.\sin .Math..Math.\theta .Math.\frac{T\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}& \left(\mathrm{Eqn}..Math.35\right)\end{array}$

If the same mathematical operations are performed for Eqn. (14), the peak secondary current I.sub.pks(θ) of the flyback converter 300 can be calculated starting from Eqn. (35) as follows:

[00027]$\begin{array}{cc}{I}_{\mathrm{pks}}\left(\theta \right)=n.Math.\frac{2}{G_M.Math.R_{t.Math..Math.3}}.Math.\frac{V_{\mathrm{REF}}}{K_V}.Math.\sin .Math..Math.\theta .Math.\frac{T\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}.Math.\frac{1}{R_S}& \left(\mathrm{Eqn}..Math.36\right)\end{array}$

[0069] Since the cycle-by-cycle secondary current I.sub.s(t, θ) is the series of triangles shown in FIG. 4A for this signal, the average value of this secondary current in a switching cycle is given by:

[00028]$\begin{array}{cc}{I}_o\left(\theta \right)=\frac{{\mathrm{nV}}_{\mathrm{REF}}}{G_M.Math.R_{t.Math..Math.3}.Math.K_V}.Math.\mathrm{Sin}.Math..Math.\theta .Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}.Math.\frac{1}{R_S}& \left(\mathrm{Eqn}..Math.37\right)\end{array}$

[0070] The DC output current I.sub.out of the flyback converter 300 is the average of the current I.sub.o(θ) over a main line half-cycle and is given by:

[00029]$\begin{array}{cc}{I}_{\mathrm{out}}=\stackrel{\_}{I_o\left(\theta \right)}=\frac{1}{\pi }.Math.{\int }_0^{\pi }.Math.\frac{{\mathrm{nV}}_{\mathrm{REF}}}{G_M.Math.R_{t.Math..Math.3}.Math.K_V.Math.R_S}.Math.\mathrm{Sin}.Math..Math.\theta .Math.\frac{T_{\mathrm{FW}}\left(\theta \right)}{T_{\mathrm{ON}}\left(\theta \right)}.Math.d.Math..Math.\theta & \left(\mathrm{Eqn}..Math.38\right)\end{array}$

[0071] Finally, combining Eqns. (38) and (10) the average output current of the flyback converter is shown to be:

[00030]$\begin{array}{cc}{I}_{\mathrm{out}}=\frac{V_{\mathrm{REF}}}{G_M.Math.R_{t.Math..Math.3}}.Math.\frac{n}{2.Math..Math.R_S}& \left(\mathrm{Eqn}..Math.39\right)\end{array}$

[0072] The Eqn. (39) shows the control method implemented by the controller 302 of FIG. 3, the DC output current I.sub.out depends only on external, user-selectable parameters, namely the turns ratio n of the transformer 308 and the sense resistor Rs, and on internally fixed parameters (G.sub.M, R.sub.t3, V.sub.REF) and does not depend on the output voltage V.sub.out, or on the RMS of the input voltage V.sub.in(θ), or on the switching frequency f.sub.SW(θ)=1/T(θ). As a result, the control method implemented by controller 302, in addition to providing ideally unity power factor PF=1 and zero harmonic distortion (THD=0) of the input current I.sub.IN(θ), also controls the flyback converter 300 to provide a regulated output current I.sub.out using only quantities available on the primary side of the converter, and without using an analog divider and line-sensing circuitry as were utilized in the converter 100 of FIG. 1.

[0073] The control method implemented by the controller 302 of FIG. 3 has been tested and validated with PSIM simulations, where PSIM is an electronic circuit simulation software package that is specifically designed specifically for use in simulating power electronics circuits. The timing diagrams resulting from some of these simulations are shown in FIGS. 5 and 6. FIG. 5 shows a simulation where the input voltage V.sub.ac(θ) is 115 VAC while FIG. 6 shows a simulation where the input voltage is 230 VAC. As seen in these simulations, there is a very low level of distortion of the input current (around 2.8% at I.sub.in=115 Vac, around 3.2% at I.sub.in=230 Vac) due to an input EMI filter and the non-idealities considered both in the power circuit and the control circuit of the converter 300. FIGS. 7A and 7B are graphs showing simulation results for the converter 300 in comparison to the converter 100, with FIG. 7A showing a comparison of the THD levels of the two converters and FIG. 7B showing a comparison of the power factor PF of the two converters. FIG. 8 is a graph showing simulation results comparing regulation of the average output current I.sub.out of the flyback converters 300 and 100 and illustrates that the converter 300 provides regulation that is just as good as the converter 100 but without requiring the line-sensing and analog divider circuitry to do so, as discussed above.

[0074] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited to the embodiments described in the present disclosure.