Magnetoresistance element and non-volatile semiconductor storage device using same magnetoresistance element

Abstract

The invention provides a magnetoresistance element with a configuration such that a stable switching action is possible with a current flowing in response to the application of a unipolar electrical pulse, and a non-volatile semiconductor storage device using the magnetoresistance element. A magnetoresistance element 1-1 includes a magnetic tunnel junction portion 13 configured by sequentially stacking a perpendicularly magnetized first magnetic body 22, an insulation layer 21, and a perpendicularly magnetized second magnetic body 200. The second magnetic body 200 has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer 21 side interface. A heat assist layer 28-1 that heats the second magnetic body 200 with a heat generated based on a current flowing through the magnetic tunnel junction portion 13 is further provided, and the magnetization direction of the second magnetic body 200 is reversed by the heating of the second magnetic body 200. A non-volatile semiconductor storage device 10-1 includes the magnetoresistance element 1-1, a switching element connected in series to the magnetoresistance element 1-1, information rewriting means that carries out a write and erase by causing a write current to flow through the magnetoresistance element 1-1, and reading means that reads information stored from the amount of current flowing through the magnetoresistance element 1-1.

Claims

1. A method comprising: forming a pinned layer, an insulation layer, and a storage layer; and forming a heat assist layer above the storage layer using reactive sputtering.

2. The method of claim 1, wherein the pinned layer, the insulation layer, and the storage layer are formed using magnetron sputtering.

3. The method of claim 1, further comprising forming an upper electrode above the heat assist layer using magnetron sputtering.

4. The method of claim 1, wherein the heat assist layer comprises TaN.

5. The method of claim 1, further comprising forming a protective layer between the storage layer and the heat assist layer.

6. The method of claim 5, wherein the protective layer comprises at least one of Ta or Ru.

7. The method of claim 1, further comprising forming an upper electrode above the heat assist layer using magnetron sputtering, and wherein the pinned layer, the insulation layer, and the storage layer are formed using magnetron sputtering.

8. The method of claim 7, further comprising: forming a resist above the upper electrode; subsequently removing material not below the resist; subsequently removing the resist; subsequently forming interlayer insulation above the upper electrode; subsequently forming a hole in the interlayer insulation above the upper electrode; and subsequently forming a contact in the hole, such that the contact abuts the upper electrode.

9. The method of claim 8, wherein said removing material not below the resist comprises using ion etching.

10. The method of claim 8, wherein said forming a hole in the interlayer insulation comprises using photolithography.

11. The method of claim 1, wherein: the pinned layer is formed above a lower electrode; and the lower electrode is formed above a portion of a CMOS transistor.

12. The method of claim 11, wherein the portion of the CMOS transistor comprises a drain region.

13. A method comprising: forming a heat assist layer using magnetron sputtering; and above the heat assist layer, forming a pinned layer, an insulation layer, and a storage layer.

14. The method of claim 13, wherein the pinned layer, the insulation layer, and the storage layer are formed using magnetron sputtering.

15. The method of claim 13, further comprising forming an upper electrode above the storage layer using magnetron sputtering.

16. The method of claim 13, wherein the heat assist layer comprises TaN.

17. The method of claim 13, further comprising forming an upper electrode above the storage layer using magnetron sputtering, and wherein the pinned layer, the insulation layer, and the storage layer are formed using magnetron sputtering.

18. The method of claim 17, further comprising: forming a resist above the upper electrode; subsequently removing material not below the resist; subsequently removing the resist; subsequently forming interlayer insulation above the upper electrode; subsequently forming a hole in the interlayer insulation above the upper electrode; and subsequently forming a contact in the hole, such that the contact abuts the upper electrode.

19. The method of claim 18, wherein said removing material not below the resist comprises using ion etching.

20. The method of claim 18, wherein said forming a hole in the interlayer insulation comprises using photolithography.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a sectional view showing a configuration of a magnetoresistance element according to a first embodiment of the invention.

(2) FIG. 2 is a graph showing magnetization-temperature characteristics of the magnetoresistance element according to the first embodiment.

(3) FIGS. 3A, 3B, 3C, and 3D illustrate schematic diagrams showing an operating principle of the magnetoresistance element according to the first embodiment.

(4) FIGS. 4A, 4B, 4C, and 4D illustrate schematic diagrams showing an operating principle of a magnetoresistance element according to a second embodiment.

(5) FIG. 5a is a sectional view showing a first fabrication step of the magnetoresistance element according to the first embodiment.

(6) FIG. 5b is a sectional view showing a second fabrication step of the magnetoresistance element according to the first embodiment.

(7) FIG. 5c is a sectional view showing a third fabrication step of the magnetoresistance element according to the first embodiment.

(8) FIG. 5d is a sectional view showing a fourth fabrication step of the magnetoresistance element according to the first embodiment.

(9) FIG. 5e is a sectional view showing a fifth fabrication step of the magnetoresistance element according to the first embodiment.

(10) FIG. 5f is a sectional view showing a sixth fabrication step of the magnetoresistance element according to the first embodiment.

(11) FIG. 5g is a sectional view showing a seventh fabrication step of the magnetoresistance element according to the first embodiment.

(12) FIG. 6 is a sectional view showing a configuration of the magnetoresistance element according to the second embodiment of the invention.

(13) FIG. 7 is a graph showing change in resistivity of a metal-insulator transition material;

(14) FIG. 8 is a graph illustrating an action of a magnetoresistance element according to a third embodiment.

(15) FIG. 9 is a schematic diagram showing a memory cell using the magnetoresistance elements shown in FIG. 1 and FIG. 6.

(16) FIG. 10 is a schematic diagram showing a non-volatile semiconductor storage device including a cross-point type memory cell array formed by arraying memory cells.

(17) FIG. 11 is a sectional view showing an example of a configuration of a magnetoresistance element according to a heretofore known technology.

(18) FIGS. 12A and 12B illustrate schematic diagrams showing an operating principle of the magnetoresistance element according to the heretofore known technology.

MODE FOR CARRYING OUT THE INVENTION

(19) Hereafter, a description will be given, based on the drawings, of embodiments of a magnetoresistance element according to the invention, and a storage device using the magnetoresistance element.

First Embodiment

(20) FIG. 1 is a partial enlarged sectional view of a storage device 10-1 showing a portion in which is disposed a magnetoresistance element 1-1 according to the invention. In FIG. 1, components the same as components shown in FIG. 11 are given the same reference numerals, and a description thereof is omitted. The configuration of the magnetoresistance element 1-1 in the first embodiment differs from that of a heretofore known magnetoresistance element 1 in that a storage layer 200 (a second magnetic body) is used instead of a storage layer 20 of the magnetoresistance element 1 shown in FIG. 11, and that a heat assist layer 28-1 is deposited on the storage layer 200. In the embodiment, the storage layer 200 and a pinned layer 22 are each formed of a perpendicularly magnetized film.

(21) The storage layer 200 is configured of a ferromagnetic layer (not shown) and a rare earth-transition metal alloy layer (not shown) stacked sequentially from an insulation layer 21 side interface. The ferromagnetic layer is formed of an N-type ferrimagnetic body.

(22) Meanwhile, the heat assist layer 28-1 is formed of a normal resistive material, as will be described hereafter. The heat assist layer 28-1 is disposed in a way such as to make contact with an interface on the side of the storage layer 200 opposite to the insulation layer 21 side interface.

(23) As an operating principle of a read of the magnetoresistance element 1-1 is the same as that of the heretofore known magnetoresistance element, a description thereof will be omitted.

(24) Next, a description will be given of a principle whereby a write action using a unipolar electrical pulse is possible with the magnetoresistance element 1-1 configured in such a way. In the embodiment, as has already been described, an N-type ferrimagnetic body is used as the ferromagnetic layer in the storage layer 200. The N-type ferrimagnetic body has the kind of magnetization-temperature characteristics shown in FIG. 2. An important point is that when a certain temperature (a compensated temperature T.sub.comp) is exceeded, the magnetization direction of the storage layer 200 is reversed. Herein, it is taken that the compensated temperature of the storage layer 200 is approximately 110 C. The compensated temperature can easily be set by adjusting the composition ratios of the rare earth element and transition metal element in the rare earth-transition metal alloy layer in the storage layer 200. This is also one reason for using a rare earth-transition metal alloy in the storage layer 200.

(25) For a write action from a high resistance condition to a low resistance condition, a spin torque transfer (STT) action the same as in the heretofore known magnetoresistance element is carried out. That is, as shown in FIG. 11, in the heretofore known magnetoresistance element, the storage layer 20 changes from a high resistance condition (FIG. 11 (a)) to a low resistance condition (FIG. 11 (b)) by a current 103 being caused to flow from the storage layer 20 (a second magnetic body) toward a pinned layer 22 (a first magnetic body). In the storage layer 200 in the embodiment too, it is possible to cause a change from a high resistance condition to a low resistance condition by causing the same kind of current to flow.

(26) Hereafter, a description will be given, using FIG. 3, of a write action from a low resistance condition to a high resistance condition. In FIG. 3, arrows 102 and 102A indicate magnetization directions. The heat assist layer 28-1 shown in FIG. 1 is omitted from FIG. 3.

(27) Firstly, when a write current flows, Joule heat is generated owing to the resistance (up to 4 k) of the heat assist layer 28-1, the heat is transmitted from the heat assist layer 28-1 to the storage layer 200, and the storage layer 200 is heated (FIG. 3(a)). When the temperature of the storage layer 200 exceeds the compensated temperature T.sub.comp owing to the heating, the net magnetization of the storage layer 200 is reversed (FIG. 3(b)). By an STT action being carried out in this condition, the storage layer 200 receives a torque directed in the same direction as the pinned layer, and reverses the magnetization direction at this point (FIG. 3(c)). When the supply of the write current stops, the temperature of the storage layer 200 decreases, and the reversed magnetization returns to the original condition when the temperature becomes lower than the compensated temperature T.sub.comp. Because of this, the magnetization directions of the storage layer 200 and pinned layer 22 are opposed directions, and the write action from the low resistance condition to the high resistance condition is completed (FIG. 3(d)).

(28) Herein, for example, TbCo, GdCo, GdFeCo, TbFeCo, or the like, is preferably used as the material of the rare earth-transition metal alloy layer in the storage layer 200 (the second magnetic body) and, for example, a spin-polarized material such as Fe, FeCo, FeCoB, or the like, is preferably used as the material of the ferromagnetic layer in the storage layer 200. As the rare earth-transition metal alloy layer is such that, as previously described, the compensated temperature can easily be adjusted using the composition thereof, the heretofore described action is easily realized, and also, as the rare earth-transition metal alloy layer has a large amount of perpendicular magnetic anisotropic energy (10.sup.5 to 10.sup.6 erg/cc), it can store data for a long period.

(29) It is assumed that the spin-polarized material used as the material of the ferromagnetic layer indicates one of the following two kinds of alloy.

(30) (1) A material with a high spin-polarization rate (for example, a half metal such as a Heusler alloy)

(31) (2) A magnetic body wherein the spin is completely polarized with respect to a 1 band, as with, for example, Fe, FeCo, FeCoB, or the like.

(32) The reason for including the magnetic body of (2), whose spin-polarization rate is not so high, in the spin-polarized materials is as follows. That is, it is because, when a spin tunnel junction is configured by combining the magnetic body (Fe, FeCo, FeCoB, or the like) of (2) with an insulation layer (for example, an insulation layer formed from Mg) having four-fold symmetry with respect to the stacking direction, the insulation layer acts in such a way as to selectively allow the 1 band conduction electrons to pass through, and it is possible to increase the effective spin-polarization rate. With this kind of configuration using FeCo, or the like, it is both theoretically and experimentally demonstrated that, by optimizing the conditions, a magnetoresistance ratio in the region of 1000% is obtained.

(33) Meanwhile, it is desirable that the heat assist layer 28-1 is given a resistance value in the region of 1 k to 50 k. As an STT type write current in an MRAM is in the region of 0.5 to 110.sup.6 A/cm.sup.2, the element temperature exceeds 500 C. when the resistance value of the heat assist layer 28-1 exceeds 50 k, and there is a danger of element breakup. Also, when the resistance value of the heat assist layer 28-1 is in the region of a few hundred Ohms, the temperature rise decreases (a few degrees Celsius), and the heretofore described action becomes difficult. Therefore, a range of 1 k to 50 k is good for the resistance value of the heat assist layer 28-1. Then, when considering the fabrication process, it is desirable that the heat assist layer 28-1 is rather thin (10 to 20 nm). Based on the above, a material having a resistivity of 0.01 cm to 10 cm is appropriate as the heat assist layer 28-1. For example, TaN.sub.x, TaO.sub.x, TiO.sub.x, or the like, are included as this kind of material.

(34) Next, a description will be given, referring to FIG. 5a to FIG. 5g, of a fabrication method of the magnetoresistance element according to the first embodiment.

(35) Firstly, a drain region 24, a source region 25, a gate line 16, a contact portion 17, a word line 18, a lower electrode 14, and an insulation body 23A are formed on a silicon substrate 15 using a normal CMOS process (FIG. 5a).

(36) Next, as shown in FIG. 5b, after stacking the pinned layer 22 (Tb.sub.16Fe.sub.59Co.sub.25 of 5 nm thickness, Fe.sub.10Co.sub.90 of 1 nm thickness), the insulation layer 21 (MgO of 0.7 nm thickness), and the storage layer 200 (Fe.sub.10Co.sub.90 of 1 nm thickness, Gd.sub.22Co.sub.78 of 2 nm thickness) using a magnetron sputtering method, the heat assist layer 28-1 (TaN of 20 nm thickness) is deposited using a reactive sputtering method, and finally, an upper electrode 12 (Ta of 2 nm thickness/Ru of 5 nm thickness) is deposited using a magnetron sputtering method.

(37) Next, a resist 51 is exposed and developed in a circular form with a diameter in the region of 100 nm using photolithography. Next, as shown in FIG. 5c, the sputtered film other than in the resist portion is scraped off using an ion etching. After the resist is removed using a solvent, ashing, or the like, an interlayer insulation film 23B (SiO.sub.2 of 60 nm thickness) is deposited (FIG. 5d). Subsequently, a contact hole 52 is formed using photolithography in a portion above the upper electrode 12 (FIG. 5e, FIG. 5f). Subsequently, a bit line 11 is formed (FIG. 5g). In the way heretofore described, it is possible to fabricate a magnetic memory in the first embodiment of the invention. An oxide protective layer (for example, a Ta layer, a Ru layer, or the like) of a few nanometers may be deposited between the storage layer 200 and heat assist layer 28-1 with an object of suppressing oxygen diffusion from the heat assist layer 28-1, allowing a stable action for a longer time.

(38) Next, a description will be given of a specific action of the magnetoresistance element 1-1i according to the embodiment.

(39) The compensated temperature T.sub.comp of the Gd.sub.22Co.sub.78 used in the storage layer 200 is around 110 C. Therefore, when taking the element size (diameter) to be 100 nm, the heat assist layer 28-1 resistance value to be 4 k, the current density to be 810.sup.5 A/cm.sup.2, and the write current pulse width to be 10 ns, and furthermore, approximating that approximately one half of the Joule heat generated in the heat assist layer 28-1 contributes to the temperature rise of the element, the temperature of the element 1-1 rises approximately 110 C., and consequently, when taking room temperature to be 20 C., the actual element temperature is 130 C. As this is equal to or higher than the compensated temperature T.sub.comp, the heretofore described write action from a low resistance condition to a high resistance condition is realized. Also, when the current density is 6.610.sup.5 A/cm.sup.2, the temperature rise is in the region of 75 C., and as the element temperature is 95 C., which is lower than the compensated temperature T.sub.comp, the write action from a high resistance condition to a low resistance condition is realized. In this way, depending on the size of the write current pulse, it is possible to write both a low resistance condition and a high resistance condition with a current of the same polarity.

Second Embodiment

(40) A description will be given, referring to FIG. 6, of a second embodiment of the invention. A magnetoresistance element 1-2 according to the second embodiment differs from the first embodiment in that the pinned layer 22 (the first magnetic body) in the first embodiment shown in FIG. 1 is replaced with a pinned layer 220, a heat assist layer 28-2 is provided instead of the heat assist layer 28-1 in the first embodiment, and the storage layer 200 (the second magnetic body) in the first embodiment is replaced with the storage layer 20 shown in FIG. 11.

(41) The pinned layer 220 (a first magnetic body) has the configuration of the storage layer 200 of FIG. 1. That is, the pinned layer 220 is configured of a ferromagnetic layer and a rare earth-transition metal alloy layer stacked sequentially from the insulation layer 21 side interface.

(42) Meanwhile, the heat assist layer 28-2 is formed of the same material as the heat assist layer 28-1 of FIG. 1, and is disposed in a way such as to make contact with an interface on the side of the pinned layer 220 opposite to the insulation layer 21 side interface.

(43) Next, a description will be given of an operating principle of the magnetoresistance element 1-2 according to the second embodiment.

(44) As a write action from a high resistance condition to a low resistance condition is exactly the same as with heretofore known technology, in the same way as in the first embodiment, a description thereof will be omitted. Hereafter, a description will be given, referring to FIG. 4, of a write action from a low resistance condition to a high resistance condition. In FIG. 4, arrows 102 and 102A indicate magnetization directions. In the second embodiment, it is taken that the compensated temperature T.sub.comp of the storage layer 20 is 200 C. or more, and the compensated temperature T.sub.comp of the pinned layer 220 is around 110 C.

(45) Firstly, when a write current flows, Joule heat is generated owing to the resistance (up to 4 k) of the heat assist layer 28-2, the heat is transmitted from the heat assist layer 28-2 to the pinned layer 220, and the pinned layer 220 is heated (FIG. 4(a)). When the temperature of the pinned layer 220 exceeds the compensated temperature T.sub.comp owing to the heating, the net magnetization of the pinned layer 220 is reversed (FIG. 4(b)). By an STT action being carried out in this condition, the storage layer 20 receives a torque directed in the same direction as the pinned layer 220, and reverses the magnetization direction at this point (FIG. 4(c)). When the supply of the write current stops, the temperature of the pinned layer 220 decreases, and the reversed magnetization returns to the original condition when the temperature becomes lower than the compensated temperature T.sub.comp. Because of this, the magnetization directions of the storage layer 20 and pinned layer 220 are opposed directions, and the write action from the low resistance condition to the high resistance condition is completed (FIG. 4(d)).

(46) Next, a description will be given of a fabrication method of the magnetoresistance element according to the second embodiment.

(47) Firstly, as shown in FIG. 5a, the drain region 24, the source region 25, the gate line 16, the contact portion 17, the word line 18, the lower electrode 14, and the insulation body 23A are formed on the silicon substrate 15 using a normal CMOS process. Next, as shown in FIG. 5b, the heat assist layer 28-2 (Ta of 20 nm thickness), the pinned layer 220 (Tb.sub.24Fe.sub.53Co.sub.23 of 5 nm thickness, Fe.sub.10Co.sub.90 of 1 nm thickness), the insulation layer 21 (MgO of 0.7 nm thickness), the storage layer 20 (Fe.sub.10Co.sub.90 of 1 nm thickness, Gd.sub.22Co.sub.78 of 2 nm thickness), and the upper electrode 12 (Ta of 2 nm thickness/Ru of 5 nm thickness) are deposited sequentially using a magnetron sputtering method. As a subsequent process is the same as in the first embodiment, a description will be omitted.

(48) In the magnetoresistance element 1-2 according to the second embodiment, the compensated temperature T.sub.comp of the Tb.sub.24Fe.sub.53Co.sub.23 used in the pinned layer 220 is around 110 C. Consequently, in the same way as in the first embodiment, owing to the temperature change of the heat assist layer 28-2 depending on the size of the write current pulse, it is possible to write both a low resistance condition and a high resistance condition with a current of the same polarity.

Third Embodiment

(49) A description will be given of a third embodiment of the invention. The third embodiment uses a metal-insulator transition material in the heat assist layer 28-2 in a configuration of the magnetoresistance element 1-2 based on the second embodiment. The transition temperature of the heat assist layer 28-2 exists in a range of temperatures from room temperature to the compensated temperature of the storage layer 20.

(50) A description will be given of a principle whereby a write action using a unipolar current is stabilized in the magnetoresistance element 1-2 configured in such a way. FIG. 7 is a graph showing a change in the resistivity of the metal-insulator transition material used in the heat assist layer 28-2. The heretofore mentioned metal-insulator transition material indicates a kind of material whose resistivity increases sharply at a temperature equal to or higher than room temperature, as shown in FIG. 7. For example, (CrV).sub.2O.sub.3 is applied as this material. In the embodiment, a material used is such that a Cr substitution content x of the material (CrV).sub.2O.sub.3 given above as an example is taken to be in the region of x=0.06, and a transition temperature T.sub.T thereof is taken to be in the region of 90 C. Also, the compensated temperature T.sub.comp of the pinned layer 220 is taken to be approximately 110 C., and a relationship is such that T.sub.T<T.sub.comp.

(51) Firstly, when a write current is caused to flow, Joule heat is generated in the insulation layer 21. When the thickness of the insulation layer 21 is 1.0 nm, resistivity (RA) is up to 10 cm, and a resistance value (R) is 1.3 k. Consequently, when taking the write current to be 70 A, and the write current pulse width to be 10 ns, the element temperature rises 60 C. owing to the Joule heat, reaching 80 C. In this condition, the temperature of the pinned layer 220 is lower than the compensated temperature T.sub.comp, and a write action from a high resistance condition to a low resistance condition is realized.

(52) Also, as the element temperature exceeds the transition temperature (90 C.) of the heat assist layer 28-2 when taking the write current to be 75 A and the write current pulse width to be 10 ns, the resistivity of the heat assist layer 28-2 leaps by two digits. As a result of this, the amount of heat generated in the heat assist layer 28-2 increases sharply, and the element temperature rises suddenly to in the region of 130 C. Because of this, the element temperature is equal to or higher than the compensated temperature T.sub.comp of the pinned layer 220, and a write action from a low resistance condition to a high resistance condition is realized. As a large temperature change is induced with only a small increase in the current in this way, even when there is variation in the compensated temperatures of individual elements 1-2 manufactured, a stable write action is realized without taking too much of a current margin.

(53) Next, a description will be given of a fabrication method of the magnetoresistance element according to the third embodiment.

(54) Firstly, as shown in FIG. 5a, the drain region 24, the source region 25, the gate line 16, the contact portion 17, the word line 18, the lower electrode 14, and the insulation body 23A are formed on the silicon substrate 15 using a normal CMOS process. Next, as shown in FIG. 5b, the substrate is heated to 350 C., and the heat assist layer 28-2 (Cr.sub.0.012V.sub.1.988O.sub.3 of 2 nm thickness) is deposited using a magnetron sputtering method. Subsequently, the pinned layer 220 (Tb.sub.24Fe.sub.53Co.sub.23 of 5 nm thickness, Fe.sub.10Co.sub.90 of 1 nm thickness), the insulation layer 21 (MgO of 0.7 nm thickness), the storage layer 20 (Fe.sub.10Co.sub.90 of 1 nm thickness, Gd.sub.22Co.sub.78 of 2 nm thickness), and the upper electrode 12 (Ta of 2 nm thickness/Ru of 5 nm thickness) are deposited sequentially. As a subsequent process is the same as in the first embodiment, a description will be omitted.

(55) Herein, a metal-insulator transition material having a transition temperature in a temperature range of room temperature to in the region of 350 C., as does, for example, (CrV).sub.2O.sub.3, LaSrMnO, or the like, is appropriate as a material of the heat assist layer 28-2. This is because when the pinned layer 220 is heated to a temperature higher than 350 C., there is a danger of the rare earth-transition metal alloy included in the pinned layer 220 crystallizing.

(56) Also, even though no extremely sharp change in resistivity is exhibited at the transition temperature T.sub.T, as with these alloys, it is possible, even when using a PTC (positive temperature coefficient) material (having a positive temperature coefficient of resistance) whose resistivity increases owing to a temperature rise in a temperature range of room temperature to the compensated temperature, to stabilize a write action using a unipolar current according to the same principle. For example, LaSrCuO.sub.4, BaTiO.sub.3 doped with a third period element (for example, BaNaTiO.sub.3, or the like), YBa.sub.2Cu.sub.3O.sub.7, Sr.sub.2Cu.sub.3O.sub.5, LaSrCoO.sub.3, NaNbO.sub.3, BiFeO.sub.3, and the like, are known as this kind of material.

(57) When using the heretofore described PTC material, a kind of material whose resistivity always increases in the temperature range of room temperature to the compensated temperature may be used but, this not being indispensable, provided that the resistivity increases in a temperature range of in the region of 5 C. of the compensated temperature, it is sufficient for the heretofore described action. However, it is desirable that the change of resistance value in the range of 5 C. is 500 or more. For example, when the write current is reduced to around 510.sup.5 A/cm.sup.2, it can be calculated that at a resistance of 500 there is a contribution to temperature rise of approximately a little under 10 C. This is because, even when the variation of the composition of the rare earth-transition metal alloy in the pinned layer 220 in individual magnetoresistance elements 1-2 manufactured is kept to within 0.2%, the variation of the compensated temperature is estimated to be in the region of 7 to 8%, and it is considered that in the region of 10 C. is necessary as a margin.

(58) Of materials (V.sub.1-xCr.sub.x).sub.2O.sub.3 used as the heat assist layer 28-2, a material (Cr.sub.0.006V.sub.0.994).sub.2O.sub.3, wherein x=0.006, has a metal-insulator transition temperature of around 90 C., and the resistivity increases by two digits with this temperature as a borderline. When taking the current value of a write action from a high resistance condition to a low resistance condition to be 70 A, the element temperature is 80 C., as heretofore described. Also, when taking the current value of a write action from a low resistance condition to a high resistance condition to be 75 A, the element temperature is 130 C., and it is possible to secure a margin of 20 C. with respect to the compensated temperature. Imagining that there are no heat assist layer 28-2, a current of 95 A would be necessary in order for the element temperature to become 130 C. FIG. 8 shows an example of a relationship between the current caused to flow through the heat assist layer 28-2 and the temperature of the magnetoresistance element 1-2. In FIG. 8, the dotted line shows current-temperature characteristics when the heat assist layer 28-2 is formed of the normal resistive material used in the first and second embodiments, and the solid line shows current-temperature characteristics when the heat assist layer 28-2 is formed of the metal-insulator transition material. As shown in FIG. 8, when the metal-insulator transition material is used in the heat assist layer 28-2, the current value necessary in order to secure the same temperature margin drops from I.sub.1 to I.sub.1. In this way, according to the memory in the embodiment, it is possible to realize a stable write action, even when the current is low.

(59) Even when applying the material of the heat assist layer in the embodiment to the heat assist layer 28-1 of the first embodiment, it is possible to achieve the same benefit as in the embodiment.

Fourth Embodiment

(60) FIG. 9 shows a memory cell 8 using the magnetoresistance elements 1 (1-1 and 1-2) shown in FIG. 1 and FIG. 6, and FIG. 10 shows a non-volatile semiconductor storage device 10 including a cross-point type memory cell array formed by arraying memory cells 8.

(61) As already described, switching with a unipolar electrical pulse is possible with the magnetoresistance elements 1-1 and 1-2 of the invention. The memory cell 8 has a configuration wherein a rectifier element 9 (for example, a diode) acting as a selector switch is connected in series to the magnetoresistance element 1. Consequently, by disposing individual memory cells 8 in an array form, the cross-point type non-volatile semiconductor storage device 10 shown in FIG. 10 is formed.

(62) With regard to the manufacture of the individual memory cells 8, for example, it is possible to form the rectifier element 9 in advance on the silicon substrate 15 (FIG. 1), and to form the magnetoresistance element 1 in a portion above the rectifier element 9. Then, by applying an electrical pulse with a positive polarity from the storage layer 20 or 200 (refer to FIG. 1 and FIG. 6) side of the magnetoresistance element 1 in the memory cell 8, it is possible to cause the memory cell 8 to carry out an efficient switching.

(63) Meanwhile, a processing temperature necessary for fabricating the magnetoresistance element 1 is in the region of, or less than, the 350 C. necessary as an annealing temperature. Consequently, it does not happen that the performance of an electrical pulse supply transistor (for example, a MOSFET), or the cell selection switch rectifier element 9, formed in a portion below the magnetoresistance element 1 is impaired by the effect of the annealing temperature. It is also possible to increase the total memory capacity by stacking non-volatile semiconductor storage devices 10 three-dimensionally. In this case, the number of wires increases but, as the wire material can sufficiently withstand the annealing temperature of 350 C., there is no danger of the wires deteriorating because of the temperature.

(64) Next, referring to FIG. 10, a more detailed description will be given of the non-volatile semiconductor storage device 10 having a configuration acting as a cross-point type memory cell array. When contents of information to be stored are written into the non-volatile semiconductor storage device 10, lines among word lines WLi (i=1 to n) corresponding to words accessed are selected by a word line decoder 110, and a signal corresponding to data to be written into the lines of memory cells 8 connected to the word lines selected is applied from a bit line decoder 120 via bit lines BLi (i=1 to m) to the corresponding memory cells 8. Word lines of words not accessed are affected by an action of the rectifier element (diode) 9 in such a way that no current flows to the memory cells 8. That is, only word lines of words accessed are connected to a ground. Then, a signal such that a set action or reset action is realized is applied from the bit line decoder 120, in accordance with data needing to be written, between the bit lines and word lines connected to the accessed memory cells 8.

(65) Next, a description will be given of a read action. The bit line decoder 120 includes current detection units (not shown) provided corresponding to each bit line. When reading, in the same way as when writing, accessed word lines are selected by the word line decoder 110, and current flowing from each bit line into the word lines is detected by the current detection units. Therefore, the bit line decoder 120 detects voltage values in accordance with the resistance of the memory cell 8 corresponding to each bit line, and reads the condition of the memory cells 8 based on the voltage values.

(66) Heretofore, a description has been given of embodiments of the invention but, the invention not being limited to the embodiments already described, various kinds of alteration, change, and combination are possible based on the technological idea of the invention.

(67) For example, in the first embodiment, the heat assist layer 28-1 is deposited on the storage layer 200 in FIG. 1, but this is not limiting. That is, provided that the heat assist layer 28-1 can heat the storage layer 200, it can be formed in any position in a magnetic tunnel junction portion 13. For example, the heat assist layer 28-1 may be interposed between the lower electrode 14 and pinned layer 22. The same also applies to the second embodiment.

DESCRIPTION OF REFERENCE NUMERALS AND SIGNS

(68) 1, 1-1, 1-2 Magnetoresistance element 8 Memory cell 9 Diode 10, 10-1, 10-2 Non-volatile semiconductor storage device 11 Bit line 12 Upper electrode 13 Magnetic tunnel junction (MTJ) portion 14 Lower electrode 15 Silicon substrate 16 Gate line 17 Contact portion 18 Word line 20, 200 Storage layer (second magnetic body) 21 Insulation layer 22, 220 Pinned layer (first magnetic body) 23, 23A, 23B Interlayer insulation film 24 Drain region 25 Source region 28-1, 28-2 Heat assist layer 51 Resist portion 52 Contact hole 102, 102A Magnetization direction 110 Word line decoder 120 Bit line decoder