Controlled Active Resistance
20200266815 ยท 2020-08-20
Inventors
Cpc classification
H03F2203/45602
ELECTRICITY
H03F2203/45528
ELECTRICITY
H03F2203/45616
ELECTRICITY
H03F2203/45524
ELECTRICITY
H03F2203/45536
ELECTRICITY
International classification
Abstract
A controlled active resistance. The active resistance is implemented on an integrated circuit. In some embodiments, the active resistance includes a MOSFET. In alternate embodiments, the active resistance includes a MOSFET and a resistor. The control for the active resistance includes a reference resistor and an operational amplifier. The control for the active resistance further includes two current sources: i) a current source producing a current that is proportional to absolute temperature, and ii) another current source that is produced by a bandgap voltage reference. In one aspect, the active resistance generates an effective resistance that is proportional to thermal voltage. In another aspect, the active resistance generates an effective resistance that is proportional to inverse of the thermal voltage. In an alternate aspect, the current sources have various dependencies, and the active resistance generates an effective resistance that is proportional to those dependencies.
Claims
1. A method of generating a controlled active resistance, the method comprising: providing a reference resistor; providing an active device; providing an operational amplifier; providing a first current source proportional to a characteristic and a second current source independent of the characteristic; and using the operational amplifier to force a voltage across the reference resistor onto the active device, thereby generating a controlled total active resistance such that the controlled total active resistance is proportional to the characteristic by connecting the first current source to a feedback node of the active device and connecting the second current source to the reference resistor.
2. The method of claim 1, wherein the active device comprises a MOSFET.
3. The method of claim 2, wherein the active device further comprises a resistive element.
4. (canceled)
5. A circuital arrangement, comprising: a first resistive element; a first active element; an operational amplifier, having a first input connected to the first resistive element, a second input connected to the first active element, and an output connected to the first active element; and a first current source proportional to a characteristic and connected to the first active element and a second current source independent of the characteristic and connected to the first resistive element, wherein the first resistive element, the operational amplifier, the first current source and the second current source are configured, in combination, to control the first active element, and cause the first active element to act as an active resistance proportional to the characteristic.
6. A ground referenced active resistance, comprising: the circuital arrangement of claim 5; a second active element, wherein the output of the operational amplifier is also connected to the second active element.
7. The ground referenced active resistance of claim 6, further comprising a third active element, wherein the output of the operational amplifier is also connected to the third active element.
8. A floating active resistance circuit, comprising: a first resistive element; a first active element having an input terminal, a control terminal and an output terminal; a second active element having an input terminal, a control terminal and an output terminal; a first operational amplifier, having a first input connected to the first resistive element, a second input connected to the input terminal of the first active element, and an output connected to the control terminal of the first active element; a second operational amplifier, having a first input connected to a reference voltage, a second input connected to the first resistive element and the output terminal of the first active element, and an output connected to the control terminal of the second active element; and a first current source connected to the first active element and a second current source connected to the first resistive element, wherein the first resistive element, the first operational amplifier, the first current source and the second current source are configured, in combination, to control the first active element, and cause the first active element to act as an active resistance, and the second operational amplifier and the second active element are configured to create a floating node for the active resistance.
9. The floating active resistance circuit of claim 8, further comprising one or more active resistances, wherein the one or more active resistances are controlled by the output of the first operational amplifier.
10. (canceled)
11. The circuital arrangement according to claim 5, wherein the characteristic is absolute temperature.
12. The circuital arrangement according to claim 5, wherein the first active element is a MOSFET.
13. The circuital arrangement according to claim 5, wherein the first active element further comprises a second resistive element.
14. The circuital arrangement according to claim 13, wherein the first resistive element is connected to ground.
15. The circuital arrangement according to claim 13, wherein the first resistive element is connected to a common mode voltage.
16. The floating active resistance circuit of claim 9, wherein the one or more active resistance includes at least one MOSFET.
17. The ground referenced active resistance of claim 6, wherein the second active element is a MOSFET.
18. The ground referenced active resistance of claim 6, wherein the second active element further comprises a second resistive element.
19. The floating active resistance of claim 8, wherein the first active element is a MOSFET.
20. The floating active resistance of claim 8, wherein the first active element further comprises a second resistive element.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The disclosed apparatus, in accordance with one or more various embodiments, are described with reference to the following figures. The drawings are provided for purposes of illustration only and merely depict examples of some embodiments of the disclosed method and apparatus. These drawings are provided to facilitate the reader's understanding of the disclosed method and apparatus. They should not be considered to limit the breadth, scope, or applicability of the claimed invention. It should be noted that for clarity and ease of illustration these drawings are not necessarily made to scale.
[0015]
[0016]
[0017]
[0018]
[0019]
[0020]
[0021] Like reference numbers and designations in the various drawings indicate like elements.
DEFINITIONS
[0022] The term thermal voltage as used throughout the present disclosure will be used to mean a voltage produced within a p-n junction due to the action of temperature. Thermal voltage depends on absolute temperature and can be given by:
V.sub.T=(k.Math.T)/q
where: [0023] V.sub.T=Thermal Voltage [0024] k=Boltzmann's constant [0025] T=Temperature in Kelvin [0026] q=elementary charge (1.60210.sup.19 Coulomb)
The terms resistor, resistance, and resistive element will be used interchangeably throughout the present disclosure to indicate two-terminal electrical component that implements electrical resistance as a circuit element.
The terms active resistance and active resistor will be used throughout the present disclosure to mean compound elements within an electrical circuit that behave as a resistor, but whose behavior is controlled by another active element such as an operational amplifier, as distinguished from a passive resistor, which is an element whose behavior is purely based on its own characteristics and not controlled by another element.
DETAILED DESCRIPTION
[0027]
[0028] As shown in
After substituting terms for I.sub.PTAT and I.sub.REF:
where k is a current scalar out of a bandgap reference generator, N is the current density ratio of diodes in the bandgap reference generator, R.sub.BG is the internal resistance across the V.sub.PTAT within the bandgap reference generator, V.sub.bg is the voltage generated by the bandgap reference generator, and Vbg/R1 is the I.sub.REF current.
As can be seen in Eq. 2, R.sub.SUM varies directly with V.sub.T. I.sub.PTAT and I.sub.REF may be chosen such that a unity gain factor can be attained at any temperature. In some examples, gain factor varies from 1.0 to 1.6 over temperatures of 40 C to 100 C. It is not required that R.sub.SUM 114 include a passive resistor 110; rather, R.sub.SUM 114 could comprise only of an active device. In the example shown in
[0029] In a further embodiment of the V.sub.T-dependent resistor, the two current sources in the V.sub.T-dependent resistor schematic can be swapped, so that constant current I.sub.REF is driven into the input of the OpAmp 106, generating a voltage V.sub.REF. The I.sub.PTAT is driven into the feedback node of the OpAmp. Therefore, R.sub.SUM will vary with 1/V.sub.T.
[0030] In some embodiments of the V.sub.T-dependent resistor, current sources with various dependencies, which are not just dependent on temperature can be used. As an example, the current sources could depend on a voltage, or on a device parameter such as threshold voltage of that device, or on any other variable that could create a dependent current source.
[0031] In yet another embodiment of the V.sub.T-dependent resistor, various current sources can be summed together at a node. For example, different amounts of a bandgap referenced current (which is constant as a function of temperature), and current that is proportional to the absolute temperature (which varies with temperature), can be summed in order to create any arbitrary slope for R.sub.SUM as a function of temperature. It will be understood by those skilled in the art that an active resistor can be created that is dependent on any variable or combination of variable, if the variables are expressed in the form of a current. It is not required that the active resistor Rsum (114) include a passive resistor. Rsum can include an active device and a resistor or just an active device.
[0032]
[0033] This external circuit includes an active resistor 216 and block 218. The OpAmp 206 which drives the active resistor 214, also drives the device in the replica resistor 216. Block 218 is a circuit that makes use of the replica resistor 216. Used in this manner, the external circuit can detect a change in the active resistor 214 as it varies with V.sub.T (or varies with any parameter contained in the input current profile generating the active resistor).
[0034] In
[0035]
[0036] The active resistors 320 and 324 are replicas of active resistor 314. Further, active resistors 320 and 324, which form the input to the OpAmp 330, are matching. The input voltage into the active resistor 320 is V.sub.M and the input voltage into active resistor 324 is V.sub.P. V.sub.M and V.sub.P are voltages across diodes 416 and 410, respectively, in later introduced
[0037] In
The term Vt*ln(Iin/Iref) is the output of the voltage-to-current-to-voltage converter and is the (vpvm) input signal to the diff amp. Diode ideality factor is ignored, since it is also a constant. It can be seen from Eq. 3 that the thermal voltage is in the numerator and the denominator, therefore it will drop out of the equation. By using only one type of resistor (e.g. polysilicon) for the resistors in Eq. 3, one can minimize variations due to manufacturing processes and temperature variations. Resistor temperature coefficients can now be assumed to be present, since in previous section they were temporarily ignored. The largest remaining errors will be due to random mismatch of the added circuitry, which can be managed by designing low offset OpAmps, and designing low offset current mirrors. It should also be noted that the voltage at node 354 is a buffered version of the voltage at node 356. Furthermore, OAP is buffered instead of OAM, in order to avoid interaction from the difference amplifier 330 feedback loop.
[0038]
[0039] The operation of the V-I-V converter schematic in
where again the diode ideality factor is ignored because it is a constant. This difference in voltage is driven into the difference amplifier 450 in
V.sub.OUT=R2/R1.Math.(VPVM)Eq. 5
[0040] The constant gain of the difference amplifier 450 causes its output voltage to vary by upwards of 60% over a temperature range of 40 C to 100 C. The reason for this wide variation in the output of the difference amplifier 450 is that the input voltage to the difference amplifier is a function of V.sub.T, as can be seen in Eq. 4. V.sub.T depends on absolute temperature, thus, the input voltage to the difference amplifier 450 depends directly on absolute temperature, and given a constant gain of the difference amplifier, the output voltage of the difference amplifier varies directly with absolute temperature.
[0041] The difference in resistor temperature coefficients between different types of resistors used with difference amplifier 450 can be exploited in an effort to maintain a constant voltage at the output of the difference amplifier. Resistors 452 and 454 have equal values R1 and are fabricated from the same semiconductor material, whereas resistors 456 and 458 have equal values R2, and are fabricated from another semiconductor material. These semiconductor materials could, for example, be polysilicon or active diffusion. R1 and R2 have different coefficients of temperature. The ratio of R2 to R1 can be used in an effort to minimize the ratio's temperature dependence; however, semiconductor processing variations can cause the nominal values or the difference in the rate of change of the resistances R1 and R2 as a function of temperature to change significantly due to the fact that different types of resistors, such as resistors fabricated out of polysilicon or active diffusion, are uncorrelated and fluctuate differently with process variations.
[0042] On the other hand,
[0043] By replacing passive resistors with active resistors, Equations 2, 4 and 5 can be combined to derive the output voltage of difference amplifier 500, which is now given by:
It can be seen from Equation 6 that V.sub.T is in the numerator and the denominator, therefore it will drop out of Equation 6. By using only one type of resistor for the resistors in Equation 6, manufacturing process and temperature variations can be minimized.
[0044] It will be understood by those skilled in the art that the principle of an active resistor can be used in any OpAmp circuit with resistors used to set the gain and/or set the pole/zero stability compensation. This principle can be used in active filters, or temperature sensors, among others.
[0045] As should be readily apparent to one of ordinary skill in the art, various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice and various embodiments of the invention may be implemented in any suitable IC technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, the invention may be implemented in other transistor technologies such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. Fabrication in CMOS on SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
[0046] Voltage levels may be adjusted or voltage and/or logic signal polarities reversed depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially stacking components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functional without significantly altering the functionality of the disclosed circuits.
[0047] The term MOSFET, as used in this disclosure, means any field effect transistor (FET) with an insulated gate and comprising a metal or metal-like, insulator, and semiconductor structure. The terms metal or metal-like include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), insulator includes at least one insulating material (such as silicon oxide or other dielectric material), and semiconductor includes at least one semiconductor material.
[0048] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion.
[0049] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).