AMPLIFIER CIRCUIT, CORRESPONDING SYSTEM, VEHICLE AND METHOD

Abstract

A cascade of amplifier stages has a differential input and a differential output. The cascade of amplifier stages includes at least one differential amplifier circuit including first and second transistors, at least one of the first and second transistors having a control terminal and a body terminal. A mismatch between the first and second transistors generates an input offset. A feedback network couples the differential output to the body terminal in order to cancel the input offset. The feedback network includes a low-pass filter and a differential amplifier stage.

Claims

1. A circuit, comprising: a cascade of amplifier stages having a differential input and a differential output, each amplifier stage comprising at least one differential amplifier circuit comprising first and second transistors, wherein the first and second transistors in the at least one differential amplifier circuit: a) comprise at least one transistor having a control terminal and a body terminal, and b) have a mismatch therebetween which generates an input offset; and a feedback network comprising a low-pass filter and a differential amplifier stage; wherein the feedback network forms a feedback loop for a signal at said differential output; wherein the differential amplifier stage in the feedback network receives the signal at said differential output as input and is coupled to the body terminal of the at least one transistor to bias the body terminal; and wherein the low-pass filter comprises: a first resistor having a first terminal coupled to a first node of the differential output and a second terminal coupled to a first input of the differential amplifier stage, a second resistor having a first terminal coupled to a second node of the differential output and a second terminal coupled to a second input of the differential amplifier stage, and a capacitor having a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to the second terminal of the second resistor.

2. The circuit of claim 1, wherein: the first transistor and the second transistor have respective control terminals and body terminals, and the differential amplifier stage in the feedback network is coupled to the body terminals of the first and second transistors.

3. The circuit of claim 1, wherein the feedback loop formed by the feedback network across the cascade of amplifier stages has a closed loop gain value configured to zero-out the input offset.

4. The circuit of claim 1, wherein the at least one transistor of the first and second transistors having the control terminal and the body terminal is a FD-SOI transistor.

5. The circuit of claim 1, wherein the at least one transistor of the first and second transistors having the control terminal and the body terminal is a 28 nm technology FD-SOI transistor.

6. A system, comprising: at least one antenna, and at least one receiver or transmitter circuit arrangement, coupled to the at least one antenna and comprising at least one amplifier circuit, the at least one amplifier circuit comprising: a cascade of amplifier stages having a differential input and a differential output, each amplifier stage comprising at least one differential amplifier circuit comprising first and second transistors, wherein the first and second transistors in the at least one differential amplifier circuit: a) comprise at least one transistor having a control terminal and a body terminal, and b) have a mismatch therebetween which generates an input offset; and a feedback network comprising a low-pass filter and a differential amplifier stage; wherein the feedback network forms a feedback loop for a signal at said differential output; wherein the differential amplifier stage in the feedback network receives the signal at said differential output as input and is coupled to the body terminal of the at least one transistor to bias the body terminal; and wherein the low-pass filter comprises: a first resistor having a first terminal coupled to a first node of the differential output and a second terminal coupled to a first input of the differential amplifier stage, a second resistor having a first terminal coupled to a second node of the differential output and a second terminal coupled to a second input of the differential amplifier stage, and a capacitor having a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to the second terminal of the second resistor.

7. The system of claim 6, wherein the system is configured to define a transceiver.

8. The system of claim 6, wherein the system is configured to define a vehicular radar system.

9. The system of claim 6, wherein the at least one transistor of the first and second transistors having the control terminal and the body terminal is a FD-SOI transistor.

10. The system of claim 9, wherein the at least one transistor of the first and second transistors having the control terminal and the body terminal is a 28 nm technology FD-SOI transistor.

11. The system of claim 8, wherein the vehicular radar sensor system is a component of a vehicle.

12. A method, comprising: amplifying a differential input signal through a cascade of amplifier stages to generate a differential output signal; where at least one amplifier stage includes a differential amplifier circuit comprising a first and second transistors, at least one of the first and second transistors having a control terminal and body terminal, and wherein a mismatch between the first and second transistors generates an input offset; low-pass filtering the differential output signal to generate a filtered differential signal; differentially amplifying the filtered differential signal to generate a feedback control signal; applying the feedback control signal to the body terminal of said at least one of the first and second transistors varying a threshold voltage to vary a threshold voltage of said at least one of the first and second transistors and cancel the input offset.

13. The method of claim 12, further comprising selecting a closed loop gain value in order to zero-out said input offset.

14. A circuit, comprising: a cascade of amplifier stages having a differential input and a differential output, at least one of the cascade of amplifier stages comprising first and second transistors having control terminals and having body terminals, wherein the first and second transistors have a mismatch therebetween which generates an input offset; and a feedback network coupled between the differential output and the body terminals, the feedback network comprising a low-pass filter and a differential amplifier stage, the differential amplifier stage generating a control signal applied to the body terminal of the first transistor to cancel the input offset; wherein the low-pass filter comprises: a first resistor having a first terminal coupled to a first node of the differential output and a second terminal coupled to a first input of the differential amplifier stage, a second resistor having a first terminal coupled to a second node of the differential output and a second terminal coupled to a second input of the differential amplifier stage, and a capacitor having a first terminal directly connected to the second terminal of the first resistor and a second terminal directly connected to the second terminal of the second resistor.

15. The circuit of claim 14, wherein the first and second transistors are coupled in parallel between a load and a bias current generator.

16. The circuit of claim 14, wherein a feedback loop formed by the feedback network across the cascade of amplifier stages has a closed loop gain value configured to zero-out the input offset.

17. The circuit of claim 14, wherein the first and second transistors are FD-SOI transistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] One or more embodiments will now be described, by way of non-limiting example only, with reference to the annexed Figures, wherein:

[0046] FIG. 1 shows a model of an amplifier circuit block;

[0047] FIG. 2 shows a graphic representation of the voltage offset;

[0048] FIG. 3 is a diagram of an amplifier circuit;

[0049] FIG. 4 is exemplary of a two-gated transistor model;

[0050] FIG. 5 is a diagram of an amplifier circuit; and

[0051] FIG. 6 shows a receiver arrangement and vehicle.

DETAILED DESCRIPTION

[0052] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0053] Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.

[0054] Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0055] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0056] The Inventors have observed that employing a negative feedback loop may be suitable for use in one or more embodiments. Specifically, the output variable of the system is read by the feedback network, which acts by modifying the input of the system. It may continuously calculate an error value as the difference between a target value and a measured value, and apply a respective correction, for example, automatically apply accurate and responsive correction to a control function.

[0057] As exemplified in FIG. 3, in one or more embodiments an amplifier circuit 30 with an offset voltage compensation feedback loop may comprise: [0058] an input node 31, [0059] a cascade of amplifier stages 32, 34, 36, comprising a first amplifier stage 32, a second amplifier stage 34, and a third amplifier stage 36, [0060] an output node 37, [0061] an Offset Compensation (OC) stage 38, which may comprise a low-pass filter (LPF) stage 380 and a feedback amplifier stage 390, as discussed in the following.

[0062] For the sake of simplicity, the cascade of amplifier stage 32, 34, 36 discussed in the following comprises three amplifiers in the example considered, it being otherwise understood that such a quantity is purely exemplary and in no-way limiting.

[0063] In one or more embodiments, the first amplifier stage may comprise one or more transistors which may be operated with two control terminals.

[0064] Typically, a transistor is modeled or represented as having three terminals (for example, a gate, a drain and a source, although other types of transistors may use different terms) and those inputs are coupled to other nodes in the system.

[0065] One or more transistors as per the present disclosure may comprise a fourth terminal (for example, the body input, also referred to as back-gate or body terminal) which is coupled to a node in the system.

[0066] As exemplified in FIG. 4, a two-gated transistor 40 may comprise a front gate (or control terminal), for example, a gate control terminal G, and a back-gate (or body terminal) B, for example, a body control terminal B, which may be operated to perform so-called body biasing, for example, for power and speed scaling, facilitating modification of the transistor threshold voltages.

[0067] Body biasing is beneficial in that it enables trade off digital circuit performance in exchange for control of the threshold voltage, for example, by about 80 mV through a variation of the voltage of 1 V applied to the back-gate B.

[0068] Body biasing may facilitate employment of smaller transistors in the circuit 30, which may make it faster and reduce its area footprint.

[0069] For instance, one or more Fully Depleted Silicon-On-Insulator (FD-SOI) MOSFET transistors, for example, 28 nm CMOS technology transistors, may be employed in the circuit 30.

[0070] As exemplified in FIG. 4, a semiconductor device (MOSFET) such as a SOI MOSFET 40 may comprise an insulator layer 44, which may be a buried oxide (BOX) layer formed in a semiconductor substrate, and a semiconductor layer 42, for example, of silicon Si or germanium Ge, formed thereon.

[0071] In the considered example, the four pins or terminals of the transistor in diagram 40 are source S, front gate (or gate or control terminal) G, drain D and body terminal (or back-gate) B. A threshold voltage value to turn on a signal path between drain D and source S terminals may be indicated as V.sub.th.

[0072] For an n-type FDSOI MOSFET as exemplified in FIG. 4, the sandwiched p-type film 42 between the gate oxide (GOX) and buried oxide (BOX) may be very thin, so that the depletion region covers the whole p-region film. In the considered example, front gate (or control terminal) G may support fewer depletion charges than back gate B so an increase in inversion charges occurs, for example, resulting in higher switching speeds.

[0073] In one or more embodiments, the limitation of the depletion charge by the BOX may induce a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing, for example, facilitating FDSOI MOSFETs to work at lower gate bias resulting in lower power operation.

[0074] In one or more embodiments, the employ of FDSOI MOSFET technology may reduce drawbacks with respect to bulk MOSFETs, for instance threshold voltage roll off, since source and drain electric fields can't interfere as a result of the BOX layer.

[0075] In any case, any other type of transistor technology having a front control terminal and a bulk/body terminal for controlling the threshold voltage may be employed, for example MOSFETs, FETs, etc.

[0076] In one or more embodiments as exemplified in FIG. 5, the first amplifier stage 32 in the cascade of amplifier stages 32, 34, 36 may comprise: [0077] a first N1 and second N2 transistor, having respective gate G.sub.N1, G.sub.N2 and body B.sub.N1, B.sub.N2 terminals and coupled as a differential pair having input nodes V.sub.IN+, V.sub.IN at respective gate nodes G.sub.N1, G.sub.N2 and output nodes V.sub.O1, V.sub.O2 at respective drain nodes, [0078] a bias current generator I.sub.BIAS coupled to common source nodes in the first and second transistors N1, N2, and [0079] a load 328 coupled to respective drain nodes in the first and second transistors N1, N2, for example, comprising, for example, a resistive load to adjust an optimum bias voltage in the differential coupled transistors N1, N2.

[0080] In one or more embodiments as exemplified in FIG. 5, the low-pass LP filter 380 in the offset compensation circuit block 38 may comprise a capacitor C coupled in series between a pair of resistors, R.sub.A, R.sub.B.

[0081] In one or more embodiments, the feedback amplifier stage in the offset compensation stage 38 may comprise a differential amplifier stage 390 having a non-inverting input 390a, an inverting input 390b, an inverting output node 390c and an inverting output node 390d, wherein output nodes are coupled to respective back-gate nodes B.sub.N1, B.sub.N2 in respective transistors N1, N2 in the differential pair N1, N2 in the first amplifier stage 32. For instance: [0082] the inverting output node 390c may be coupled to the back-gate node B.sub.N1 in the first transistor N1, and [0083] the non-inverting output node 390d may be coupled to the back-gate node B.sub.N2 in the second transistor N2.

[0084] As mentioned, the Offset Compensator (OC) circuit block 38 may be arranged in a negative feedback loop between output V.sub.OUT of the amplifier cascade 32, 34, 36 and nodes input V.sub.N+, V.sub.IN of the differential pair N1, N2 in the first amplifier stage 32 in the amplifier cascade.

[0085] As a result, voltage correction may be provided to the transistors N1, N2 of the input differential amplifier by means of the output (offset) voltage acquired by the OC block 38.

[0086] Consequently, offset compensation 38 may be performed the to properly induce a variation of threshold voltage V.sub.th of the two transistors N1, N2 of the input differential stage 32 by exploiting the body effect in transistors in the differential coupled transistors N1, N2, thus cancelling the input offset voltage V.sub.os as discussed in the following.

[0087] The body effect upon transistor signal path channel can be described as a modification of the threshold voltage V.sub.th which may be expressed as:

V.sub.th=V.sub.th0+({square root over (|.sub.B+V.sub.SB|)}{square root over (|2.sub.B|)})

[0088] where: [0089] V.sub.th is the threshold voltage with substrate bias present, [0090] V.sub.th0 is the zero-V.sub.SB value of threshold voltage (V.sub.SB indicating source to body voltage),

[00001]$-=\frac{\sqrt{2.Math..Math.q.Math..Math.N_A.Math.{\mathrm{.Math.}}_{\mathrm{Si}}}}{C_{\mathrm{OX}}}.Math..Math.\mathrm{is}.Math..Math.\mathrm{the}.Math..Math.\mathrm{body}.Math..Math.\mathrm{effect}.Math..Math.\mathrm{parameter},$

and [0091] 2.sub.B is the approximate potential drop between surface and bulk across the depletion layer when V.sub.SB=0 and the gate bias is sufficient to ensure that a channel is present.

[0092] For instance, the threshold voltage of a MOSFET may be affected by the voltage which is applied to the body/back contact B. The voltage difference between the source and the bulk, V.sub.SB changes the width of the depletion layer and therefore also the voltage across the oxide due to the change of the charge in the depletion region, resulting in a difference in threshold voltage which equals the difference in charge in the depletion region divided by the oxide capacitance.

[0093] In one or more embodiments as exemplified in FIG. 5, amplifier stage 32, 34, 36 may have a respective gain value associated to the stage, for instance: [0094] a first gain value A.sub.1 for the first amplifier stage 32, [0095] a second gain value A.sub.2 for the second amplifier stage 34, [0096] a third gain value A.sub.3 for the third amplifier stage 36, and so on.

[0097] Thus, a total gain T may be obtained for the amplifiers cascade which may be expressed as the product of respective gains, for example: T=A.sub.1*A.sub.2*A.sub.3.

[0098] If the input voltage offset Vos is present at the input nodes V.sub.N+, V.sub.IN, this offset may be amplified by the total gain T providing an (output) offset voltage V.sub.os having approximately a value of, for example: V.sub.os=T*V.sub.os.

[0099] In one or more embodiments, as a result of a negative closed loop via the feedback amplification stage 380, the offset voltage at the input V.sub.os can be reduced to a negligible value, for example, by modifying the total loop gain from the open loop value T to a closed loop value T taking into account also a respective gain value of the amplifier in the feedback branch 380, for instance: T=T/(1+).

[0100] Said otherwise, the offset compensator 38 exploits the (output) offset voltage Vos' to control the MOS transistors N1, N2 of the first differential amplifier 32 of the VGA 30.

[0101] In one or more embodiments, the offset compensator 38 may use the Low-Pass Filter (LPF) 380 to safeguard the lower band of the VGA amplifier/regulator 30.

[0102] In one or more embodiments, the offset compensator 38 may use the LPF 380 to provide a suitable closed loop gain, for example, when the total gain T given by the main gain chain 32, 34, 36 is very high.

[0103] It is noted that the proposed circuit can be integrated in any circuit/functional block that suffers from voltage offset, not only in a VGA but also in other contexts such as operational amplifiers, regulators, etc.

[0104] In one or more embodiments, different transistor technologies can be applied, for example CMOS, FET, MOSFET, etc.

[0105] One or more embodiments as exemplified in FIG. 6, may be employed to cancel the offset voltage Vos from a variable-gain amplifier (VGA) circuit 110, 112 used in the baseband of a radar receiver 122 or transmitter 120, for example, a 77 GHz CMOS radar transceiver 140.

[0106] In one or more embodiments the system 100 may have further processing stages 200 and communication interfaces 500 and a battery 400 to provide power supply circuits in the system 100.

[0107] For instance, the radar sensor system 100 in the vehicle V may provide support to a vehicle driver, for example, via an Automated Driving Assistance System ADAS capable to take control over the vehicle, in detecting people crossing the road during the night or in adverse eye visibility conditions, hence facilitating a reduction in the number of road accidents.

[0108] For instance, in such an application context, one or more embodiments may advantageously avoid potential saturation of the output level even with a small input offset voltage.

[0109] For instance, one or more embodiments may employ 28 nm FDSOI CMOS technology, facilitating voltage to control of the threshold voltage V.sub.th through the body terminal (or back-gate), for example, by about 80 mV/V (1 mV=1 milliVolt=10.sup.3 Volt).

[0110] It will be otherwise understood that the various individual implementing options exemplified throughout the figures accompanying this description are not necessarily intended to be adopted in the same combinations exemplified in the figures. One or more embodiments may thus adopt these (otherwise non-mandatory) options individually and/or in different combinations with respect to the combination exemplified in the accompanying figures.

[0111] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection. The extent of protection is defined by the annexed claims.