Low gate-count encoding algorithm and hardware of flexible rate GLDPC ECC

Abstract

Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.

Claims

1. A storage system, comprising: a storage device configured to store a plurality of generalized low-density parity-check (GLDPC) codewords; at least one processor configured to: obtain information bits, and place the information bits in a first bit chunk included in a first arrangement of a GLDPC codeword; set balance bits included in the first bit chunk to zero; encode the information bits and the balance bits using a systematic code to generate first parity bits, and place the first parity bits in the first bit chunk; permute the first bit chunk to generate first permutated bits, and place the first permutated bits in a second bit chunk included in a second arrangement of the GLDPC codeword; encode the first permutated bits using the systematic code to generate second parity bits, and place the second parity bits in a third bit chunk included in the second arrangement; permute a first portion of the third bit chunk to generate second permutated bits, and place the second permutated bits in a fourth bit chunk included in the first arrangement; encode the second permutated bits using the systematic code to generate third parity bits, and place the third parity bits in a fifth bit chunk included in the first arrangement; permute a second portion of the third bit chunk to generate fourth permutated bits; adjust the first bit chunk by adjusting the balance bits based on a comparison between the fourth bit chunk and the fourth permutated bits, and adjust the fourth bit chunk and the fifth bit chunk based on the adjusted first bit chunk; obtain the GLDPC codeword based on the adjusted first bit chunk, the adjusted fourth bit chunk, and the adjusted fifth bit chunk; and store the GLDPC codeword in the storage device.

2. The storage system of claim 1, wherein a bijective mapping exists between the first arrangement and the second arrangement, and wherein within the bijective mapping, bits of the first bit chunk are mapped exclusively to bits of the second bit chunk, bits of the fourth bit chunk are mapped exclusively to bits of the first portion of the third bit chunk, and bits of the fifth bit chunk are mapped exclusively to bits of the second portion of the third bit chunk.

3. The storage system of claim 1, wherein the first arrangement comprises a first plurality of rows and the second arrangement comprises a second plurality of rows, and wherein a number of the first plurality of rows is different from a number of the second plurality of rows.

4. The storage system of claim 3, wherein each row of the first plurality of rows and the second plurality of rows comprises a codeword of the systematic code, and wherein the systematic code comprises at least one from among a Reed-Muller code, a Hadamard code, a Bose-Chaudhuri-Hocquenghem code, and a Hamming code.

5. The storage system of claim 1, wherein the adjusting of the balance bits comprises: determining a difference between the fourth bit chunk and the fourth permutated bits; and obtaining adjusted balance bits by multiplying the difference by a first balancing matrix.

6. The storage system of claim 5, wherein the first parity bits include parity balance bits corresponding to the balance bits, and wherein the adjusting of the first bit chunk comprises: adding the adjusted balance bits to the first bit chunk; encoding the adjusted balance bits using the systematic code to generate fourth parity bits; and adjusting the parity balance bits by adding the fourth parity bits.

7. The storage system of claim 6, wherein the adjusting of the fourth bit chunk and the fifth bit chunk comprises: multiplying the adjusted balance bits and the adjusted balance parity bits by a second balancing matrix; and adding a result of the multiplying to the fourth bit chunk and the fifth bit chunk.

8. A device for encoding information bits for storage in a storage device, the device comprising: a memory interface configured to communicate with the storage device; and at least one processor configured to: encode information bits and balance bits using a first coding scheme to obtain a first bit chunk included in a first arrangement of a codeword corresponding to a second coding scheme; permute the first bit chunk to obtain a second bit chunk included in a second arrangement of the codeword corresponding to the second coding scheme; encode bits of the second bit chunk using the first coding scheme to obtain a third bit chunk included in the second arrangement; permute a first portion of the third bit chunk to obtain a fourth bit chunk included in the first arrangement, and encode bits of the fourth bit chunk using the first coding scheme to obtain a fifth bit chunk included in the first arrangement; permute a second portion of the third bit chunk, and adjust the balance bits based on a comparison between the fifth bit chunk and the permutated second portion of the third bit chunk; adjust the first arrangement based on the adjusted balance bits, and obtain the codeword corresponding to the second coding scheme based on the adjusted first arrangement; and control the memory interface to transmit the obtained codeword to the storage device.

9. The device of claim 8, wherein the first coding scheme comprises at least one from among a Reed-Muller coding scheme, a Hadamard coding scheme, a Bose-Chaudhuri-Hocquenghem coding scheme, and a Hamming coding scheme, and wherein the second coding scheme comprises a GLDPC coding scheme.

10. The device of claim 8, wherein a bijective mapping exists between the first arrangement and the second arrangement, and wherein within the bijective mapping, bits of the first bit chunk are mapped exclusively to bits of the second bit chunk, bits of the fourth bit chunk are mapped exclusively to bits of the first portion of the third bit chunk, and bits of the fifth bit chunk are mapped exclusively to bits of the second portion of the third bit chunk.

11. The device of claim 8, wherein the first arrangement comprises a first plurality of rows and the second arrangement comprises a second plurality of rows, and wherein a number of the first plurality of rows is different from a number of the second plurality of rows.

12. The device of claim 11, wherein each row of the first plurality of rows and the second plurality of rows comprises a codeword corresponding to the first coding scheme.

13. The device of claim 8, wherein the adjusting of the balance bits comprises: determining a difference between the fourth bit chunk and the permutated second portion of the third bit chunk; and obtaining adjusted balance bits by multiplying the difference by a first balancing matrix.

14. The device of claim 13, wherein the first bit chunk includes parity balance bits corresponding to the balance bits, and wherein the adjusting of the first arrangement comprises: adding the adjusted balance bits to the first bit chunk; encoding the adjusted balance bits using the first coding scheme to generate second parity bits; and adjusting the parity balance bits by adding the second parity bits.

15. The device of claim 14, wherein the adjusting of the first arrangement further comprises: multiplying the adjusted balance bits and the adjusted parity balance bits by a second balancing matrix; and adding a result of the multiplying to the fourth bit chunk and the fifth bit chunk.

16. A method of controlling a storage system, the method being executed by at least one processor and comprising: obtaining information bits, and placing the information bits in a first bit chunk included in a first arrangement of a generalized low-density parity-check (GLDPC) codeword; setting balance bits included in the first bit chunk to zero; encoding the information bits and the balance bits using a systematic code to generate first parity bits, and placing the first parity bits in the first bit chunk; permuting the first bit chunk to generate first permutated bits, and placing the first permutated bits in a second bit chunk included in a second arrangement of the GLDPC codeword; encoding the first permutated bits using the systematic code to generate second parity bits, and placing the second parity bits in a third bit chunk included in the second arrangement; permuting a first portion of the third bit chunk to generate second permutated bits, and placing the second permutated bits in a fourth bit chunk included in the first arrangement; encoding the second permutated bits using the systematic code to generate third parity bits, and placing the third parity bits in a fifth bit chunk included in the first arrangement; permuting a second portion of the third bit chunk to generate fourth permutated bits; adjusting the first bit chunk by adjusting the balance bits based on a comparison between the fourth bit chunk and the fourth permutated bits, and adjusting the fourth bit chunk and the fifth bit chunk based on the adjusted first bit chunk; obtaining the GLDPC codeword based on the adjusted first bit chunk, the adjusted fourth bit chunk, and the adjusted fifth bit chunk; and storing the GLDPC codeword in a storage device.

17. The method of claim 16, wherein a bijective mapping exists between the first arrangement and the second arrangement, and wherein within the bijective mapping, bits of the first bit chunk are mapped exclusively to bits of the second bit chunk, bits of the fourth bit chunk are mapped exclusively to bits of the first portion of the third bit chunk, and bits of the fifth bit chunk are mapped exclusively to bits of the second portion of the third bit chunk.

18. The method of claim 16, wherein the first arrangement comprises a first plurality of rows and the second arrangement comprises a second plurality of rows, and wherein a number of the first plurality of rows is different from a number of the second plurality of rows.

19. The method of claim 18, wherein each row of the first plurality of rows and the second plurality of rows comprises a codeword of the systematic code, and wherein the systematic code comprises at least one from among a Reed-Muller code, a Hadamard code, a Bose-Chaudhuri-Hocquenghem code, and a Hamming code.

20. The method of claim 16, wherein the adjusting of the balance bits comprises: determining a difference between the fourth bit chunk and the fourth permutated bits; and obtaining adjusted balance bits by multiplying the difference by a first balancing matrix.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of a memory system according to embodiments.

(2) FIG. 2 illustrates an example of a GLDPC codeword 200, according to embodiments.

(3) FIGS. 3A-3B and 4A-4B illustrate examples of partitioning schemes, according to embodiments.

(4) FIGS. 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13, and 14A-14B illustrate examples of a GLPDC codeword at various stages of an encoding process, according to embodiments.

(5) FIGS. 15A-15B are flowcharts of processes for controlling storage systems and devices, according to embodiments.

(6) FIG. 16 is a block diagram of computer system including a memory system according to embodiments.

(7) FIG. 17 is a block diagram of a memory card according to embodiments.

(8) FIG. 18 is a block diagram of a network system including a memory system according to embodiments.

DETAILED DESCRIPTION

(9) Embodiments of the present disclosure may relate to a low-complexity method of encoding a GLDPC codeword having supercodes, or arrangements, with a large number of degrees of freedom relative to related-art methods. As discussed above, many related-art GLDPC encoding procedures are burdened by high complexity or very restrictive constraints. Embodiments may relieve the constraints discussed above and enable encoding at practically any rate. This may permit integration of embodiments in products with low ECC redundancy, or high rates, for example embedded MultiMediaCard (eMMC) storage devices. In addition, embodiments may also permit the supercodes, or arrangements, to be of different sizes (s, n), relieving an equal size requirement, for example a requirement that n.sub.1=n.sub.2, where n.sub.1 represents a number of. This may allow a belief propagation (BP) decoder check node to be strengthened in cases where the equal size requirement would leave it weak. Relieving this constraint may enable extraction of maximal protection from a given budget of redundant bits, improving error probability and convergence speed. Accordingly, embodiments may be useful many storage technologies, for example Universal Flash Storage (UFS) storage devices.

(10) In addition, embodiments may allow the use of any systematic constituent (component) linear block code. When compared to the related-art methods that have similar capabilities, embodiments may benefit from a much smaller complexity, for example O (p.Math.k).

(11) FIG. 1 is a block diagram of a memory system according to embodiments of the present disclosure. Referring to FIG. 1, the memory system may include the memory controller 100 and a memory device 110, which may be a nonvolatile memory device.

(12) The memory device 110 may be, but is not limited to, a flash memory device, a NAND flash memory device, a phase change RAM (PRAM), a ferroelectric RAM (FRAM), a magnetic RAM (MRAM), etc. According to embodiments, the memory device 110 may include a plurality of NAND flash memory devices. The memory device 110 may have a planar structure or a three-dimensional (3D) memory cell structure with a stack of memory cells.

(13) The memory device 110 may include a memory cell array 115, an X Decoder 120, a voltage generator 114, an input/output (I/O) buffer 117, a page buffer 116, and a control logic 112 each of which may be implemented as one or more circuits. The memory device 110 may also include an I/O pad 111.

(14) The memory cell array 115 may include a plurality of word lines and a plurality of bit lines. Each memory cell of the memory cell array 115 may be implemented as a nonvolatile memory cell. For example, each memory cell of the memory cell array 115 may have, for example, a floating gate or a charge storage layer such as a charge trapping layer.

(15) The memory cell array 115 may include a plurality of blocks and a plurality of pages. Each block may include a plurality of pages. For example, a first block 118 may include a first plurality of pages 1-N while a second block 119 may include a second plurality of pages 1-N, where N is an integer greater than 1. A page may be a unit of program and read operations, and a block may be a unit of erase operation.

(16) The control logic 112 may control the overall operation of the memory device 110. When receiving a command CMD from the memory controller 100, the control logic 112 may interpret the command CMD and control the memory device 110 to perform an operation (e.g., a program operation, a read operation, a read retry operation, or an erase operation) according to the interpreted command CMD.

(17) The X Decoder 120 may be controlled by the control logic 112 and drive at least one of the word lines in the memory cell array 115 according to a row address.

(18) The voltage generator 114 may be controlled by the control logic 112 to generate one or more voltages required for a program operation, a read operation or an erase operation and provide the generated voltages to one or more rows selected by the X Decoder 120.

(19) The page buffer 116 may be controlled by the control logic 112 and operate as a sense amplifier or a write driver according to an operation mode (e.g., a read operation or a program operation).

(20) The I/O pad 111 and the I/O buffer 117 may serve as I/O paths of data exchanged between an external device, e.g., the memory controller 100 or a host and the memory device 110.

(21) The memory controller 100 may include a processor 101, a read-only memory (ROM) 103, a random access memory (RAM) 102, an encoder 104, a decoder 105, a memory interface 106, and a bus 107. The elements 101 through 106 of the memory controller 100 may be electrically connected to each other through the bus 107.

(22) The processor 101 may control the overall operation of the memory system including the memory controller 100. The processor 101 may include a circuit that controls other elements by generating control signals. When power is supplied to the memory system, the processor 101 may drive firmware (e.g., stored in the ROM 103) for operating the memory system on the RAM 102, thereby controlling the overall operation of the memory system. According to embodiments, the processor 101 may also issue instructions for controlling operations of other elements of the memory controller 100 including, for example, some or all of the ROM 103, RAM 102, encoder 104, decoder 105, memory interface 106, and a bus 107. According to embodiments, any operations described herein as being performed by the memory controller 100 may be performed by, or under the control of, the processor 101. According to embodiments, any operations described herein as being performed by the memory controller 100 may be performed by, or under the control of, the processor 101 executing instructions that correspond to the operations and are included in program code (e.g., stored in the ROM 103).

(23) A driving firmware code of the memory system may be stored in the ROM 103, however embodiments are not limited thereto. The firmware code can also be stored in a portion of the memory device 110. Therefore, the control or intervention of the processor 101 may encompass not only the direct control of the processor 101 but also the intervention of firmware which is software driven by the processor 101.

(24) The RAM 102, which may include a memory serving as a buffer, may store an initial command, data, and various variables input from a host or the processor 101, or data output from the memory device 110. The RAM 102 may store data and various parameters and variables input to and output from the memory device 110.

(25) The memory interface 106 may serve as an interface between the memory controller 100 and the memory device 110. The memory interface 106 is connected to the I/O pad 111 of the memory device 110 and may exchange data with the I/O pad 111. In addition, the memory interface 106 may create a command suitable for the memory device 110 and provide the created command to the I/O pad 111 of the memory device 110. The memory interface 106 provides a command to be executed by the memory device 110 and an address ADD of the memory device 110.

(26) According to embodiments, the decoder 105 may be an error correcting code (ECC) decoder configured to decode data in the manner described above, and the encoder 104 may be an ECC encoder configured to encode data in the manner described above. According to embodiments, the decoder 105 and the encoder 104 may perform error bit correction in the manner described above. The encoder 104 may generate data added with one or more parity and/or redundancy bits by performing error correction encoding on data before the data is provided to the memory device 110. The one or more parity and/or redundancy bits may be stored in the memory device 110.

(27) The decoder 105 may perform error correction decoding on output data, determine whether the error correction decoding is successful based on the result of the error correction decoding, and output an instruction signal based on the determination result. Read data may be transmitted to the decoder 105, and the decoder 105 may correct error bits of the data using the one or more parity and/or redundancy bits.

(28) In embodiments, encoder 104 and decoder 105 may be configured to encode and decode data including GLDPC codewords. A GLDPC codeword is a binary word having a length N which is composed of shorter codewords, which may be referred to as subcodewords, encoded with block encoding scheme which may be referred to as a component code, or constituent code. The constituent code may be a linear block code, for example a Reed-Muller code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a Hadamard code, or a Hamming code.

(29) FIG. 2 illustrates an example of a GLDPC codeword 200, according to embodiments. Each GLDPC codeword may have J≥2 different arrangements with a known bijective arbitrary mapping, or permutation, transforming between them. As a result, every bit of the GLDPC codeword 200 may belong simultaneously to J subcodewords; one in every arrangement. As shown in FIG. 2, the GLDPC codeword 200 may be represented in two arrangements, for example arrangement J.sub.1 and arrangement J.sub.2. Each of arrangement J.sub.1 and arrangement J.sub.2 may be an s×n matrix whose rows are subcodewords. GLDPC codeword 200 satisfies a basic relation shown in Equation 1 below:
N=s.sub.1.Math.n.sub.1= . . . =s.sub.j.Math.n.sub.j   (Equation 1)

(30) where n represents a length of each subcodeword, and s represents a number of the subcodewords. In embodiments, it may be possible that a subcodeword of one arrangement is of a different size than a subcodeword of another arrangement. In other words, it may be possible that that s.sub.1≠s.sub.2, n.sub.1≠n.sub.2, where s.sub.1 represents a number of subcodewords in first arrangement, n.sub.1 represents a length of a subcodeword in the first arrangement, s.sub.2 represents a number of subcodewords in second arrangement, and n.sub.2represents a length of a subcodeword in the second arrangement. Further, although FIG. 2 illustrates an example in which J=2, embodiments are not limited thereto.

(31) A GLDPC codeword may contain bits of several types. For example, information bits may be pure information bits as viewed by a GLDPC ECC. Parity bits may be constituent redundant bits resulting from the encoding in the two arrangements. Balancing bits may be used by embodiments to overcome a certain problem within the encoding procedure, as explained in greater detail below. Cyclic-redundancy-check (CRC) parity bits may be used to reduce an undetected error probability. In embodiments, CRC parity bits may be omitted. Shortening bits may be padding bits placed in the GLDPC arrangements in order to satisfy layout constraints. Shortening bits are not written to memory, but may be a virtual part of the matrices and may be considered to have a known value by the encoder and decoder, for example a value of 0. Unused bits may be parity bits that are not used. In embodiments, unused bits may be written to memory. In some embodiments, unused bits may have any known value, for example all having a value of 0, or all having a value of 1. In other embodiments, unused bits may have the value of the first l.sub.unused info bits. This may be chosen to considerations other than decoding performance, for example wear on a memory device that may be caused by frequent changes related to the unused bits. In embodiments, parity bits, balancing bits, CRC parity bits, and unused bits may be included in the redundant bits budget.

(32) Parameters involved with the structure of GLDPC codes, for example the matrix sizes (s×n) and those of their subsets, may be determined by a number of constraints. For example, for a given I.sub.0, which may represent a number of pure information bits to be encoded, and a given P.sub.0, which may represent a number of non-information bits allowed by a non-information bits budget, an encoding and decoding system according to embodiments may specify that I.sub.0=I.sub.data+I.sub.meta+I.sub.vss+I.sub.NCRC, may specify that N.sub.0=I.sub.0+P.sub.0, may specify that N=N.sub.0+sh.sub.total, where sh.sub.total represents a total number of shortening bits, and may specify that an overhead

(33) $OH=\frac{P_0}{I_0}.$

(34) In addition, a particular constituent code according to embodiments, for example an extended Hamming code, may specify that n=2.sup.m−short, where short represents a number of shortening bits in an information word of each subcodeword, may specify that p=m+1, where p represents a length of parity in each subcodeword of the constituent code, and may specify that k=2.sup.m−m−1−short=n−p, where k represents a length of an information word in each subcodeword.

(35) In addition, a GLDPC scheme according to embodiments may specify that N=s.sub.1.Math.n.sub.1=s.sub.2.Math.n.sub.2, and that P.sub.code=s.sub.1.Math.p.sub.1+s.sub.2.Math.p.sub.2+l.sub.cop, where l.sub.cop represents a length of a check-on-checks chunk. Further, a GLDPC encoding scheme according to embodiments may specify that l.sub.bal=l.sub.cop−1, where l.sub.bal represents a length of balance bits included in the GLDPC codeword, may specify that l.sub.cop=(s.sub.1−t.sub.1).Math.p.sub.1, where t.sub.1 represents a number of subcodewords in an information bit chunk of a first arrangement, for example arrangement J.sub.1, and may specify that P.sub.0=P.sub.code+l.sub.bal+l.sub.slack, where l.sub.slack=l.sub.CRC+l.sub.unused, and where l.sub.CRC represents a length of cyclic redundancy check bits, and l.sub.unused represents a length of unused bits.

(36) In embodiments, out of the possible configurations filtered by those constraints, a single configuration may be selected based on the following: Minimization of subcodeword length, n, through shortening: This may optimize the operation of the Belief-Propagation based decoder, by distributing a given information (protection) level delivered by the constituent codeword on an effectively reduced number of vulnerable bits. Minimization of the number unused bits: Unused bits may be part of the redundant bits budget and may be, for example, part of the information that is written to a storage, but unused bits do not carry any information nor code protection.

(37) FIGS. 3A-3B and 4A-4B illustrate two examples of partitioning schemes which may be used to partition an arrangement J.sub.1 and an arrangement J.sub.2 into partitions, which may be referred to as zones or bit chunks.

(38) FIGS. 3A-3B are block diagrams of arrangement J.sub.1 and arrangement J.sub.2 corresponding to a GLDC code, according to embodiments. As illustrated in FIGS. 3A-3B, arrangement J.sub.1 and arrangement J.sub.2 may be divided or partitioned into zones or bit chunks based on a purpose of the bits included in the zones or bit chunks.

(39) In embodiments, arrangement J.sub.1 may include, for example, a bit chunk Information 1, which may include information bits, a bit chunk Parity 1, which may include parity bits, a bit chunk Parity 2, which may include parity bits, a bit chunk CRC which may include CRC bits, one or more bit chunks Balance, which may include balance bits, and one or more bit chunks Unused, which may include unused bits. In addition, arrangement J.sub.1 may include a bit chunk Short info 1 which may include shortened bits, and a bit chunk Short parity 1 which may include parity bits.

(40) In embodiments, arrangement J.sub.2 may include a bit chunk Information 2, which may include information bits, a bit chunk Parity 2, which may include parity bits, and a bit chunk Short info 2, which may include shortened bits.

(41) In embodiments, the parity bits included in bit chunk Parity 1 and bit chunk Parity 2 may be the result of the systematic encoding of J.sub.1 and subsequently J.sub.2. The balance bits, CRC bits and unused bits may be an interleaved mixture of bits spread across the last rows of the bit chunk Information 1 following a priority order below (rightmost bottom to leftmost top): 1. Balance 2. Unused 3. CRC 4. Info

(42) The balance bits ordering may depend on the chosen permutation. Moreover, they may not be guaranteed to be ordered continuously, but the unused bits may be sufficient in covering the spaces between them, resulting in continuous CRC and information bit sequences.

(43) In embodiments, the bits of bit chunk Information 2 may be not identical to the bits of bit chunk Information 1. Instead, the bit chunk Information 2 may correspond to bits of bit chunk Information 1 bits and also bits having other roles including the bits of bit chunk Parity 1, the bits of the bits chunks Balancing and the bits of the bit chunk CRC. The bits of the bit chunk Short info 1 may be spread all across the bit chunk Information 2, depending on the permutation.

(44) FIGS. 4A-4B illustrate a partitioning scheme in which arrangement J.sub.1 and arrangement J.sub.2 are partitioned for permutation reasons. In particular, FIG. 4A illustrates arrangement A partitioned according to permutation constraints of the bits of arrangement J.sub.1, and FIG. 4B illustrates arrangement J.sub.2 partitioned according to permutation constraints of the bits of arrangement J.sub.2, according to embodiments.

(45) In embodiments, arrangement J.sub.1 may include a bit chunk A.sub.1, a bit chunk B.sub.1, and a bit chunk C.sub.1, and arrangement J.sub.2 may include a bit chunk A.sub.2, a bit chunk B.sub.2, and a bit chunk C.sub.2. In addition, arrangement J.sub.1 may include the bit chunks Short info 1 and Short parity 1 of FIG. 3A, and arrangement J.sub.2 may include the bit chunk Short info 2 of FIG. 3B.

(46) In embodiments, specific bit chunks from arrangement J.sub.1 and arrangement J.sub.2 may be constrained to exchange bits exclusively with each other, thus limiting the size of the ensemble of possible permutations. However, these “sub-permutations”, or permutations within the specific bit chunks, may be arbitrary within their boundaries;

(47) For example, in embodiments a GLDPC permutations ensemble, regardless of the actual permutation, may require that bit chunk A.sub.1 exchanges all its bits with all those of bit chunk A.sub.2 following an arbitrary permutation (π), may require that bit chunk B.sub.1 exchanges all its bits with all those of bit chunk B.sub.2, and may require that bit chunk C.sub.1 exchanges all its bits with all those of bit chunk C.sub.2, as represented in Equations 2-4 below:
π.sub.1.fwdarw.2(A.sub.1)=A.sub.2⇔π.sub.2.fwdarw.1(A.sub.2)=A.sub.1  (Equation 2)
π.sub.1.fwdarw.2(B.sub.1)=B.sub.2⇔π.sub.2.fwdarw.1(B.sub.2)=B.sub.1  (Equation 3)
π.sub.1.fwdarw.2(C.sub.1)=C.sub.2⇔π.sub.2.fwdarw.1(C.sub.2)=C.sub.1  (Equation 4)

(48) In embodiments, B.sub.2 and C.sub.2 may share the same initial bits “reservoir”, which may be referred to as bit chunk BC.sub.2, and the partition between the two may be arbitrary.

(49) The three permutations above may be independent of each other in principle. In embodiments, the “shortening” bit chunks do not participate in the exchange. In embodiments, the corresponding chunks excluding the “shortenings” may be identical in area. The bit roles, as discussed above, may not necessarily coincide with the chunk exchange partitioning.

(50) FIGS. 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13, and 14A-14B illustrate examples of arrangement J.sub.1 and arrangement J.sub.2 at various stages of an encoding process, according to embodiments. In embodiments, some or all of the encoding process or encoding processes described with respect to FIGS. 5A-14B may be performed by memory system 1000 or a component of memory system 1000, for example memory controller 100 or encoder 104.

(51) At a beginning of the encoding process, the following parameters may be known: Block Encoding : G z,? , parity part of constituent code generating matrix including shortening. All following block encoding operation may be calculation of only the “parity” part, as the “systematic” part is identical by definition. Dimensions parameters: constituent code parameters: p, n, k, short number of rows: s Permutation parameters: ind.sub.A, ind.sub.B, ind.sub.c, permutation matrices for corresponding bit chunks Balancing parameters: Indices of balancing bits within arrangement

(52) $J_1:\underset{1\times \left(l_{\mathrm{cop}}-1\right)}{{\mathrm{Ind}}_{\mathrm{Bal}}}$ Balancing matrix:

(53) $\underset{\left(l_{\mathrm{cop}}-1\right)\times \left(l_{\mathrm{cop}}-1\right)}{T_{\mathrm{Bal}}^{-1}}$ Balance to BC transfer matrix:

(54) $\underset{\left(l_{\mathrm{bal}}+b_{\mathrm{rows}}.Math.p\right)\times \left(s.Math.p\right)}{T_{\mathrm{bal}.fwdarw.{\mathrm{BC}}_1}}$

(55) As illustrated in FIGS. 5A-5B, at a beginning of an encoding procedure according to embodiments, the information bits may be obtained, and may be placed in the bit chunk Information 1. In FIG. 5A the information bits may be labeled Info. In addition, the bits of ind.sub.Bal,ind.sub.short may be set to 0, and the bits of ind.sub.unused may be set to the values of the first l.sub.unused information bits. The bits of ind.sub.CRC may be left blank.

(56) As illustrated in FIGS. 6A-6B, Ĩ may be block encoded to generate Ã.sub.1, by calculating

(57) $\underset{t\times n}{{\tilde{A}}_1}=\underset{t\times k}{\tilde{I}}.Math.\underset{k\times n}{G}.$
In this step, I may correspond to the information bits, for example bit chunk Information 1, I.sub.bal may correspond to bit chunk Balance, and I.sub.CRC may correspond to bit chunk CRC. Further, Ĩ may be equal to I\{rows with I.sub.Bal, I.sub.CRC}. This block encoding may be done row by row.

(58) As illustrated in FIGS. 7A-7B, the CRC bits may be determined by calculating

(59) $I_{CRC}=\frac{\widetilde{A_1}}{g_{CRC}},$
and the bit chunk CRC may be filled by setting J.sub.1[ind.sub.CRC]=I.sub.CRC.

(60) As illustrated in FIGS. 8A-8B, the block encoding of bit chunk A.sub.1 may be completed by block encoding {tilde over (Ĩ)} to generate {tilde over (Ã)}.sub.1 by calculating {tilde over (Ã)}.sub.1={tilde over (Ĩ)}.Math.G, where {tilde over (Ĩ)}=I\Ĩ. This block encoding may generate an initial P.sub.bal, which may be parity bits of bit chunk Parity 1 which are influenced by I.sub.bal, and which may be referred to as parity balance bits. The initial P.sub.bal may be saved for a later step.

(61) As illustrated in FIGS. 9A-9B, bit chunk A.sub.1 may then be permuted to obtain bit chunk A.sub.2 by calculating A.sub.2=π.sub.1.fwdarw.2(A.sub.1).

(62) As illustrated in FIGS. 10A-10B, A.sub.2 may be block encoded to obtain arrangement J.sub.2 by calculating

(63) $\underset{s\times n}{J_2}=\underset{s\times k}{A_2}.Math.\underset{k\times n}{G}.$
Then, bit chunk BC.sub.2 may be divided into bit chunk B.sub.2 and bit chunk C.sub.2 using B.sub.2=J.sub.2[ind.sub.B.sub.2], C.sub.2=J.sub.2[ind.sub.C.sub.2]. Although it is described herein that J.sub.1 and J.sub.2 use the same block encoding matrix G, embodiments are not limited to. In embodiments, J.sub.1 and J.sub.2 could use different block encoding matrices corresponding to a same type of constituent code, or different block encoding matrices corresponding to different types of constituent codes.

(64) As illustrated in FIGS. 11A-11B, bit chunk B.sub.2 may be permuted to obtain an initial bit chunk B.sub.1 by calculating B.sub.1=π.sub.2.fwdarw.1(B.sub.2). Initial bit chunk B.sub.1 may be saved for a later step, for example a second round of encoding.

(65) As illustrated in FIGS. 12A-12B, initial bit chunk B.sub.1 may be block encoded to generate bit chunk BC.sub.1 by calculating

(66) $\underset{\left(s-t\right)\times n}{{\mathrm{BC}}_1}=\underset{\left(s-t\right)\times k}{B_1}.Math.\underset{k\times n}{G}.$
This block encoding may generate an initial bit chunk C.sub.1, which may be saved for a later step, for example a second round of encoding.

(67) In embodiments, encoding procedure described above with respect to FIGS. 5A-12B may be referred to as a first round of the encoding procedure, and the encoding procedure described below with respect to FIGS. 13-14B may be referred to as a second round of the encoding procedure.

(68) As illustrated in FIG. 13, the balance bits may be adjusted. First, a difference may be determined between the initial bit chunk C.sub.1 determined above, and a result of a permutation of bit chunk C.sub.2. For example, the permuted C.sub.2 may be superposed onto the initial C.sub.1 using binary addition according to Equation 5 below:
P=C.sub.1+π.sub.2.fwdarw.1(C.sub.2)   (Equation 5)

(69) Then, the adjusted balance bits may be calculated using Equation 6 below:

(70) 0$\begin{array}{cc}\underset{1\times \left(l_{\mathrm{cop}}-1\right)}{{\underset{\_}{I}}_{\mathrm{Bal}}}=\underset{1\times \left(l_{\mathrm{cop}}-1\right)}{\underset{\_}{P}}.Math.\underset{\left(l_{\mathrm{cop}}-1\right)\times \left(l_{\mathrm{cop}}-1\right)}{T_{\mathrm{Bal}}^{-1}}& \left(\mathrm{Equation}6\right)\end{array}$

(71) Finally, the balance bits of arrangement J.sub.1, which were initially set to zero, may be adjusted by placing I.sub.bal in arrangement J.sub.1 using J.sub.1 [ind.sub.Bal]=I.sub.Bal.

(72) Then, as illustrated in FIG. 14A, the contribution of I.sub.bal to P.sub.bal may be determined, and that contribution may be added to the initial P.sub.bal determined above to adjust P.sub.bal. After P.sub.bal, is adjusted, I.sub.bal and P.sub.bal may then be combined into IP.sub.bal, and the contribution of IP.sub.bal to bit chunk BC.sub.1 may be determined in order to adjust the initial bit chunk B.sub.1 and bit chunk C.sub.1 determined above. Once the bit chunk B.sub.1 and the bit chunk C.sub.1 are adjusted, the encoding process may be complete.

(73) An example of a procedure for determining the contribution of I.sub.bal to P.sub.bal, and the contribution of IP.sub.bal to bit chunk BC.sub.1, is described in detail below.

(74) A basic requirement may be that the J=2 arrangements be identical up to permutation. However, the first round of the encoding procedure described above cannot guarantee that, and in principle C.sub.1≠π.sub.2.fwdarw.1(C.sub.2). Therefore, some preliminary actions may be taken.

(75) The encoding procedure described above may be a succession of matrix multiplications and permutations; both are linear operations. This means that they can be described as an equivalent single linear operation whose “input” is the Info chunk (flattened) and its outputs are arrangement J.sub.1, arrangement J.sub.2 any of their subsets or their linear combinations (flattened), hereby treated as “output”. For example

(76) $\underset{1\times s.Math.n}{J_1}=\underset{1\times t.Math.k}{I}.Math.\underset{t.Math.k\times s.Math.n}{T}.$
This linearity holds also for J.sub.2 or subsets of J.sub.1 and J.sub.2.

(77) In addition, for any “output” of some length, we may find a subset of I, an “input”, of identical length that is tied to that “output” through a reversible linear transform.

(78) The flattened Check-On-Parity (CoP) chunks, for example bit chunk C.sub.1 and bit chunk C.sub.2, may have a length of l.sub.cop=p.Math.(s−t). As discussed above, these may be considered “outputs” of the encoding procedure discussed above. Moreover, their subtraction can be considered an “output” as well, as shown in Equation 7 below:

(79) $\begin{array}{cc}\underset{1\times l_{\mathrm{cop}}}{P}=\underset{1\times l_{\mathrm{cop}}}{C_1}+{\pi }_{2.fwdarw.1}\left(\underset{1\times l_{\mathrm{cop}}}{C_2}\right)& \left(\mathrm{Equation}7\right)\end{array}$

(80) Where π.sub.2.fwdarw.1(C.sub.2) are bits of bit chunk C.sub.2 in arrangement J.sub.2 but permuted to arrangement J.sub.1.

(81) Because any GLDPC codeword has an information chunk that is larger than that, a subset can be found, I.sub.Bal⊂I , which satisfies the reversible relation given in Equation 8 below:

(82) $\begin{array}{cc}\underset{1\times l_{\mathrm{cop}}}{P}=\underset{1\times l_{\mathrm{cop}}}{I_{\mathrm{Bal}}}.Math.\underset{l_{\mathrm{cop}}\times l_{\mathrm{cop}}}{T_{\mathrm{Bal}}}& \left(\mathrm{Equation}8\right)\end{array}$

(83) The remaining info bits, I.sub.NoBal=I\I.sub.bal are also affecting P independently of I.sub.bal in a linear but non-reversible way. From the principle of superposition, as shown in Equation 9 below:
I.sub.Bal.Math.T.sub.Bal+I.sub.NoBal.Math.T.sub.NoBal=P.sub.Bal+P.sub.NoBal=P  (Equation 9)

(84) The demand for C.sub.1=π.sub.2.fwdarw.1(C.sub.2) can be seen to be equivalent to P=0, that is equivalent to: I.sub.Bal.Math.T.sub.Bal=I.sub.NoBal.Math.T.sub.NoBal

(85) Therefore, by sacrificing few bits of the total parity budget, the I.sub.bal bits according to Equation 10 below:

(86) $\begin{array}{cc}{I}_{\mathrm{Bal}}=\left(I_{\mathrm{NoBal}}.Math.T_{\mathrm{NoBal}}\right).Math.T_{\mathrm{Bal}}^{-1}& \left(\mathrm{Equation}10\right)\end{array}$

(87) The effect of I.sub.NoBal can be compensated such that P.sub.Bal=P.sub.NoBal.Math.P=0.

(88) T.sub.bal represents the reversible effect of the l.sub.cop bits within the info chunk on the l.sub.cop bits of CoP chunk. In embodiments, T.sub.bal may be constructed using the following procedure: Initialize: ind.sub.running=l.sub.info−1 (last [lowermost right] bit of the info chunk) cnt.sub.bal=0

(89) $\underset{{\mathrm{cnt}}_{\mathrm{bal}}\times l_{\mathrm{cop}}}{T_{\mathrm{bal},\mathrm{acc}}}=\mathrm{empty}$ Repeat the following steps: 1. Zeroise the info chunk 2. Set ‘1’ on bit ind.sub.running 3. Fully encode 4. Extract C.sub.1, C.sub.2 and compute

(90) $\underset{1\times l_{\mathrm{cop}}}{P}$ 5. Test linear dependency of P on current

(91) $\underset{{\mathrm{cnt}}_{\mathrm{bal}}\times l_{\mathrm{cop}}}{T_{\mathrm{bal},\mathrm{acc}}}:$
if independent, Append P to T.sub.bal,acc Increase cnt.sub.bal by 1 6. If cnt.sub.bal=l.sub.bal, Terminate. Else, decrease ind.sub.running by 1 and return to step 1

(92) The parity of the CoP sequence is always even; it has an even Hamming weight. Therefore, the last bit's value depends on the all its l.sub.cop−1 predecessors. Thus, the true length of I.sub.Bal and the dimensions of T.sub.Bal is l.sub.cop−1.

(93) Accordingly, in embodiments the contribution of I.sub.bal may be determined in the second round of the encoding procedure as follows. The balance bits immediate effect is on the

(94) $\underset{b_{\mathrm{rows}}\times p}{P_{\mathrm{bal}}}$
bits, where b.sub.rows is the number of rows within A that contain balance bits (usually 1 or 2). Both I.sub.bal and P.sub.bal are part of bit chunk A.sub.1 and therefore affect the BC chunks, for example bit chunk BC.sub.2 as well as bit chunk BC.sub.1.

(95) First, P.sub.bal may be calculated according to Equation 11 below:

(96) $\begin{array}{cc}\underset{b_{\mathrm{rows}}\times p}{P_{\mathrm{bal}}}=\underset{b_{\mathrm{rows}}\times k}{{\tilde{I}}_{\mathrm{bal}}}.Math.\underset{k\times p}{G}& \left(\mathrm{Equation}11\right)\end{array}$

(97) Where

(98) 0$\underset{b_{\mathrm{rows}}\times k}{{\tilde{I}}_{\mathrm{bal}}}$
are b.sub.rows zero rows to which the

(99) $\underset{1\times l_{\mathrm{bal}}}{I_{\mathrm{bal}}}$
bits were embedded in their appropriate locations, and added to the

(100) $\underset{b_{\mathrm{rows}}\times p}{P_{\mathrm{bal}}}$
calculated previously on the first round before the balance bits calculation.

(101) Next, the above may be merged into

(102) $\underset{1\times \left(l_{\mathrm{bal}}+b_{\mathrm{rows}}.Math.p\right)}{{\mathrm{IP}}_{\mathrm{bal}}},$
and BC.sub.1 may be computed according to Equation 12 below:

(103) $\begin{array}{cc}\underset{1\times s.Math.p}{{\mathrm{BC}}_1}=\underset{1\times \left(l_{\mathrm{bal}}+b_{\mathrm{rows}}.Math.p\right)}{{\mathrm{IP}}_{\mathrm{bal}}}.Math.\underset{\left(l_{\mathrm{bal}}+b_{\mathrm{rows}}.Math.p\right)\times \left(s.Math.p\right)}{T_{\mathrm{bal}.fwdarw.{\mathrm{BC}}_1}}& \left(\mathrm{Equation}12\right)\end{array}$

(104) This may be added to the

(105) $\underset{1\times s.Math.p}{{\mathrm{BC}}_1}$
calculated in the first round of the encoding procedure. In embodiments, the bit chunk B.sub.1 and the bit chunk C.sub.1 may be adjusted accordingly.

(106) In embodiments, T.sub.bal.fwdarw.BC.sub.1 may be a sparse matrix, which may result in a low complexity operation relative to the dimensions involved.

(107) FIG. 15A is a block diagram of an example of a process 1500A of controlling a storage system, according to embodiments. In some implementations, one or more process blocks of FIG. 15A may be performed by memory system 1000, or any other element described herein, for example memory controller 100 or encoder 104.

(108) As further shown in FIG. 15A, at operation 1504 the process 1500A may include obtaining information bits and placing the information bits in a first bit chunk included in a first arrangement of a generalized low-density parity-check (GLDPC) codeword. In embodiments, the first arrangement may correspond to the arrangement J.sub.1, and the first bit chunk may correspond to the bit chunk A.sub.1.

(109) As further shown in FIG. 15A, at operation 1506 the process 1500A may include setting balance bits included in the first bit chunk to zero.

(110) As further shown in FIG. 15A, at operation 1508 the process 1500A may include encoding the information bits and the balance bits using a systematic code to generate first parity bits, and placing the first parity bits in the first bit chunk. In embodiments, the systematic code may correspond to the constituent code or component code.

(111) As further shown in FIG. 15A, at operation 1510 the process 1500A may include permuting the first bit chunk to generate first permutated bits, and placing the first permutated bits in a second bit chunk included in a second arrangement of the GLDPC codeword. In embodiments, the second arrangement may correspond to the arrangement J.sub.2, and the second bit chunk may correspond to the bit chunk A.sub.2.

(112) As further shown in FIG. 15A, at operation 1512 the process 1500A may include encoding the first permutated bits using the systematic code to generate second parity bits and placing the second parity bits in a third bit chunk included in the second arrangement. In embodiments, the third bit chunk may correspond to the bit chunk BC.sub.2.

(113) As further shown in FIG. 15A, at operation 1514 the process 1500A may include permuting a first portion of the third bit chunk to generate second permutated bits, and placing the second permutated bits in a fourth bit chunk included in the first arrangement. In embodiments, the first portion of the third bit chunk may correspond to the bit chunk B.sub.2, and the fourth bit chunk may correspond to the bit chunk B.sub.1.

(114) As further shown in FIG. 15A, at operation 1516 the process 1500A may include encoding the second permutated bits using the systematic code to generate third parity bits; and placing the third parity bits in a fifth bit chunk included in the first arrangement. In embodiments, the fifth bit chunk may correspond to the bit chunk C.sub.1.

(115) As further shown in FIG. 15A, at operation 1518 the process 1500A may include permuting a second portion of the third bit chunk to generate fourth permutated bits. In embodiments, the second portion of the third bit chunk may correspond to the bit chunk C.sub.2.

(116) As further shown in FIG. 15A, at operation 1520 the process 1500A may include adjusting the first bit chunk by adjusting the balance bits based on a comparison between the fourth bit chunk and the fourth permutated bits.

(117) As further shown in FIG. 15A, at operation 1522 the process 1500A may include adjusting the fourth bit chunk and the fifth bit chunk based on the adjusted first bit chunk.

(118) As further shown in FIG. 15A, at operation 1524 the process 1500A may include obtaining the GLDPC codeword based on the adjusted first bit chunk, the adjusted fourth bit chunk, and the adjusted fifth bit chunk.

(119) As further shown in FIG. 15A, at operation 1526 the process 1500A may include storing the GLDPC codeword in a storage device. In embodiments, the storage device may correspond to memory system 1000 or memory device 1100.

(120) In embodiments, a bijective mapping may exist between the first arrangement and the second arrangement, and within the bijective mapping, bits of the first bit chunk may be mapped exclusively to bits of the second bit chunk, bits of the fourth bit chunk may be mapped exclusively to bits of the first portion of the third bit chunk, and bits of the fifth bit chunk may be mapped exclusively to bits of the second portion of the third bit chunk.

(121) In embodiments, the first arrangement may include a first plurality of rows and the second arrangement may include a second plurality of rows, and a number of the first plurality of rows may be different from a number of the second plurality of rows.

(122) In embodiments, each row of the first plurality of rows and the second plurality of rows may include a codeword of the systematic code, and the systematic code may include at least one from among a Reed-Muller code, a Hadamard code, a Bose-Chaudhuri-Hocquenghem code, and a Hamming code.

(123) FIG. 15B is a flowchart of a process 1500B of controlling a storage system, according to embodiments. In some implementations, one or more process blocks of FIG. 1500B may be performed by memory system 1000, or any other element described herein, for example encoder 104.

(124) In embodiments, one or more process blocks of process 1500B may be performed after process blocks of process 1500A.

(125) As shown in FIG. 15B, at operation 1528 the process 1500B may include determining a difference between the fourth bit chunk and the fourth permutated bits.

(126) As further shown in FIG. 15B, at operation 1530 process 1500B may include obtaining adjusted balance bits by multiplying the difference by a first balancing matrix.

(127) As further shown in FIG. 15B, at operation 1532 process 1500B may include adding the adjusted balance bits to the first bit chunk.

(128) As further shown in FIG. 15B, at operation 1534 process 1500B may include encoding the adjusted balance bits using the systematic code to generate fourth parity bits.

(129) As further shown in FIG. 15B, at operation 1536 process 1500B may include adjusting the parity balance bits by adding the fourth parity bits.

(130) As further shown in FIG. 15B, at operation 1538 process 1500B may include multiplying the adjusted balance bits and the adjusted balance parity bits by a second balancing matrix.

(131) As further shown in FIG. 15B, at operation 1540 process 1500B may include adding a result of the multiplying to the fourth bit chunk and the fifth bit chunk.

(132) Although FIGS. 15A-15B show example blocks of the processes 1500A-1500B, in some implementations, the processes 1500A-1500B may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIGS. 15A-15B. Additionally, or alternatively, two or more of the blocks of the processes 1500A-1500B may be arranged or combined in any order, or performed in parallel. For example, in embodiments the operations 1528-1536 may be included in operation 1520. As another example, in embodiments the operations 1538-1540 may be included in operation 1522.

(133) FIG. 16 is a block diagram of a computer system 16000 including a memory system according to embodiments. The computer system 16000, such as a mobile device, a desktop computer, and a server, may employ a memory system 16400 according to embodiments.

(134) The computer system 16000 may include a central processing unit 16100, a RAM 16200, a user interface 16300, and the memory system 16400, are electrically connected to buses 16500. The host as described above may include the central processing unit 16100, the RAM 16200, and the user interface 16300 in the computer system 16000. The central processing unit 16100 may control the entire computer system 16000 and may perform calculations corresponding to user commands input via the user interface 16300. The RAM 16200 may function as a data memory for the central processing unit 16100, and the central processing unit 16100 may write/read data to/from the memory system 16400.

(135) As in example embodiments described above, the memory system 16400 may include a memory controller 16410 and a memory device 16420. The memory controller 16410 may include an encoder and a decoder, and the memory device 16420 may include a cell array including a plurality of memory cells.

(136) According to embodiments, the memory controller 16410 may be implemented by the memory controller 100 discussed above with reference to FIG. 1, and the memory device 11420 may be implemented by the memory device 110 discussed above with reference to FIG. 1.

(137) FIG. 17 is a block diagram showing a memory card 17000 according to embodiments. The memory system 1000 according to example embodiments discussed above with reference to FIG. 1 may be the memory card 17000. For example, the memory card 17000 may include an embedded multimedia card (eMMC), a secure digital (SD) card, or a Universal Flash Storage (UFS) card. As shown in FIG. 17, the memory card 17000 may include a memory controller 17100, a non-volatile memory 17200, and a port region 17300. The memory controller 17100 may be implemented by the controller 100 discussed above with reference to FIG. 1, and the non-volatile memory 12200 shown in FIG. 17 may be implemented by the memory device 110 discussed above with reference to FIG. 1.

(138) The memory controller 17100 may include an encoder and a decoder. The encoder and the decoder may perform an encoding method and a decoding method according to embodiments. The memory controller 17100 may communicate with an external host via the port region 17300 in compliance with a pre-set protocol. The protocol may be eMMC protocol, SD protocol, SATA protocol, SAS protocol, USB protocol, UFS protocol, nonvolatile memory express (NVMe) protocol, peripheral component interconnect express (PCIe) protocol, or compute express link (CXL) protocol. The non-volatile memory 17200 may include memory cells which retain data stored therein even if power supplied thereto is blocked. For example, the non-volatile memory 17200 may include a flash memory, a magnetic random access memory (MRAM), a resistance RAM (RRAM), a ferroelectric RAM (FRAM), or a phase change memory (PCM).

(139) According to embodiments, memory controller 17100 and non-volatile memory 17200 may be implemented, respectively, by the memory controller 100 and the memory device 110 discussed above with reference to FIG. 1.

(140) FIG. 18 is a block diagram of a network system 18000 including a memory system according to embodiments. As shown in FIG. 18, the network system 18000 may include a server system 18100 and a plurality of terminals 18300, 18400, and 18500 that are connected via a network 18200. The server system 18100 may include a server 18110 for processing requests received from the plurality of terminals 18300, 18400, and 18500 connected to the network 18200 and an SSD 18120 for storing data corresponding to the requests received from the terminals 18300, 18400, and 18500. Here, the SSD 18120 may be a memory system according to embodiments.

(141) According to embodiments, SSD 18120 may be implemented by the memory system 1000 discussed above with reference to FIG. 1.

(142) As is traditional in the field, the embodiments are described, and illustrated in the drawings, in terms of functional blocks, units and/or modules. Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units and/or modules being implemented by microprocessors or similar, they may be programmed using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. Alternatively, each block, unit and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit and/or module of the embodiments may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the present scope. Further, the blocks, units and/or modules of the embodiments may be physically combined into more complex blocks, units and/or modules without departing from the present scope.

(143) The various operations of methods described above may be performed by any suitable means capable of performing the operations, such as various hardware and/or software component(s), circuits, and/or module(s).

(144) The software may include an ordered listing of executable instructions for implementing logical functions, and can be embodied in any “processor-readable medium” for use by or in connection with an instruction execution system, apparatus, or device, such as a single or multiple-core processor or processor-containing system.

(145) The blocks or steps of a method or algorithm and functions described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a tangible, non-transitory computer-readable medium. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD ROM, or any other form of storage medium known in the art.

(146) The foregoing is illustrative of the embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the present scope.

(147) Selected Notations and Abbreviations:

(148) n.sub.full: full length (non-shortened) of a subcodeword

(149) k.sub.full: full length (non-shortened) of a sub infoword

(150) short: Number of shortened bits within a codeword/inforword

(151) k=k.sub.full−short: Length of a sub infoword.

(152) n=n.sub.full−short: Length of a subcodeword

(153) p=n−k: Length of parity per subcodeword

(154) G: constituent code generating matrix. Left systematic (G=(I; A))

(155) s: Number of subcodewords in a GLDPC codeword

(156) t: Number of subcodewords in the Info chunk

(157) J: Number of equivalent arrangements of a GLDPC codeword

(158) ind.sub.A, ind.sub.B, ind.sub.c: Permutation indices per chunk

(159) ind.sub.sh: Indices of bits that are part of the GLDPC codeword but are not transmitted. Considered by the Decoder to have a known value (‘0’)

(160) l.sub.cop: Length of Check-On-Checks chunk (bits)

(161) ind.sub.Bal: Indices of balancing bits

(162) T.sub.bal, T.sub.Bal.sup.−1: balance bits to CoC transfer matrix (and its inverse)

(163) $\underset{\left(l_{\mathrm{bal}}+b_{\mathrm{rows}}.Math.p\right)\times \left(s.Math.p\right)}{T_{\mathrm{bal}.fwdarw.{\mathrm{BC}}_1}}:$
balance bits (and their corresponding parity) to BC.sub.1 chunk transfer matrix
l.sub.unused: Number of transmitted but unused bits. Considered by the Decoder to have a known value (‘0’)
π.sub.1.fwdarw.2(J.sub.1), π.sub.2.fwdarw.1(J.sub.2): Permutation between J.sub.1 and J.sub.2 arrangements
I.sub.0: Number of pure information bits
P.sub.0: Number of bits allocated for other purposes than info; parity, balancing, CRC etc.
N.sub.0=I.sub.0+P.sub.0: Total number of transmitted bits
sh.sub.total: Number of non-transmitted bits, that are considered part of the GLDPC codeword
N=N.sub.0+sh.sub.total: Total number of bits

(164) $OH=\frac{P_0}{I_0}:$
Overhead of codeword
ind.sub.CRC: the indices of the CRC sequence bits
l.sub.CRC: Length of CRC sequence (bits)
g.sub.CRC: CRC code generating polynomial