Methods of forming interdigitated back contact solar cells

Abstract

Methods for forming interdigitated back contact solar cells from III-V materials are provided. According to an aspect of the invention, a method includes depositing a patterned Zn layer to cover first areas of an n-type emitter region, wherein the emitter region comprises a III-V material, and forming a passivated back contact region by counter-doping the first areas of the emitter region by diffusing Zn from the patterned Zn layer into the first areas of the emitter region, such that the first areas of the emitter region become p-type.

Claims

1. A method comprising: depositing a patterned Zn layer to cover first areas of an n-type emitter region, wherein the n-type emitter region includes an emitter layer, a minority carrier confinement layer, and a contact layer; wherein the n-type emitter region is doped with at least one of Si, Se, S, or Te; wherein the depositing of the patterned Zn layer comprises electroplating a Zn layer on the emitter region; forming a mask on the first areas of the Zn layer corresponding to the first areas of the emitter region; wherein the mask is formed by nanoimprinting or microlithography; and removing Zn from second areas of the emitter region that are not covered by the mask; wherein the emitter region comprises a III-V material; and forming a passivated back contact region by counter-doping the first areas of the emitter region by diffusing Zn from the patterned Zn layer into the first areas of the emitter region, such that the first areas of the emitter region become p-type; wherein the passivated back contact region forms a back surface field.

2. The method according to claim 1, wherein the Zn is diffused such that a concentration of the Zn within the passivated back contact region decreases from an interface with the patterned Zn layer to an interface with a base layer on a side of the passivated back contact region opposite to the patterned Zn layer.

3. The method according to claim 1, further comprising depositing a metal layer on at least a portion of the patterned Zn layer and at least a portion of the second areas of the emitter region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 depicts a flowchart of an exemplary embodiment of a method for forming an IBC solar cell from III-V materials; and

(2) FIG. 2 depicts an enlarged view of a completed IBC solar cell using III-V materials.

DETAILED DESCRIPTION

(3) Exemplary embodiments of the present invention provide methods of forming IBC solar cells from III-V materials. This may be accomplished by forming patterned, well-passivated, back contacts by counter-doping diffusion rather than by epitaxial growth. This process is largely unexplored in III-V devices, yet opens a pathway for new device designs for solar cells, transistors, and power electronics. Further, closely spaced contact regions may be formed using low-cost nanoimprint technology to properly space and size the emitter and back-contact regions, while allowing very close metal finger tolerances for nearly full metal coverage. Nanoimprint technology may allow 5 m structures over cm length scales that may be optimized with 3D device modeling.

(4) FIG. 1 shows a flowchart of an exemplary embodiment of a method for forming an IBC solar cell from III-V materials. The method begins with a Grow step, during which various III-V layers are deposited by any suitable method, such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). In this example, an InGaP etch stop layer and a p-type GaAs buffer layer may be grown on a GaAs substrate for later removal of the GaAs substrate. Alternatively, one or more layers may be grown for later removal of the GaAs substrate by epitaxial liftoff. For example, growing an AlAs layer that can be selectively etched would allow for the GaAs substrate to be reused. Next, an AlInP window layer is deposited on the p-type GaAs buffer layer to provide a wide band gap front passivation layer for the p-type GaAs buffer layer. The AlInP window layer may be undoped, p-type for a front surface field, or n-type for a floating front emitter region. A p-type GaAs:Zn base layer, which functions as the main optical absorption region, is grown next on the AlInP window layer. A homojunction emitter made of GaAs doped with any suitable n-type dopant, such as Si, Se, S, or Te, is then deposited on the p-type GaAs:Zn base layer. For simplicity, FIG. 1 shows Si as the n-type dopant (for example, the homojunction emitter layer is labeled as GaAs:Si), but the Si may be replaced by any other suitable n-type dopant in any of the n-type layers shown in FIG. 1. Next, an n-type InGaP:Si minority carrier confinement layer is grown on the GaAs:Si homojunction emitter, and an n-type AlGaAs:Si contact layer is grown on the InGaP:Si minority carrier confinement layer to provide good Ohmic contact. Approximate ranges for the thicknesses of the various layers are depicted in FIG. 1. In an embodiment, the thickness of the various layers at the end of the Grow stage include a layer of AlGaAs:Si of from about 15 to about 20 nm adjacent to a InGaP:Si layer of from about 15 to about 20 nm adjacent to a GaAs:Si-emitter layer of from about 20 to about 50 nm adjacent to a GaAs:Zn-base layer of from about 1 to about 3 m adjacent to a AlInP-window layer of about 20 nm adjacent to a GaAs (buffer) layer of about 500 nm adjacent to a InGaP (etch stop) layer of about 500 nm which is adjacent to a GaAs substrate. As depicted in FIG. 1 and FIG. 2, materials that are p-type are shown in blue, while materials that are n-type are shown in red.

(5) As shown in FIG. 1, the method continues with the Plate step, in which a Zn layer is electroplated on the n-type AlGaAs:Si layer for subsequent diffusion of the p-type contacts. Although Zn is used here as an example, any other suitable p-type dopant with a sufficiently high diffusion coefficient may also be used. The Mask step then covers regions that will be subsequently diffused with Zn with any suitable mask. The Mask step may be performed by nanoimprinting or photolithography. The Etch step removes Zn from regions that will remain emitter regions for the solar cell by etching away regions of the Zn layer that are not covered with the mask. The mask is removed after the Etch step.

(6) The Diffuse step leverages the larger diffusion coefficient of Zn over the n-type dopant, such as Si, Se, S, or Te, to drive Zn into the three layers of the emitter region, which includes the AlGaAs:Si contact layer, the InGaP:Si minority carrier confinement layer, and the GaAs:Si homojunction emitter. The diffusion is performed by annealing, and an overpressure of As or P may be used. The Zn (or other suitable p-type dopant) is only driven into areas of the emitter region corresponding to areas of the Zn layer that were not removed during the Etch step. These areas are shown in greater detail in FIG. 2, where they are labeled as AlGaAs:Si:Zn, InGaP:Si:Zn, and GaAs:Si:Zn, respectively. The patterned Zn diffusion will counter-dope these areas of the emitter region, such that previously n-type materials become p-type materials, to form a passivated back contact region that includes passivated back contact areas to the GaAs:Zn base layer. The passivated back contact region forms a back surface field. The remaining areas of n-type materials form the emitter region.

(7) The diffusion profile within the passivated back contact region may vary as a function of the depth (i.e., the distance from the Zn layer). For example, areas that are closer to the Zn layer may have a higher concentration of Zn than areas that are farther from the Zn layer. The thicknesses of the layers within the passivated back contact region are much thinner (less than about 100 nm) than the widths of the areas within the n-type emitter region and the p-type passivated back contact region (about 5 m each) to minimize lateral counter-doping that could affect the cell functionality. Si is a slow diffuser in GaAs, while Se promotes Zn diffusion through a vacancy and interstitial kickout mechanism coupled with Coulombic attraction of Zn to substitutional Se on As sites. The p-type back contact region will be passivated by the counter-doped p-type InGaP:Si:Zn layer, while the n-type emitter region will remain as epitaxially grown. This will provide a GaAs/InGaP passivated interface for both the emitter region and the back contact region.

(8) The Metallize step then forms a metal layer on the exposed back surfaces. The metal may be formed on part or all of each surface. However, adjacent metal regions should not touch each other. Any appropriate metal may be used, such as Ni or Au. Finally, in the Etch+ARC step, the GaAs substrate and the InGaP etch stop layers are removed by etching, an antireflective coating (ARC) is deposited on the AlInP window layer. FIG. 2 depicts an enlarged view of a solar cell that is formed by the method described above. In an embodiment, and as depicted in FIG. 2, the positive and negative symbols represent the positive and negative terminals of the solar cell.

(9) The foregoing disclosure has been set forth merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof.