Method for manufacturing a membrane component and a membrane component

Abstract

The present invention relates to a method for manufacturing a membrane component with a membrane made of a thin film (<1 μm, thin-film membrane). The membrane component can be used in microelectromechanical systems (MEMS). The invention is intended to provide a method for manufacturing a membrane component, the membrane being manufacturable with high-precision membrane dimensions and a freely selectable membrane geometry. This is achieved by a method comprising . . . providing a semiconductor wafer (100) with a first layer (116), a second layer (118) and a third layer (126). Depositing (12) a first masking layer (112) on the first layer (116), the first masking layer (112) defining a first selectively processable area (114) for determining a geometry of the membrane (M.sub.1). Forming (13) a first recess (120) by anisotropic etching (13) of the first layer (116) and removing the first masking layer (112). Introducing (14) a material (122) in the first recess (120) and depositing (15) a membrane layer (124) on the first layer (116) with the introduced material (122). Depositing on the third layer (126) a second masking layer that defines a second selectively processable area. Forming a second recess by anisotropic etching of the third layer (126) and of the second layer (118) up to the first layer (116). Removing the second masking layer; and isotropically etching (18) the first layer (116), the isotropic etching being limited by the membrane layer (124) and by the introduced material (122), so that the membrane (M.sub.1) will be exposed.

Claims

1. A method for manufacturing a membrane component with a membrane, the method comprising: providing a semiconductor wafer (100) with a first layer (116), a second layer (118) and a third layer (126); depositing (12) a first masking layer (112) on the first layer (116), the first masking layer defining a first selectively processable area (114) for determining a geometry of the membrane (M1); forming a first recess (120) by anisotropic etching of the first layer; removing the first masking layer (112); introducing (14) a material (122) in the first recess (120); depositing (15) a membrane layer (124) on the first layer (116) with the introduced material (122); depositing on the third layer (126) a second masking layer that defines a second selectively processable area; forming a second recess by anisotropic etching of the third layer (126) and of the second layer (118) up to the first layer (116); removing the second masking layer; after the removal of the second masking layer, depositing (16) a fourth layer (152) on the third layer (126), on the first layer (116) and on at least one sidewall of the second recess created by anisotropically etching the third (126) and the second layer (118); and anisotropically etching (17) an area of the fourth layer (152), the area of the fourth layer (152) contacting the first layer (116), up to the first layer; and isotropically etching (18) the first layer (116), the isotropic etching being limited by the membrane layer (124) and by the introduced material (122), so that the membrane (M1) will be exposed.

2. The method according to claim 1, wherein the first layer (116) comprises a material different from that of the second layer (118).

3. The method according to claim 1, wherein the first layer (116) comprises a silicon layer and the second layer (118) comprises an oxide layer.

4. The method according to claim 1, wherein the semiconductor wafer (100) is a silicon-on-insulator wafer.

5. The method according to claim 1, wherein the first layer (116) has a first layer thickness (d1) smaller than a fourth thickness (d4) resulting from the summation of a second layer thickness (d2) of the second layer (118) and a third layer thickness (d3) of the third layer (126).

6. The method according to claim 5, wherein a ratio of the first layer thickness (d1) to the fourth thickness (d4) lies between 1:10 and 1:200.

7. The method according to claim 6, wherein a ratio of the first layer thickness (d1) to the fourth thickness (d4) lies between 1:50 and 1:150.

8. The method according to claim 7, wherein a ratio of the first layer thickness (d1) to the fourth thickness (d4) lies between 1:50 and 1:100.

9. The method according to claim 1, wherein a fourth layer (152) comprises a passivation layer.

10. The method according to claim 1, wherein at least the first or at least the second masking layer comprises a photoresist.

11. The method according to claim 1, wherein the first and the second masking layer are produced by means of photolithography.

12. The method according to claim 1, wherein the membrane (M1) has a circular, a rectangular, a polygonal, or a non-circular basic shape.

13. The method according to claim 1, wherein the membrane (M1) has at least one opening (150).

14. The method according to claim 13, wherein the membrane (M1) is perforated.

15. A method for manufacturing a membrane component with a membrane, the method comprising: providing a semiconductor wafer (100) with a first layer (116), a second layer (118) and a third layer (126); depositing (12) a first masking layer (112) on the first layer (116), the first masking layer defining a first selectively processable area (114) for determining a geometry of the membrane (M1); forming a first recess (120) by anisotropic etching of the first layer; removing the first masking layer (112); introducing (14) a material (122) in the first recess (120); depositing (15) a membrane layer (124) on the first layer (116) with the introduced material (122); depositing on the third layer (126) a second masking layer that defines a second selectively processable area; forming a second recess by anisotropic etching of the third layer (126) and of the second layer (118) up to the first layer (116); removing the second masking layer; polishing the first layer (116) with the introduced material (122) prior to applying (15) the membrane layer (124); and isotropically etching (18) the first layer (116), the isotropic etching being limited by the membrane layer (124) and by the introduced material (122), so that the membrane (M1) will be exposed.

16. The method according to claim 15, wherein the polishing is a chemical-mechanical polishing.

17. A method for manufacturing a membrane component with a membrane, the method comprising: providing a semiconductor wafer (100) with a first layer (116), a second layer (118) and a third layer (126); depositing (12) a first masking layer (112) on the first layer (116), the first masking layer defining a first selectively processable area (114) for determining a geometry of the membrane (M1); forming a first recess (120) by anisotropic etching of the first layer; removing the first masking layer (112); introducing (14) a material (122) in the first recess (120) wherein the introduced material (122) and the second layer (118) comprise an identical material; depositing (15) a membrane layer (124) on the first layer (116) with the introduced material (122); depositing on the third layer (126) a second masking layer that defines a second selectively processable area; forming a second recess by anisotropic etching of the third layer (126) and of the second layer (118) up to the first layer (116); removing the second masking layer; and isotropically etching (18) the first layer (116), the isotropic etching being limited by the membrane layer (124) and by the introduced material (122), so that the membrane (M1) will be exposed.

18. A method for manufacturing a membrane component with a membrane, the method comprising: providing a semiconductor wafer (100) with a first layer (116), a second layer (118) and a third layer (126); depositing (12) a first masking layer (112) on the first layer (116), the first masking layer defining a first selectively processable area (114) for determining a geometry of the membrane (M1) wherein the membrane (M1) has at least one opening (150); forming a first recess (120) by anisotropic etching of the first layer; removing the first masking layer (112); introducing (14) a material (122) in the first recess (120); depositing (15) a membrane layer (124) on the first layer (116) with the introduced material (122); depositing on the third layer (126) a second masking layer that defines a second selectively processable area; forming a second recess by anisotropic etching of the third layer (126) and of the second layer (118) up to the first layer (116); removing the second masking layer; and isotropically etching (18) the first layer (116), the isotropic etching being limited by the membrane layer (124) and by the introduced material (122), so that the membrane (M1) will be exposed, wherein the isotropic etching is carried out through the at least one opening (150) of the membrane (M1).

Description

INTRODUCTION TO THE DRAWINGS

(1) The embodiments of the present invention are described on the basis of examples, but they are not described in a way allowing limitations to be transferred from the figures to the claims or to be read into the claims. Like reference numerals stand for like elements.

(2) FIG. 1 shows schematic representations 11, 12, . . . , 15 of a pre-patterning of an SOI wafer 100 at various stages of pre-patterning of the SOI wafer 100 and a deposition of a continuous membrane layer 124, each shown in a sectional view, for manufacturing a membrane component 190;

(3) FIG. 2 shows schematic representations 15, 17, 18 of the membrane component manufacture from the pre-patterned SOI wafer with a continuously deposited membrane layer 124, at various stages of manufacture, each shown in a sectional view;

(4) FIG. 3 shows schematic representations 15′, 17′, 18′ of the membrane component manufacture from a pre-patterned SOI wafer with a discontinuously deposited membrane layer 124′ at various stages of manufacture, each shown in a sectional view;

(5) FIG. 4 shows schematic representations 41, 42, . . . , 46 of a pre-patterning of a silicon wafer by means of local oxidation at various stages of the pre-patterning of the silicon wafer, and a deposition of a continuous membrane layer 224 for the manufacture of a membrane component 290, each shown in a sectional view;

(6) FIG. 5 shows schematic representations 46, 47, 48 of a membrane component manufacture of the silicon wafer pre-patterned by local oxidation and provided with a continuously deposited membrane layer 224 at various stages of membrane component manufacture, each shown in a sectional view;

(7) FIG. 6 shows schematic representations 46′, 47′, 48′ of a membrane component manufacture of a silicon wafer pre-patterned by local oxidation and provided with a discontinuously deposited membrane layer 224′ at various stages of manufacture, each shown in a sectional view;

(8) FIG. 7 shows schematic representations of membrane geometries in a top view;

(9) FIG. 8 shows a schematic representation of the membrane component 190 in a sectional view and a detail extract of the membrane component.

(10) FIG. 9 shows a schematic representation of the membrane component 290 in a sectional view and a detail extract of the membrane component.

DETAILED DISCLOSURE

(11) FIG. 1 shows a pre-patterning of an SOI wafer 100 at various stages of pre-patterning of the SOI wafer 100 and a deposition of a continuous membrane layer 124, each shown in a sectional view, for manufacturing a membrane component 190.

(12) Section 11 shows the semiconductor wafer 100 of a type that may be provided for a method for manufacturing the membrane component 190. The semiconductor wafer comprises three layers: a first layer 116, a second layer 118, and a third layer 126.

(13) The first layer 116 has a first layer thickness d.sub.1, the second layer 118 has a layer thickness d.sub.2, and the third layer 126 has a layer thickness d.sub.3. A fourth thickness d.sub.4 results from the summation of the layer thicknesses d.sub.2 and d.sub.3.

(14) The semiconductor wafer 100 may be an SOI wafer. Accordingly, the first layer 116 may be a (thin) silicon layer, the second layer 118 may be a (thin) oxide layer (BOX), and the third layer 126 may be a carrier substrate layer made of silicon.

(15) Section 12 shows the semiconductor wafer 100 with an additionally deposited masking layer 112. The masking layer 112 has an opening.

(16) The opening may preferably have an annular basic shape.

(17) In the example shown, an annular opening is shown. Correspondingly, depicted depressions are shown as portions of the opening and connected to each other.

(18) The first masking layer 112 may be formed by means of photolithographic processes and may serve as an etch mask.

(19) The masking layer 112 may comprise a photoresist. The photoresist may be applied by spin coating.

(20) The opening in the masking layer 112 can be removed, for example, by means of development or exposure (positive resist).

(21) The opening in the first masking layer 112 exposes a first selectively processable area 114 on the first layer 116. A surface of the first layer 116, with the exception of the area 114, is covered by the masking layer 112.

(22) Section 13 shows the semiconductor wafer 100 after anisotropic etching (in a z-direction) of the first layer 116.

(23) The anisotropic etching of the first layer may include trench etching by deep reactive ion etching.

(24) The anisotropic etching may, in sections, take place through the entire layer thickness of the first layer 116 (in a z-direction) and at least partially through the second layer 118. Preferably, the anisotropic etching can be stopped, when a surface of the second layer 118 has been exposed, without residues of the first layer 116 remaining on the exposed surface of the second layer 118. The first recess 120 shown can thus be created by the anisotropic etching.

(25) The recess 120 has a basic shape that (substantially) corresponds to the first selectively processable area 114.

(26) Section 14 shows the semiconductor wafer 100 without the masking layer 112 and with a material 122 introduced into the recess 120.

(27) For example, the first masking layer 112 can, if the masking layer comprises a photoresist, be removed by means of a remover (e.g. acetone, 1-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), etc.), stripping, or ashing (O.sub.2 ashing).

(28) The introduced material 122 and the second layer 118 may both comprise an oxide material (oxide layer material).

(29) The introduced material 122 can be introduced into the second layer 118 by means of trench isolation (deep trench isolation) (thermal oxidation and filling of the trench with CVD oxide).

(30) When the material 122 has been introduced, a subsequent polishing step (chemical-mechanical polishing) may be carried out.

(31) Section 15 shows the semiconductor wafer 100 with the additionally deposited membrane layer 124.

(32) The membrane layer 124 may be deposited areally.

(33) The membrane layer may comprise aluminum nitride (AlN), in particular the membrane layer may be made of aluminum nitride.

(34) The membrane layer may be deposited by physical vapor deposition (PVD), sputtering or metal organic chemical vapor deposition (MOCVD).

(35) FIG. 2 shows the completion of the membrane component on the basis of the pre-patterned SOI wafer with the continuously deposited membrane layer 124, at various stages of manufacture, each shown in a sectional view.

(36) Section 15 according to FIG. 1 is shown again, for simplifying the understanding of the manufacturing process, and represents the starting point for the following process steps.

(37) Section 16 shows the pre-patterned semiconductor wafer 100 with a fourth layer 152 deposited, in sections, on the first layer 116, the third layer 126 and sidewalls of a recess in the third layer 126 and the second layer 118.

(38) The recess in the third layer 126 and the second layer 118 may be produced by anisotropic etching of the third layer 126 and the second layer 118. The anisotropic etching of the third and of the second layer may be carried out selectively and, in particular, the geometry of the recess may be determined by previously masking the third layer 126 or by applying thereto a second masking layer with an opening defining a second selectively processable area.

(39) The anisotropic etching may stop on the first layer 116. In particular, the anisotropic etching of the third layer 126 can be stopped, when a surface of the first layer has been (completely) exposed, without residues of the second layer 118 remaining on the first layer 116. Subsequently, the fourth layer 152 may be deposited.

(40) The fourth layer 152 may comprise an oxide layer, and in particular, the fourth layer 152 may be an oxide layer.

(41) The fourth layer 152 may comprise a passivation layer, and in particular, the fourth layer 152 may be a passivation layer.

(42) A cavity 146 is formed (enclosed) by sidewalls of the fourth layer 152.

(43) The cavity 146 may have a circular base.

(44) Section 17 shows the semiconductor wafer 100 after another anisotropic etching step (in a z-direction) of the fourth layer 152, so that the cavity 142 is formed (as a recess of the cavity 148). The area etched (removed) is exclusively the area of the fourth layer 152 that contacted the second layer 118, a surface of the first layer 116 being thus exposed.

(45) Section 18 shows the semiconductor wafer 100 (or membrane component 190) with the first layer 116 partially removed.

(46) A portion of the first layer 116 enclosed by the membrane layer 124 and by the introduced material 122 can be removed by means of an isotropic etching step. The isotropic etching can be stopped by the membrane layer 124 and by the introduced material 122 so that a recess 142 is formed that extends up to underneath the membrane layer 124 and up to a sidewall 144 (sidewalls) of the introduced material, thereby exposing the membrane layer 124 on both sides.

(47) The portion of the membrane layer 124 exposed on both sides forms a membrane M.sub.1.

(48) FIG. 3 shows a manufacture of a membrane component 190′ from a pre-patterned Sol wafer with a discontinuously deposited membrane layer 124′ at various stages of manufacture, each shown in a sectional view.

(49) The representations according to sections 15′ to 18′ correspond substantially to the sectional views 15 to 18 according to FIG. 2, except that the membrane layer 124′ has an opening 150.

(50) The membrane M.sub.1′ may have a plurality of openings, in particular it may be perforated.

(51) An isotropic etching of the semiconductor wafer 100 for removing a part of the first layer 116, as shown in 18′, can be carried out through the opening 150 (on the front side).

(52) FIG. 4 shows a pre-patterning of the semiconductor wafer 200 by means of a layer modification (local oxidation) at various stages of the pre-patterning of the semiconductor wafer 200 and a deposition of a continuous membrane layer 224, each shown in a sectional view, for the manufacture of a membrane component 290.

(53) Section 41 shows the semiconductor wafer 200. The semiconductor wafer 200 includes a first layer 216, a second layer 218, and a third (carrier) layer 226 (silicon wafer). The third layer 226 has a layer thickness d.sub.8.

(54) The first layer 216 may comprise a silicon layer, and in particular, the first layer 216 may be a silicon nitride layer.

(55) The second layer 218 may comprise an oxide layer, and in particular, the second layer 218 may be a silicon dioxide layer.

(56) Section 42 shows the semiconductor wafer 200 having a first masking layer 212. The first masking layer has an opening. Through the opening in the first masking layer 212, a first selectively processable area 214 is defined on the first layer 216.

(57) The first masking layer 212 may be formed by means of photolithographic processes and serve as an etch mask. The masking layer 212 may comprise a photoresist.

(58) The first selectively processable surface 214 may, in particular, define a geometry of a membrane M.sub.2 yet to be manufactured.

(59) Section 43 shows the semiconductor wafer 200 with the masking layer 212 removed and the first and second layers 216, 218 partially removed.

(60) The partial or selective removal of the first and second layers 216, 218 can be carried out by means of (deep) reactive ion etching.

(61) The anisotropic etching may take place through the entire first layer 216 (in a z-direction) and the second layer 218. In particular, the anisotropic etching may be stopped, when a surface of the third layer 226 has been exposed, without residues of the second layer 218 remaining on the exposed surface of the third layer 226.

(62) Due to the partial removal of the first and second layers 216, 218, the recess 220 is created.

(63) Section 44 shows the semiconductor wafer 200 with a layer modification 222.

(64) The layer modification 222 may be produced by means of localized thermal oxidation of silicon.

(65) The oxidation may further include growing SiO.sub.2 on silicon.

(66) The layer modification 222 extends into a depth d.sub.7 of the third layer 226.

(67) The depth d.sub.7 may be smaller than a layer thickness d.sub.8 of the third layer 226. The depth d.sub.7 of the layer modification 222 may be substantially smaller than the layer thickness d.sub.8 of the third layer 226, preferably a ratio of the depth d.sub.7 to the layer thickness d.sub.8 lies between 1:5 and 1:150, more preferably 1:100.

(68) Section 45 shows the semiconductor wafer 200 with the first and second layers 216, 218 completely removed. What remains is the third layer 226 with the embedded layer modification 222.

(69) The first layer 216 can be removed by means of wet chemical etching.

(70) The first and/or the second layer 216, 218 can be removed by polishing, in particular by chemical-mechanical polishing.

(71) The polishing may be carried out down to the third layer. In particular, the polishing may be stopped, when no residues of the second layer 218 remain on the third layer 226.

(72) In section 46, the semiconductor wafer is shown with a membrane layer 224 deposited thereon.

(73) The membrane layer may be deposited areally.

(74) The membrane layer may be deposited by means of sputtering.

(75) The membrane layer may be a thin film. In particular, the membrane may be thinner than 1.0 μm.

(76) The membrane layer may comprise aluminum nitride (AlN), and in particular, the membrane layer may be made of AlN.

(77) FIG. 5 shows the continuation of the manufacture of the membrane component from the silicon wafer pre-patterned by local layer modification and with a continuously deposited membrane layer 224 at various stages of membrane component manufacture, each shown in a sectional view. For better understanding, section 46 is shown in FIG. 5 once more.

(78) Section 47 shows the semiconductor wafer 200 with the third layer 226 partially removed.

(79) Partially removing the third layer may comprise a previous masking of the third layer 226 with a second masking layer that defines a second selectively processable area on the third layer 226.

(80) The second masking layer may be produced by means of photolithographic processes. The masking layer may comprise a photoresist.

(81) The second selectively processable area may result from at least one opening in the second masking layer.

(82) The second selectively processable area may determine a geometry of a recess to be created.

(83) The partial removal of the third layer may be accomplished by means of anisotropic etching (deep reactive ion etching) resulting in a recess 248 in the third layer 226.

(84) The anisotropic etching may stop on the layer modification 222. In particular, the anisotropic etching may be stopped, when a surface of the layer modification has been exposed, without any residues of the third layer 226 remaining on the layer modification 222.

(85) A basic shape of the recess 248 may (substantially) correspond to the second selectively processable area defined by the second masking layer.

(86) Section 47 shows the semiconductor wafer 200 (or membrane component 290) with the layer modification 222 removed, so that a part of the membrane layer 224 is exposed on both sides. The area of the membrane layer 224 exposed on both sides defines the membrane M.sub.2.

(87) The removal of the layer modification 222 can be carried out by means of an isotropic etching step.

(88) The isotropic etching may stop in particular at the membrane layer 224 and the third layer 226, so as to form a recess 242 that extends up to underneath the membrane layer 224 and exposes a sidewall 244 (sidewalls) of the third layer 226.

(89) FIG. 6 shows a manufacture of a membrane component 290′ from a silicon wafer, pre-patterned by means of local oxidation and provided with a discontinuously deposited membrane layer 224′, at various stages of manufacture, each shown in a sectional view.

(90) The representations according to sections 46′ to 48′ correspond substantially to the sectional views 46 to 48, except that the membrane layer 224′ has an opening 250.

(91) The membrane layer 224′ may have a plurality of openings, and in particular it may be perforated.

(92) A removal of the layer modification 222 by isotropic etching can be carried out through the opening 250 (on the front side).

(93) FIG. 7 shows various membrane geometries of membrane components 390, 490, 590 and 690 in top views. The areas in dark gray each correspond to a respective membrane layer 324, 424, 524 and 624. For a better representation of the geometries, a dashed-line representation of the structural edges actually located under the membrane layers 324, 424, 524 and 624 has been dispensed with. Instead, a sectional view A-A of one of the membrane components (membrane component 390) shown in FIG. 7 is illustrated.

(94) The sectional view A-A shows the membrane component 390 in a cutaway view. The membrane component comprises a membrane layer 324 with a membrane, a material 344 enclosed by a first layer with an exposed sidewall 344, and a cavity 342.

(95) In the top view, it can be seen that the cavity 342 has a circular basic shape.

(96) The cavity 342 may have a different basic shape, for example, the cavity may have a rectangular, polygonal, or non-circular basic shape.

(97) The introduced material 324 has a circular basic shape.

(98) Through the introduced material 322, a geometry of a membrane in the membrane layer 324 can be defined, since the introduced material 322 (and the membrane layer 322 itself) can stop an isotropic etching process during a step carried out for exposing the membrane (cf. FIGS. 2 and 3, sections 18 and 18′, respectively).

(99) The membrane components 390, 490, 590 and 690 shown are identical to one another, except for the geometries of the membrane.

(100) In this respect, 442, 542 and 642 equal to 342 identify a (circular) cavity of the respective membrane component, and 422, 522 and 622 equal to 322 identify a material enclosed by a first layer of the respective membrane component. The enclosed material 422, 522 and 622 equal to 322 has a respective exposed sidewall 444, 544, and 644.

(101) The membrane component 490 has a membrane with a hexagonal basic shape.

(102) The membrane component 590 has a membrane with a square basic shape. In particular, corners of the membrane may be rounded or blunted.

(103) The membrane component 690 has a membrane with a sawtooth-shaped or star-shaped basic shape.

(104) Coordinates of a plane defined by a surface of the membrane component 390, 490, 590 and 690 can unambiguously be defined by an x-y coordinate system.

(105) FIG. 8 shows the membrane component 190 in a sectional view and a detail extract of the membrane component 190.

(106) The detail extract shows a portion of the introduced material 122, of the first layer 116, of the membrane layer 124, and of the membrane M.sub.1.

(107) Between the membrane layer 124 and the membrane M.sub.1, respectively, and an (exposed) sidewall 144 of the enclosed material 144, an angle α.sub.1 is included.

(108) The angle α.sub.1 may be substantially 90.0°. The angle α.sub.1 may be between 88.0° and 92.0°, and in particular, between 89.0° and 91.0°.

(109) The angle α.sub.1 may result from process-related deviations. Due to the angle α.sub.1, a deviation d.sub.10 in a geometry of the introduced material 122 from the selectively processable area 114 previously determined by the first masking layer 112 may occur into a depth (in a z-direction taking as a basis the membrane layer) of the semiconductor wafer 100.

(110) The deviation d.sub.10 may be less than 20.0 μm, preferably less than 10.0 μm, more preferably less than 1.0 μm.

(111) FIG. 9 shows the membrane component 290 in a sectional view and a detail extract of the membrane component 290.

(112) The cavity 242 comprises a first section 260 and a second section 264. The first section 260 has a first lateral dimension SAL The second section 264 has a second lateral dimension S.sub.A2.

(113) The first and/or the second lateral dimension S.sub.A1, S.sub.A2 may each describe a diameter of a circle.

(114) The second lateral dimension S.sub.A2 may be unequal to the first lateral dimension S.sub.A1, and in particular, the second lateral dimension S.sub.A2 may even be 50% smaller than the first lateral dimension S.sub.A1 preferably 30%, more preferably 10%.

(115) The detail extract shows, in sections, the third layer 226, the membrane layer 224 and the membrane M.sub.2.

(116) Between the membrane layer 224 and the membrane M.sub.2, respectively, and the sidewall 244 of the third layer 226, an angle α.sub.3 is included.

(117) The angle α.sub.3 may be substantially 90.0°. The angle α.sub.3 may be between 88.0° and 92.0°, and in particular between 89.0° and 91.0°.

(118) Also the angle α.sub.3 may result from process-related deviations. Due to the angle α.sub.3, a (geometry) deviation d.sub.11 (in comparison with a lateral dimension that was predetermined by the selectively processable area) occurs into a depth (in a z-direction taking as a basis the membrane layer 224) of the semiconductor wafer 200.

(119) The deviation d.sub.11 may be less than 20.0 μm, preferably less than 10.0 μm, more preferably less than 1.0 μm.