GaN based adjustable driver current circuit

Abstract

A circuit for providing an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, V.sub.GS, for a high-current GaN driver FET to obtain a desired, high slew-rate driver current, I.sub.DRV. An externally provided reference current is used to create the required V.sub.GS for the driver FET, which is stored on an external capacitor. The value of the capacitor far exceeds the relatively low input-capacitance of the GaN driver FET. When a pulse I.sub.DRV of desired value is needed, the voltage on the capacitor is impinged upon the gate of the driver FET, thereby creating the desired I.sub.DRV. The reference charging circuit replenishes any charge lost on the capacitor, so that the same desired I.sub.DRV can be obtained on the next command pulse.

Claims

1. An adjustable current driver circuit, comprising: a circuit comprising a current mirror for charging a storage capacitor from a first supply voltage based on an externally provided reference current; and a pulse controller circuit, responsive to a control signal, for connecting the storage capacitor to a gate of a power transistor to drive and allow driving current to flow through the power transistor, or for disconnecting the storage capacitor from the gate of the power transistor and connecting the gate of the power transistor to ground, to prevent driving current from flowing through the power transistor.

2. The adjustable current driver circuit of claim 1, wherein the power transistor comprises a first gallium nitride (GaN) field effect transistor (FET) connected to a second supply voltage, wherein the second supply voltage is greater than the first supply voltage.

3. The adjustable current driver circuit of claim 2, wherein the current mirror comprises a plurality of GaN FET transistors, and the pulse controller circuit comprises a plurality a GaN FET transistors, all of the GaN FET transistors of the current mirror and the pulse controller circuit being substantially smaller in size than the GaN FET power transistor controlled by the driver circuit.

4. The adjustable current driver circuit of claim 1, wherein the storage capacitor has a capacitance greater than an input capacitance of the power transistor.

5. The adjustable current driver circuit of claim 1, further comprising a resistor connected to the pulse controller circuit and the power transistor for discharging the charge on the storage capacitor and shutting down the flow of the driving current through the power transistor in the event that the control signal is stuck on.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

(2) FIG. 1 illustrates schematics of a conventional current driver circuit.

(3) FIG. 2 illustrates an adjustable current driver circuit according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(4) In the following detailed description, reference is made to certain embodiments. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made. The combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in the broadest sense and are instead taught merely to describe particularly representative examples of the present teachings.

(5) FIG. 2 illustrates an adjustable current driver circuit 200 according to the present invention. As described in detail below, the circuit of the present invention, which can be implemented as a low-power integrated circuit, provides an adjustable output driver current for use in LiDAR or other similar GaN driver applications. The circuit creates an appropriate gate-to-source voltage, V.sub.GS, for a high-current GaN driver FET 295 to obtain a desired, high slew-rate output current (typically, tens of Gaga-Amps/second). An externally provided reference current I.sub.REF is used to create the required V.sub.GS needed for the driver FET 295. The V.sub.GS created by the circuit adjusts variations in process traits, temperature or supply voltage. The V.sub.GS voltage is stored on an external capacitor 250. The value of capacitor 250 far exceeds the parasitic capacitance C.sub.ISS of the large GaN driver FET 295, but is still practical in size given the low value of input capacitance for GaN FETs.

(6) When a pulse current of desired value is needed (i.e., when the driver FET 295 needs to be activated), the voltage on capacitor 250 is impinged upon the gate of the driver FET 295 through a pulse controller 270 that connects capacitor 250 to the gate of the driver FET 295, thereby creating the desired and scaled up driver current. When the driver FET 295 is to be turned off, the pulse controller 270 opens the connection to capacitor 250 and shorts the gate of driver FET 295 to ground.

(7) Any charge lost on capacitor 250 due to the charge transfer to driver FET 295 is replenished by the reference charging circuit I.sub.CHG, which is on the same order of magnitude as the reference current I.sub.REF, so that the same desired rapid and large driver current can be obtained on the next command pulse to produce the next rapid and large slew-rate pulse. Advantageously, the instantaneous draw of current from the supply to charge the gate of the driver FET 295 is highly reduced due to the charge already being pre-stored in the capacitor prior to the generation of the output current pulse. This reduces supply voltage spiking.

(8) The circuit preferably includes a safe driver shut-down in the event the command signal gets stuck on, as described in further detail below.

(9) Turning now to the details of the preferred embodiment of the invention shown in FIG. 2, adjustable current driver circuit 200 includes current mirror 220, capacitor 250, pulse controller 270, and driving transistor 295. Current mirror 220 receives the reference current I.sub.REF, in this example from external current source 245, and outputs a charging current I.sub.CHG from supply voltage V.sub.dd 215B for charging capacitor 250. As shown in FIG. 2, current mirror 220 includes transistors 225, 230, 235, and 240, connected together in a conventional arrangement. Pulse controller 270 includes transistors 280 and 285. Transistors 225, 230, 235, and 240 in current mirror 220, transistors 280 and 285 in pulse controller 270, and driving transistor 295, are all preferably enhancement mode GaN FET semiconductor devices, which are all preferably monolithically integrated onto a single semiconductor die.

(10) Current mirror 220 has a conventional topology, with the gate and drain terminals of transistor 225 connected together and receiving I.sub.REF, in this example from current source 245. The source terminal of transistor 225 is connected to the drain terminal of transistor 235. The gate terminal of transistor 235 is connected to the gate and drain terminals of transistor 240, and to source terminal of transistor 230, at node 255. The gate terminal of transistor 230 is connected to the gate and drain terminals of transistor 225. The drain terminal of transistor 230 is connected to supply voltage source 215B.

(11) In the operation of the circuit, the charging current I.sub.CHG is drawn from supply voltage source 215B by current mirror 220 based on the reference current I.sub.REF and charges capacitor 250 to a desired voltage that will be applied to the gate terminal of driving transistor 295. Changes to the value of I.sub.REF result in changes in the value of charging current I.sub.CHG and the charge stored in capacitor 250. Variation of I.sub.REF offers dynamic control of the voltage across capacitor 250, such that capacitor 250 can apply different voltages to the gate terminal of driving transistor 295 in response to variations in temperature, supply voltage, circuit impedances, and process variations. By extension, variation of I.sub.REF enables dynamic control of the driving current I.sub.DRV through driving transistor 295 by controlling the voltage applied to its gate terminal.

(12) The capacitance of capacitor 250 is much larger than the input capacitance C.sub.ISS of driving transistor 295 to ensure it can store charge from I.sub.CHG such that the voltage across capacitor 250 is the desired V.sub.GS for driving transistor 295. In the preferred embodiment of the invention shown in FIG. 2, current mirror 220 receives the reference current I.sub.REF and generates the charging current I.sub.CHG from supply voltage source 215B to control the supply voltage V.sub.dd available for adjustable current driver circuit 200. In other implementations, the reference current I.sub.REF is applied directly to node 255 and directly charges capacitor 250.

(13) In accordance with the present invention, the near-instantaneous energy needed for driving transistor 295 is largely drawn from the charge stored on capacitor 250, rather than from a supply voltage source, which greatly reduces supply voltage spiking from the near-instantaneous current draw from the supply voltage source. The reduced supply voltage spiking reduces resistive and inductive noise spikes in other pre-driver circuits as well. Charge drawn from capacitor 250 is replenished by I.sub.CHG while driving transistor 295 acts as an open switch. I.sub.CHG is a similar order of magnitude as I.sub.REF and is sufficient to recharge capacitor 250 in between pulses of transistor 295 despite its much smaller magnitude. To illustrate using an example, the driving current I.sub.DRV pulses every microsecond (s), and driving transistor 295 acts as a closed switch for 5 ns. I.sub.CHG charges capacitor 250 over the intervening 995 ns before the next pulse of driving current I.sub.DRV.

(14) Pulse controller 270 is connected at its input to node 255 and at its output to the gate terminal of driving transistor 295 at node 290, and receives a control signal CTL 205. Controller 270 includes driver 275 and transistors 280 and 285. Driver 275 receives CTL 205 and is connected to the gate terminals of transistors 280 and 285. The drain terminal of transistor 280 is connected to node 255, and the source terminal of transistor 280 is connected to the gate terminal of driving transistor 295 at node 290. The drain terminal of transistor 285 is connected to the gate terminal of driving transistor 295 and the source terminal of transistor 280 at node 290.

(15) When CTL 205 indicates driving transistor 295 should be turned on and the driving current I.sub.DRV generated, transistor 285 acts as an open switch, disconnecting the gate terminal of driving transistor 295 from ground 210. Transistor 280 acts as a closed switch, connecting the gate terminal of transistor 295 to capacitor 250 at node 255. Charge stored in capacitor 250 increases the voltage on the gate terminal of driving transistor 295 above its threshold voltage V.sub.Th, causing it to turn on and generate a driving current I.sub.DRV proportional to I.sub.REF. When CTL 205 indicates driving transistor 295 should be turned off, transistor 280 acts as an open switch, disconnecting the gate terminal of driving transistor 295 from capacitor 250. Transistor 285 acts as a closed switch, connecting the gate terminal of driving transistor 295 to ground 210, and causes the gate voltage of driving transistor 295 to quickly decrease to ground.

(16) The drain terminal of driving transistor 295 is connected to a second supply voltage source 215A, which provides a supply voltage V.sub.HV that is much higher than the supply voltage V.sub.dd from supply voltage source 215B. The source terminal of driving transistor 295 is connected to ground 210. The driving current I.sub.DRV is drawn from the second supply voltage source 215A.

(17) In some implementations, a resistor 260 is connected to node 290 and ground 210 as a safety feature, in the event pulse controller 270 malfunctions and causes driving transistor 295 to be turned on for more than a predetermined safety threshold length of time. Resistor 260 discharges capacitor 250 to zero over a period of time, in response to CTL 205 or pulse controller 270 indicating driving transistor 295 is to be turned on for more than the safety threshold length of time. By discharging capacitor 250 over time, resistor 260 reduces the gate voltage of driving transistor 295 below its threshold voltage V.sub.Th, turning off driving transistor 295 and stopping flow of driving current I.sub.DRV. The resistance of resistor 260 is chosen to implement the desired safety threshold length of time before driving transistor 295 is turned off.

(18) As discussed previously herein, the reference current I.sub.REF is highly scaled down compared to the I.sub.REF input to current driver circuit 100 shown in FIG. 1. The much larger driving current I.sub.DRV is drawn from the much larger supply voltage source 215A and is achieved based on the relative sizes of transistors in current mirror 220 compared to driving transistor 295. For example, transistors 235 and 240 are substantially the same size, and driving transistor 295 is approximately 30,000 times the size of transistors 235 and 240. A driving current I.sub.DRV equal to 30 A is achieved with a reference current I.sub.REF of only 1 mA. Thus, a small reference current I.sub.REF is sufficient to generate a driving current I.sub.DRV several orders of magnitude larger that slews on the order of tens of GA/second with a reduced impact on the supply voltage available in the integrated circuit. Varying the magnitude of I.sub.REF proportionally varies the magnitude of I.sub.DRV.

(19) Returning to the exemplary implementation of adjustable current driver circuit as part of a lidar system, varying the magnitude of I.sub.REF proportionally varies the magnitude of IDR and the corresponding intensity of light emitted by the laser diode driven by I.sub.DRV. Thus, the lidar system can carefully control the light intensity based on the range of distances it is imaging and environmental conditions. I.sub.DRV can be dynamically adjusted as the lidar system images the environment to accommodate changes in the environmental conditions as well. Dynamic adjustment of I.sub.DRV enables the lidar system to adjust for different distances, maintain a constant light intensity over different environmental and process conditions, and/or modulate the light intensity over time to implement a time-of-flight imaging process.

(20) The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.