Anodic Bonding of a Substrate of Glass having Contact Vias to a Substrate of Silicon

Abstract

A semiconductor device comprising a first substrate (100) including silicon may include a bondable passivation (200) made of a bondable material, especially a glass material; at least one contact via (210) extending through the passivation and contacting a region of the first substrate (100); an interface (204) created by anodic bonding between the substrate including silicon and the bondable passivation (200), wherein silicon-oxygen-silicon bonds are formed in the interface in order to provide adhesion between the passivation (200) and the substrate (100)

Claims

1-82. (canceled)

83. A semiconductor device comprising a first substrate (100) including silicon, and comprising: a bondable passivation (200) made of a bondable material, especially a glass material; at least one contact via (210) extending through the passivation and contacting a region of the first substrate (100); an interface (204) created by anodic bonding between the substrate including silicon and the bondable passivation (200), wherein silicon-oxygen-silicon bonds are formed in the interface in order to provide adhesion between the passivation (200) and the substrate (100).

84. The semiconductor device according to claim 83, wherein the bondable material of the passivation is a glass material.

85. The semiconductor device according to claim 83, wherein the bondable passivation material (200) is an alkaline glass material having an adapted thermal expansion coefficient, or is a glass material, or is a glass-like material.

86. The semiconductor device according to claim 83, wherein the bondable passivation material becomes sufficiently conductive under the influence of a temperature within a range of 300 C. to 500 C., thereby enabling ion migration and thus a current flow through the passivation material.

87. The semiconductor device according to claim 83, wherein an upper electrode (3) or an electrode wafer (300) having recesses therein is provided, wherein the recesses are arranged above the through vias (210) of the passivation (200).

88. The semiconductor device according to claim 87, wherein, for enabling a bonding process, the upper electrode (3) or the electrode wafer (300) does not contact the through vias (210) so that no short circuit occurs.

89. The semiconductor device according to claim 88, wherein contacting the semiconductor wafer (100) is achieved: either via a lower bottom plate (2), or by an edge pin (5) via recesses in the electrode wafer (300) and the passivation (200) accommodating the same.

90. The semiconductor device according to claim 83, wherein the lower semiconductor wafer (100) can be contacted by the lower bottom plate (2) or the edge pin (5), especially when the edge pin (5) reaches through a recess in an electrode wafer (300).

91. The semiconductor device according to claim 90, wherein the contacting is achieved when the edge pin (5) reaches through the recess in the electrode wafer (300).

92. The semiconductor device according to claim 83, wherein an electrode wafer (300) is provided that comprises insulating fences in order to separate potentials for contacting the passivation (200) and for contacting the lower semiconductor wafer (100) via the through via (210).

93. The semiconductor device according to claim 92, wherein the fences are realized by a glass-silicon-composite wafer including a high-resistance glass.

94. The semiconductor device according to claim 93, wherein the electric contacting of the electrode wafer is achieved via a structured metal layer on the wafer backside.

95. The semiconductor device according to claim 94, wherein the electric contacting of the electrode wafer is achieved via the structured metal layer on the wafer backside and is separated from other portions of the wafer having a structured electric insulating layer or a high-resistance barrier layer in order to prevent a current flow.

96. The semiconductor device according to claim 95, wherein the preventing of a current flow is preventing a short circuit.

97. The semiconductor device according to claim 83, wherein a metal layer on the passivation (200) is structured such that there is no metal in the position(s) of the contact via(s) (210).

98. The semiconductor device according to claim 83, wherein the structured metal layer is located on the passivation (200) formed as a glass substrate.

99. The semiconductor device according to claim 97, wherein the metal layer can be contacted by a center pin, and the first substrate (100) can be contacted via the lower bottom plate (2), or by the edge pin (5) via a recess in the passivation (200).

100. An arrangement for contacting a semiconductor device having a first substrate (100) including silicon and a bondable passivation (200) made of a bondable glass material, the arrangement comprising: at least one contact via (210) extending through the passivation in order to contact a region of the first substrate (100); an interface (204) created by anodic bonding between the substrate including silicon and the bondable passivation (200), wherein silicon-oxygen-silicon bonds are formed in the interface in order to provide adhesion between the passivation (200) and the substrate (100).

101. The arrangement according to claim 100, wherein an upper electrode (3) or an electrode wafer (300) having recesses therein is provided, wherein the recesses are arranged above the through vias (210) of the passivation (200).

102. The arrangement according to claim 100, wherein, for enabling a bonding process, the upper electrode (3) or the electrode wafer (300) does not contact the through vias (210) so that no short circuit occurs.

103. The arrangement according to claim 100, wherein, for contacting: a lower bottom plate (2) is provided, or an edge pin (5) is provided via recesses in the electrode wafer (300) and the passivation (200) accommodating the same in order to achieve contacting the semiconductor wafer (100).

104. The arrangement according to claim 100, wherein the arrangement is formed such that the lower semiconductor wafer (100) can be contacted by the lower bottom plate (2) or the edge pin (5), when the edge pin (5) reaches through a recess in a or the electrode wafer (300).

105. The arrangement according to claim 100, wherein a metal layer on the passivation (200) can be contacted by a center pin, and the first substrate (100) can be contacted via the lower bottom plate (2), or by the edge pin (5) via a recess in the passivation (200).

106. The arrangement according to claim 105, wherein the metal layer is structured such that there is no metal in the position(s) of the contact via(s) (210).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The embodiments of the invention are illustrated and not in a way that transfers or incorporates limitations from the Figures into the patent claims. Same reference numerals in the Figures denote similar elements. Features or properties of the following examples are not to be considered or understood as essential to the claimed invention unless explicitly stated otherwise. The claims have precedence and the examples explain or supplement them.

[0048] FIG. 1A is prior art and schematically shows a cross-sectional view of a bonding device 1 for anodically bonding a glass substrate 200 and a silicon wafer 100 using conventional techniques.

[0049] FIG. 1B is prior art and shows a schematic cross-sectional view of an arrangement in which a glass substrate 200 having contact vias 210 is to be connected with a silicon wafer 100, however, wherein the required conditions for reliable bonding are not achieved due to relatively low-resistance current paths (through the contact vias).

[0050] FIG. 2 is an example of the invention and schematically shows a cross-section of a composite of a glass substrate 200 having contact vias and a substrate 100 including a semiconductor material. Said substrates are to be connected in a bonding device, wherein the contact vias are covered, at least in part, by a layer provided on the glass substrate.

[0051] FIG. 3 is a further example of the invention and shows a view of a composite of a glass substrate having contact vias 210, an electrode substrate and a substrate including a semiconductor material in a bonding device, wherein the contact vias are covered by the electrode substrate.

DETAILED EXPLANATION OF THE DRAWINGS

[0052] The above disclosed concept for connecting a glass substrate having contact vias and a substrate including a semiconductor material on the basis of the anodic bonding method is now explained further with reference to FIGS. 2 and 3, wherein reference may also be made to prior art FIGS. 1A and 1B, if necessary.

[0053] FIG. 2 schematically shows a cross-sectional view of a composite of a substrate 100 that is, for example, a substrate including a semiconductor material, e.g. silicon, in which not shown device components are realized in the form of mechanical, and/or optical, and/or electrical sensor components, transistors, resistors or the like, wherein, in particularly advantageous embodiments, mechanical sensor components are provided, for example, in the form of cantilevers, membranes or the like, the deformation of which is used for evaluating corresponding physical quantities. As explained in the beginning, appropriate recesses or cavities to be suitably covered are often created in the substrate 100 for this purpose. For example, the substrate 100 can already comprise such a substrate that is provided on a backside 101 and is or has been connected with a starting material of the substrate 100, for example, subsequently or previously thereto, using the technique described above with reference to FIG. 1A.

[0054] As explained above, it is further advantageous to provide a housing component on a wafer basis, wherein a glass substrate 200 can be anodically bonded in which contact vias 210 are formed that are filled with any suitable conductive material, e.g. with silicon, a metal, a conductive barrier material/metal or the like.

[0055] By connecting the substrates 100 and 200, the housing components and electrical connections in the form of the contact vias 210 that make a connection with a surface 102 of the substrate 100 to be bonded on the one side and provide possible connections with further peripheral components on the other side which are also to be contacted in the substrate 200 on a wafer basis or after separating the corresponding chip areas. However, as opposed to the illustrations in FIGS. 1A and 1B, the contact vias 210 of the substrate 200 are covered by a suitable material so that a high-resistance path is created between the corresponding contact vias 210 and a contact point for the potential to be applied. This high-resistance path is schematically illustrated by 205.

[0056] In one embodiment variant, at least a part of the high-resistance path 205 is formed by a residual layer 220 that is formed on the substrate 200 above the respective contact vias 210. The residual layer 220 can be provided, for example, in the form of a bondable glass material having the same or at least very similar properties as the bondable glass material of the substrate 200 in which the contact vias 210 are embedded.

[0057] Examples of bondable glass materials include Borofloat33 by Schott, Pyrex 7740 by Corning, or SD2 by Hoya which combine low conductivity with temperature shock resistance.

[0058] In other embodiments, a different material can be used, provided that this material is compatible with the further conditions during the anodic bonding method to be performed.

[0059] In the illustrated embodiment, a thickness 221 of the residual layer 220 is set such that suitable parameter values for pressure and temperature as well as the voltage to be applied can be determined throughout the anodic bonding method.

[0060] Appropriate parameters can be determined, for example, by monitoring the current flow through the high-resistance path 205 for correspondingly selected further process parameters (at a constant voltage), e.g. pressure and temperature, so that, on the one hand, a selection of suitable parameters in the form of temperature and pressure can be performed, when using test substrates, on the basis of the path of the current that increases at the onset of ion migration and then decreases again when the width of the depletion zone (see FIG. 1A) increases as a consequence of the increasing lack of ions in the depletion zone. On the other hand, the current monitoring can also be performed during the actual process for product substrates as an endpoint control of the anodic process. For example, an appropriate analysis of the interface between the substrates 100 and 200 can be performed with respect to a suitable current path indicating a successful bonding of or between the substrates 100 and 200. A quality of the corresponding interface is determined and used for the selection of suitable process parameters.

[0061] In some embodiments, an electrode layer 310, e.g. in the form of aluminum or the like, which can be contacted by a suitable electrode 4 of the bonding device 1, is provided in order to improve the uniformity of the initial electric field across the substrate 200. At the same time, the electrode layer 310, which also serves the purpose of potential distribution, can further have a diffusion inhibiting-effect, for example, on sodium ions so that an adverse effect on the bonding plate 3 of the device 1 due to Na contamination can be significantly reduced at the onset of ion migration. For example, an aluminum layer having a thickness of several 100 nm can be efficiently used in order to obtain an effective potential distribution and a diffusion-inhibiting effect. The electrode layer 310 can be applied in the production of the residual layer 220 so that one or more additional deposition steps are performed in the production of the substrate 200 in order to temporarily apply the electrode layer or the potential-distribution layer 310 to the substrate 200.

[0062] In further advantageous embodiment variants, the contacting to the bonding device 1 can be performed by using an electrode substrate which is schematically denoted by 300 herein and is made of a conductive material and thus serves as an interface between the bonding plate 3 and the substrate 200 containing the residual layer 220. For example, a non-processed silicon wafer can be used as the electrode substrate 300 in order to thus enable a thermal, electrical and mechanical coupling of the substrate 200 to the bonding plate 3. In this embodiment variant, the thickness 221 of the layer 220 is selected such that it is sufficient for providing the high-resistance path 205, and the electrode substrate 300 is incorporated into the composite instead of or in addition to the electrode layer 310 and serves as a contact to the bonding plate 3.

[0063] In other embodiment variants, the electrode substrate 300 is provided in such a way that it forms a portion of the high-resistance path 205, as schematically indicated by the dashed line, so that the residual layer 220 serves the purpose of mechanically covering the contact vias 210 and provides the desired high resistance 205 only in cooperation with a further material of the electrode substrate 300.

[0064] For example, a bondable glass material is provided in the electrode substrate 300, which material can have, for example, similar or the same properties as the glass material of the substrate 200 and/or of the residual layer 220 on which the electrode layer 310 is provided, e.g. in the form of aluminum, in order to make contact with the electrode 4.

[0065] Dividing the high-resistance path 205 into the residual layer 220 and the electrode substrate 300 offers the advantage that the residual layer 220 contributes to a high mechanical robustness of the contact vias 210, but can be efficiently removed in the further course of the processing, i.e. after connecting the substrates 100 and 200, for example, by means of a simple grinding operation. On the other hand, the electrode substrate 300 can be reused in further bonding processes so that efficiency can be enhanced on the whole. The residual layer prevents bonding.

[0066] In further embodiment variants, the material of the electrode substrate 300 beneath the electrode layer 310 can be a different material exhibiting the required properties with respect to thermal robustness, electric strength or the like so that the high-resistance path 205 is provided without tending to make a bond with the contact vias 210, if the vias comprise a material which would otherwise tend to make a bond with glass, as is the case with silicon, aluminum or the like.

[0067] Also for this variant, i.e. the use of the electrode substrate 300 together with an insulating material providing the high-resistance path 205, suitable process parameters can be selected in connection with the electrode layer 310, as described above. In particular, an appropriate adjustment can be made on the side of the electrode substrate 300, e.g. when the residual layer 220 has the same thickness 221, wherein aspects of reusability of the electrode substrate 300 can also be taken into consideration when selecting suitable process parameters and a suitable structure of the electrode substrate 300.

[0068] When performing the anodic bonding process by means of the device 1, a potential is thus applied across the composite of the substrates 100 and 200 and, if provided, the substrate 300, wherein, for example, the electrode layer 310 and the substrate 100 serve as suitable conductive materials for connection to the corresponding electrodes. In this case, a conventional electrode arrangement can be chosen, as schematically shown, for example, in FIGS. 1A and 1B.

[0069] In the shown variant, the contacting of the composite is performed such that, for example, the electrode 4 is provided that makes contact with the electrode layer 310 in an appropriate position, whereas an electrode 5 of the bonding device 1 is arranged such that contacting of the surface 102 to be treated is possible.

[0070] However, the center pin 4 does not have to be used, rather the entire upper bonding plate 3 can be used as an electrode.

[0071] For example, the two live electrodes 4 and 5 (also referred to as center pin and edge pin) enable contacting of the substrate composite from the same direction, from above in FIG. 2. For this purpose, the bonding plate 3 as well as the substrate 200 and the electrode substrate 300, if provided, comprise a suitable recess 4a or 5a, for example, at the edge of the disk-shaped substrates so that the electrode 5 can be reliably moved past the substrates 300 and 200 while maintaining a sufficient safety distance. The bonding plates 3 and 2 exert a pressure in the above-mentioned way and heat the composite to a temperature so that, after applying the suitable voltage, the corresponding ion migration starts, the course of which can be monitored as described above in order to determine the end of the bonding process at the interface between the substrate 100 and the substrate 200 (see also FIG. 1A).

[0072] It should be noted that, in the shown arrangement of the bonding device 1, the electrode 4 is to be connected with the more negative potential in order to initiate the migration of the positive ions towards the electrode layer 310, whereas the more positive potential is to be connected with the electrode 5 in order to thus initiate migration of negative oxygen ions.

[0073] After completing the bonding of the substrates 200 and 100, semiconductor devices are thus created on a wafer basis that comprise the corresponding components in and/or on the substrate 100 together with corresponding housing components formed by the glass material substrate 200 together with the contact vias 210. The corresponding semiconductor devices thus also have an interface, for example, in accordance with the interface 204 of FIG. 1A, which includes corresponding SiOSi bonds when silicon is used as a semiconductor material for the substrate 100, whereby a firm connection with the housing substrate is obtained. The glass material of the substrate 200 is connected with the contact vias 210 in the region of the surface 102 belonging to a corresponding device component.

[0074] After successfully connecting the substrates 100 and 200, the process can be continued, for example, by removing the residual layer 220 which can be performed by grinding or the like. In this way, the contact vias 210 are exposed and can be used for further processes.

[0075] As explained above, a low thickness 221 of the residual layer 220 in this production phase has the advantage that the contact vias 210 can be exposed with relatively little effort, while the release of the electrode substrate 300 from the composite of substrates 100 and 200 can be performed mechanically in a simple manner, since a bond between the contact vias 210 and the material of the electrode substrate 300 is prevented, as described above.

[0076] FIG. 3 shows a schematic cross-sectional illustration, wherein a composite of the substrate 100 and the substrate 200 is to be bonded by means of the bonding device 1. In contrast to the embodiment illustrated in FIG. 2, the substrate 200 comprises the contact vias 210 in a form in which they would typically tend to make a bond with the glass material during an anodic bonding process. For example, the contact vias can be exposed in the glass substrate 200, as described above in the conventional method of FIG. 1B. In particular, contact surfaces in the form of aluminum surfaces on the contact vias 210 can already be provided so that a further processing at a later stage can be made more efficient.

[0077] In this embodiment variant, the glass substrate 200 is covered by the electrode substrate 300 comprising an insulating material, for example, in the form of a bondable glass material in order to create the required high resistance 205 between the electrode layer 310 that is connected with the electrode 4 and the respective contact vias 210. The insulating material of the electrode substrate 300 is chosen such that the high-resistance path 205 is obtained for a given set of parameters regarding voltage, pressure and temperature, as explained above.

[0078] In case there is no conductive path at all in the electrode wafer, a capacitive coupling can be incorporated. The electrode substrate (the electrode wafer 300) is not conductive and the electric field for anodic bonding is created by the capacitive coupling.

[0079] However, when using a bondable glass material for the electrode substrate 300, there is the risk of a bond of the glass material with the material of the contact vias 210, as explained above, especially when the vias are provided with an aluminum contact surface. A bonding to the through via or to pads on the through via may take place.

[0080] In order to prevent the undesired bonding, a barrier layer 320 is provided in the electrode substrate 300, which barrier layer is configured such that at least the diffusion of oxygen ions is stopped so that no or at least no noteworthy bonding of oxygen to the material of the contact vias 210 occurs. The barrier layer 320 can be applied in the form of any material that does not affect the high resistance of the path 205, but nevertheless allows a desired current flow and has the desired inhibitory effect on oxygen diffusion.

[0081] For example, silicon nitride is a material that, when having a thickness of some 100 nm to some m, is suited to at least inhibit the diffusion of oxygen, while allowing a diffusion of positive sodium ions to a sufficient extent in order to thus create the conditions at the interface between the substrates 100 and 200, as explained above.

[0082] The silicon nitride is supposed to actually prevent the diffusion of oxygen only. In practice it also absorbs the sodium ions (sodium depletion), however, this does not affect the actual bonding process in an appreciable manner. Whether the Na.sup.+ ions are stopped by the barrier layer on the electrode wafer or are able to diffuse therethrough, has no effect on the actual bonding process. The bonding process can then be performed in the same way as described above.

[0083] In the two embodiment variants of FIGS. 2 and 3, it can be achieved that an excessive sodium contamination of the glass substrate 200 on the top side thereof is prevented, for example, due to the fact that the diffusion takes place into the residual layer 220 and, if provided, possibly into the material of the electrode substrate 300 so that a corresponding desired high sodium concentration in the glass material of the substrate 200 is prevented after removal of the residual layer 220. On the other hand, the diffusion of sodium ions into the bonding plate 3 can be effectively suppressed by the layer 310 so that a longer reliability and consistency of the properties of the bonding plate 3 can be achieved.

[0084] The same applies to the embodiment variant of FIG. 3 in which, for example, the sodium ions diffuse into the electrode substrate 300 where their further diffusion into the bonding plate 3 is impeded by the layer 310. The possible enrichment of sodium in the material of the electrode substrate 300 can, for example, generally be taken into consideration from the start when constructing the substrate, e.g. in the form of the layer thickness of the glass material or the like so that the reuse rate can be correspondingly high even for the electrode substrate 300.

[0085] Respective glass substrates 200 can be produced, for example, by etching silicon substrates in such a manner that columns corresponding to the contact vias are left behind. A glass substrate is adhered to this etched surface by anodic bonding as is described, for example, in connection with FIG. 1A so that the glass substrate adheres to the columns of the silicon substrate. Subsequently thereto, the glass can be thermally treated in an appropriate manner so that it fills the interspaces of the silicon columns in a flowable manner, thereby reliably enclosing the columns and thus the vias by the glass material. When levelling the glass material that was flowably deformed before and removing excess material, a processing can be performed such that a desired residual layer, e.g. the layer 220, is maintained which meets the requirements made to the high-resistance path 205, as described above. When required, the layer 310 can be applied by known methods. In other variants, the properties of the residual layer 220 are supplemented by the additional electrode substrate 300, as described above in connection with FIG. 2.

[0086] Common methods can be used for producing the residual layer 220 so that the desired residual layer is left behind when the glass material is leveled after filling and enclosing the shaping silicon columns so that no substantial additional effort is created.

[0087] In the method described with reference to FIG. 2, the glass substrate can be produced in a conventional manner, without any further process steps being required.

[0088] On the other hand, the electrode substrate 300 of FIG. 3 can be produced in a simple manner by known depositing processes so that the effects on the entire process sequence are low owing to the reusability of the electrode substrate 300. All in all, the anodic bonding process for bonding the glass substrate to the contact vias exhibits high robustness and can thus be effectively used for the mass process.

[0089] A robust approach for anodic bonding of substrates having contact vias (or pads on the contact vias) is suggested, which substrates can be made of bondable materials, e.g. silicon, aluminum or the like. Owing to the reliable anodic bonding of the glass material having the contact vias, semiconductor devices can be provided with housing components on a wafer basis using a robust anodic bonding process so that a very firm bond, a high tightness and a high degree of parallelism of the bonded substrates with respect to each other is ensured, wherein the temperature stress during the bonding process is CMOS-compatible so that no limitations are required in the production of CMOS components on the semiconductor substrate. Thus, the properties of a glass material as a passivating housing material can also be fully utilized in conjunction with the contact vias on the basis of a robust bonding method, such as the transparency of the glass housing components in an optical inspection of the components after adding the housing components, and the good aptitude for high-frequency applications due to the dielectric properties of the glass material.