METAL CHALCOGENIDE DEVICE AND PRODUCTION METHOD THEREFOR

Abstract

The present invention relates to a chalcogenide device and particularly to a metal chalcogenide device using transition metal chalcogenides as electrodes and a production method therefor. The metal chalcogenide device according to the present invention may comprise: a substrate; an oxide layer positioned on the substrate; a first conductive metal chalcogenide layer positioned on the oxide layer; and first and second electrodes, which are positioned apart from one another on the metal chalcogenide layer and comprise metal chalcogenides.

Claims

1. A metal chalcogenide device comprising: a substrate; a metal chalcogenide layer with a first conductivity disposed on the substrate; and a first electrode and a second electrode spaced from each other on an upper surface or a side surface of the metal chalcogenide layer, the first electrode and the second electrode comprising metal chalcogenide.

2. The metal chalcogenide device according to claim 1, wherein the first conductivity is p-type.

3. The metal chalcogenide device according to claim 1, wherein at least one of the first electrode and the second electrode comprises Nb.

4. The metal chalcogenide device according to claim 1, wherein the metal chalcogenide layer comprises MoS.sub.2.

5. The metal chalcogenide device according to claim 1, wherein at least one of the first electrode and the second electrode comprises NbS.sub.2.

6. The metal chalcogenide device according to claim 1, wherein the metal chalcogenide layer contacts at least one of the first electrode and the second electrode in a side surface direction.

7. The metal chalcogenide device according to claim 1, wherein a diffusion area having a relatively high first conductivity is disposed between the metal chalcogenide layer and at least one of the first electrode and the second electrode.

8. The metal chalcogenide device according to claim 1, further comprising: a gate insulator disposed on the metal chalcogenide layer; and a gate electrode disposed on the gate insulator.

9. A metal chalcogenide device comprising: a substrate; a channel layer comprising a p-type MoS.sub.2 thin film disposed on the substrate; a first electrode connected to the channel layer at a first position in a side surface direction, the first electrode comprising Nb; a second electrode connected to the channel layer in a side surface direction at a second position spaced from the first position, the second electrode comprising Nb; and a diffusion area disposed at at least one position of between the first electrode and the channel layer, and between the second electrode and the channel layer, the diffusion area being a region where a Nb atom diffuses into the channel layer.

10. The metal chalcogenide device according to claim 9, wherein the diffusion area has a higher conductivity than that of the channel layer.

11. The metal chalcogenide device according to claim 9, wherein the Nb atom is used as a dopant in the channel layer.

12. The metal chalcogenide device according to claim 9, further comprising: a gate insulator disposed on the channel layer; and a gate electrode disposed on the gate insulator.

13. A method of manufacturing a metal chalcogenide device comprising: forming a first metal chalcogenide layer on a semiconductor substrate with a first conductivity where an oxide layer is disposed; forming metal patterns spaced from each other at a position where the metal patterns contact the first metal chalcogenide layer; and supplying a chalcogen-containing gas to the metal pattern to form the metal pattern into an electrode comprising a second metal chalcogenide.

14. The method according to claim 13, wherein the first metal chalcogenide layer comprises MoS.sub.2.

15. The method according to claim 13, wherein the metal pattern comprises Nb.

16. The method according to claim 13, wherein the forming the metal pattern into the electrode comprises allowing the first metal chalcogenide layer to have the first conductivity by an atom contained in the metal pattern.

17. The method according to claim 13, wherein the first metal chalcogenide layer contacts the metal pattern in a side surface direction.

18. The method according to claim 13, wherein the forming the metal pattern comprises: forming a mask pattern having an open part where the metal pattern is to be formed, on the first metal chalcogenide layer; removing the opened first metal chalcogenide layer using the mask pattern; forming the metal pattern in the area from which the first metal chalcogenide layer is removed; and removing the mask pattern.

19. The method according to claim 18, wherein the first conductivity is p-type.

20. The method according to claim 13, further comprising: forming a gate insulator between the metal patterns; and forming a gate electrode on the gate insulator.

Description

DESCRIPTION OF DRAWINGS

[0031] FIG. 1 is a schematic sectional view illustrating a metal chalcogenide device according to an embodiment of the present invention.

[0032] FIG. 2 is a schematic sectional view illustrating a metal chalcogenide device according to another embodiment of the present invention.

[0033] FIGS. 3 to 5 are sectional views illustrating a process of manufacturing a metal chalcogenide device according to an embodiment of the present invention.

[0034] FIGS. 6 to 10 are sectional views illustrating a process of manufacturing a metal chalcogenide device according to another embodiment of the present invention.

[0035] FIGS. 11 to 14 are sectional views illustrating a process of manufacturing a metal chalcogenide device according to another embodiment of the present invention.

[0036] FIG. 15 is a graph showing a transfer curve of a metal chalcogenide device.

BEST MODE

[0037] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0038] However, the present invention allows various modifications and variations and specific embodiments thereof are exemplified with reference to the drawings and will be described in detail. The present invention should not be construed as limited to the embodiments set forth herein and includes modifications, equivalents and substitutions compliant with the spirit or scope of the present invention defined by the appended claims.

[0039] It will be understood that when an element such as a layer, area or substrate is referred to as being “on” another element, it may be directly on the element, or one or more intervening elements may also be present therebetween.

[0040] In addition, it will be understood that although terms such as “first” and “second” may be used herein to describe elements, components, areas, layers and/or regions, the elements, components. areas, layers and/or regions should not be limited by these terms.

[0041] In addition, it is not deemed that processes described in the present invention should be conducted in order. For example, when several steps are mentioned, the steps may not be performed in order.

[0042] A two-dimensional material grabs much attention as a next-generation material in the semiconductor industry. Among two-dimensional materials, MoS.sub.2, which is a transition metal chalcogen compound, exhibits direct transition type semiconductor properties in a single layer and has a bandgap of 1.8 eV. MoS.sub.2 is a potential material since it has a bandgap without any separate treatment process and exhibits n-type semiconductor characteristics.

[0043] However, MoS.sub.2 has a drawback of lower mobility than graphene which is another two-dimensional material. In addition, there is no established doping technology to implement p-type semiconductors essential to construct various device structures and circuits.

[0044] In order to apply MoS.sub.2 as a next-generation electronic and photoelectric device to a variety of invention fields such as flat panel displays and solar cells, technology to improve charge mobility and implement p-type semiconductors is required.

[0045] The present invention provides a p-type MoS.sub.2 device which is manufactured by using a top-surface or side-surface contact method to reduce a contact resistant and utilizing NbS.sub.2 as another transition metal chalcogen compound as an electrode and a method of manufacturing the same.

[0046] NbS.sub.2, like MoS.sub.2, which is a (transition) metal chalcogen compound, has a similar crystal structure to MoS.sub.2 However, NbS.sub.2 has properties of a conductor, unlike MoS.sub.2. The present invention suggests formation of composite structures using transition metal chalcogen compounds having various properties and will be expected to greatly affect studies on composite structures between various transition metal chalcogen compounds in the future.

[0047] Since NbS.sub.2 and MoS.sub.2 have similar crystal structures, when NbS.sub.2 is used as an electrode, contact resistance can be reduced, as compared to when a general metal is used. When the side-surface contact method suggested in the present invention is further used, contact resistance can be further reduced.

[0048] High contact resistance is a determining factor limiting performance of an device. The way to reduce contact resistance suggested in the present invention will be expected to play an important role in improving device performance of MoS.sub.2 in the future.

[0049] Meanwhile, doping is a technology which should be established in order to apply MoS.sub.2 to the real industry. MoS.sub.2 has n-type semiconductor properties in itself and is doped with a p-type semiconductor when a small amount of Nb atom is added to it.

[0050] The present invention suggests a manufacturing method which includes depositing a Nb metal in a part where an electrode is connected to MoS.sub.2 and diffusing a small amount of Nb into MoS.sub.2 while synthesizing NbS.sub.2 at high temperature. Technology to manufacture both polarities of the MoS.sub.2 semiconductor is suggested by a method of doping MoS.sub.2, an n-type semiconductor, with a p-type semiconductor.

[0051] The present invention described above will be expected to be actively used in research related to a variety of devices and circuits using MoS.sub.2. Specifically, the present invention will be expected to be essentially used to develop and study PN junction structures using n-type and p-type semiconductors and CMOS transistors, and furthermore, to manufacture optical sensors using two-dimensional materials, light emitting devices, photodetectors, photomagnetic memory devices, photocatalysts, flat panel displays, solar cells and the like as well as electronic and photoelectric devices based on next-generation transparent and flexible semiconductors.

[0052] FIG. 1 is a schematic sectional view illustrating a metal chalcogenide device according to an embodiment of the present invention.

[0053] Referring to FIG. 1, the metal chalcogenide device includes a metal chalcogenide layer 30 with a first conductivity disposed on a substrate 10.

[0054] In addition, a first electrode 40 and a second electrode 50, which each include metal chalcogenide, are disposed on the metal chalcogenide layer 30 such that they are spaced from each other.

[0055] The substrate 10 may be a semiconductor substrate, for example, a silicon (Si) semiconductor substrate. In this case, an oxide layer 20 may be disposed between the substrate 10 and the metal chalcogenide layer 30 and the oxide layer 20 may be a silicon oxide (SiO.sub.2) layer.

[0056] The substrate 10 may include an insulating material such as sapphire or glass. In this case, a separate oxide layer may not be disposed.

[0057] The first conductivity may be a p-type conductivity. Accordingly, a metal chalcogenide layer having p-type conductivity can be acquired. In this case, the substrate 10 may also be a semiconductor substrate with p-type conductivity.

[0058] Here, the metal chalcogenide layer 30 may include a thin film, for example, a MoS.sub.2 thin film, including a single atomic layer or a plurality of atomic layers made of one kind of transition metal chalcogenide material.

[0059] Such a metal chalcogenide layer 30 may be used as a channel layer of a field effect transistor (FET) device made of a metal-oxide-semiconductor. In this case, the first electrode 40 may be used as a source electrode and the second electrode 50 may be used as a drain electrode. In addition, a separate metal electrode may be further provided on each of the first electrode 40 and the second electrode 50, and the metal electrode may be used as each of the source electrode and the drain electrode.

[0060] The semiconductor substrate 10 may be provided with a separate gate electrode. This device structure may constitute a back-gate type FET device.

[0061] Meanwhile, a gate insulator and a gate electrode (91, 90; see FIG. 14 may be further disposed on the metal chalcogenide layer 30. This device structure may constitute a top-gate type FET device.

[0062] The metal chalcogenide layer 30 may have chemical formula MX.sub.2, wherein M is any one of Mo, W, Tc, Re, Pd and Pt, and X is any one of S, Se and Te.

[0063] That is, the metal chalcogenide layer 30 may include at least one of MoSe.sub.2, WS.sub.2, WSe.sub.2, TiS.sub.2, TiSe.sub.2, TiTe.sub.2, HfS.sub.2, HfSe.sub.2, HfTe.sub.2, ZrS.sub.2, ZrSe.sub.2, ZrTe.sub.2, TcS.sub.2, TcSe.sub.2, TcTe.sub.2, ReS.sub.2, ReSe.sub.2, ReTe.sub.2, PdS.sub.2, PdSe.sub.2, PtS.sub.2, and PtSe.sub.2. Hereinafter, an example in which the metal chalcogenide layer 30 is a MoS.sub.2 layer will be described.

[0064] In this case, at least one of the first electrode 40 and the second electrode 50 may include a Group 5 metal chalcogenide material, that is, a Group 5 metal including at least one of V, Nb and Ta. In addition, at least one of the first electrode 40 and the second electrode 50 may include S, Se and Te bonded to the Group 5 metal.

[0065] For example, at least one of the first electrode 40 and the second electrode 50 may be NbS.sub.2. Hereinafter, an example in which the first electrode 40 and the second electrode 50 are formed using NbS.sub.2 will be described.

[0066] NbS.sub.2 is a two-dimensional material having a similar crystal structure to MoS.sub.2 NbS.sub.2 is classified as a transition metal chalcogen, like MoS.sub.2 but has a conductor property. In addition, when a Nb atom is partially added to MoS.sub.2, the Nb atom serves as a dopant so that MoS.sub.2 can exhibit p-type conductivity.

[0067] Since NbS.sub.2 has a similar crystal structure to MoS.sub.2, the contact resistance between the metal chalcogenide layer 30, and the first electrode 40 and the second electrode 50 is reduced, so that some Nb atoms of the first electrode 40 and the second electrode 50 diffuse into MoS.sub.2, and the p-type semiconductor can thus be manufactured. In this case, NbS.sub.2 constituting the first electrode 40 and the second electrode 50 may contact the top surface of the metal chalcogenide layer 30 (top-surface contact method) or the side surface of the metal chalcogenide layer 30 (side-surface contact method).

[0068] As such, since some of the Nb atoms contained in the electrodes 40 and 50 diffuse into MoS.sub.2 to constitute a p-type semiconductor, diffusion areas 43 and 53 having a higher conductivity can be disposed between the metal chalcogenide layer 30 and at least one of the first electrode 40 and the second electrode 50.

[0069] Through these diffusion areas 43 and 53, an energy band structure can be smoothly connected between the metal chalcogenide layer 30, and the first electrode 40 and the second electrode 50. That is, a band structure having a broad gradient can be formed.

[0070] Accordingly, an energy barrier therebetween is reduced so that flow of charges can be facilitated.

[0071] FIG. 1 illustrates a top-surface contact type metal chalcogenide device. Referring to FIG. 1, as mentioned above, the effect of p-type doping can be obtained by using NbS.sub.2 for electrodes 40 and 50 so that a p-type MoS.sub.2 device can be realized.

[0072] By providing an electrode using NbS.sub.2 having a similar crystal structure to this MoS.sub.2 layer, the metal chalcogenide device can have an effect of exhibiting reduced contact resistance as compared to a structure in which the metal chalcogenide device directly contacts the metal electrode. In addition, such a top-surface contact type offers an easy manufacture process, as compared to the side-surface contact type method.

[0073] FIG. 2 is a schematic sectional view illustrating a metal chalcogenide device according to another embodiment of the present invention.

[0074] FIG. 2 illustrates an example of a side-surface contact type metal chalcogenide device in which NbS.sub.2 constituting the first electrode 60 and the second electrode 70 contacts the side surface of the metal chalcogenide layer 30.

[0075] In such a structure, NbS.sub.2, a two-dimensional material, may contact the metal chalcogenide layer 30 made of MoS.sub.2, another two-dimensional material, in a side surface direction.

[0076] Since the two-dimensional material has a structure in which respective atoms are bonded and disposed on one plane, its bonding strength in a vertical direction is as low as an intermolecular bonding strength. However, interatomic bonds may be formed in a side surface direction and contact resistance between the electrodes 60 and 70, and the metal chalcogenide layer 30 can thus be significantly reduced.

[0077] Accordingly, contact in a parallel direction enabling easy charge transfer of the two-dimensional material leads to great improvement in the device performance of MoS.sub.2.

[0078] As mentioned above, since some of the Nb atoms contained in the electrodes 60 and 70 diffuse into MoS.sub.2 to form a p-type semiconductor, diffusion areas 63 and 73 having higher conductivity may be disposed between the metal chalcogenide layer 30 and at least one of the first electrode 40 and the second electrode 50.

[0079] Through these diffusion areas 63 and 73, an energy band structure can be smoothly connected between the metal chalcogenide layer 30, and the first electrode 60 and the second electrode 70. That is, a band structure having a broad gradient can be formed.

[0080] Accordingly, an energy barrier therebetween is reduced so that flow of charges can be facilitated owing to strong interatomic bonding.

[0081] The contents described with reference to FIG. 1 may be applied to other contents not described herein.

[0082] FIGS. 3 to 5 are sectional views illustrating a process of manufacturing a metal chalcogenide device according to an embodiment of the present invention. Hereinafter, a method of manufacturing a top-surface contact type metal chalcogenide device shown in FIG. 1 will be described with reference to FIGS. 3 to 5.

[0083] First, as shown in FIG. 3, a MoS.sub.2 layer 30 is formed on a substrate 10. In this case, a silicon oxide (SiO.sub.2) layer 20 may be disposed between the substrate 10 and the MoS.sub.2 layer 30.

[0084] Next, as shown in FIG. 4, a mask pattern having an electrode shape is formed on the MoS.sub.2 layer 30 using electron beam lithography or photolithography and Nb metal patterns 41 and 51 are then deposited thereon.

[0085] Next, as shown in FIG. 5, a chalcogen-containing gas, for example, H.sub.2S gas, is injected at high temperature using a low-pressure chemical vapor deposition system to synthesize NbS.sub.2 layers 42 and 52 from the Nb metal patterns 41 and 51. In this case, the synthesis process may be carried at a temperature ranging from 600° C. to 1000° C.

[0086] During the synthesis process shown in FIG. 5, some of the Nb atoms diffuse into MoS.sub.2 to produce a p-type MoS.sub.2 device shown in FIG. 1. In this case, the NbS.sub.2 layers 42 and 52 are formed as a first electrode 40 and a second electrode 50.

[0087] FIGS. 6 to 10 are sectional views illustrating a process of manufacturing a metal chalcogenide device according to another embodiment of the present invention. Hereinafter, a method of manufacturing a side-surface contact type metal chalcogenide device shown in FIG. 2 will be described with reference to FIGS. 6 to 10.

[0088] First, as shown in FIG. 6, a MoS.sub.2 layer 30 is formed on a substrate 10. In this case, as mentioned above, the substrate 10 may be a silicon (Si) substrate. In this case, a silicon oxide (SiO.sub.2) layer 20 may be disposed between the substrate 10 and the MoS.sub.2 layer 30.

[0089] Next, as shown in FIG. 7, a mask pattern 80 having an electrode shape is formed on the MoS.sub.2 layer 30 using electron beam lithography or photolithography. That is, a mask pattern 80 having an open part where the electrode is to be formed is obtained.

[0090] Next, as shown in FIG. 8, the MoS.sub.2 layer 30 disposed in the part where the electrode is to be formed is removed. Removal of the MoS.sub.2 layer 30 may be carried out by plasma etching. Through this process, electrode formation positions 63 and 73 where the electrodes contact the MoS.sub.2 layer 30 in a side surface direction can be acquired.

[0091] Next, as shown in FIG. 9, Nb metal patterns 61 and 71 are deposited at the electrode formation positions 63 and 73 from which the MoS.sub.2 layer 30 is removed. Next, the mask pattern 80 is removed.

[0092] Next, as shown in FIG. 10, a chalcogen-containing gas, for example, H.sub.2S gas, is injected at high temperature using a low-pressure chemical vapor deposition system to synthesize NbS.sub.2 layers 62 and 72 from the Nb metal patterns 61 and 61. In this case, the synthesis process may be carried at a temperature ranging from 600° C. to 1000° C.

[0093] During the synthesis process shown in FIG. 10, some of the Nb atoms diffuse into MoS.sub.2 to produce a p-type MoS.sub.2 device shown in FIG. 2. In this case, the NbS.sub.2 layers 62 and 72 are formed as a first electrode 60 and a second electrode 70.

[0094] FIGS. 11 to 14 are sectional views illustrating a process of manufacturing a metal chalcogenide device according to another embodiment of the present invention. Hereinafter, a method of manufacturing a side-surface contact type metal chalcogenide device will be described with reference to FIGS. 11 to 14.

[0095] First, as shown in FIG. 11, a Nb thin film 64 is deposited by electron beam (e-beam) deposition or sputtering on the substrate 10 and is then patterned such that the Nb thin film 64 includes a channel and an electrode.

[0096] Next, as shown in FIG. 12, a Mo thin film 31 is deposited by electron beam deposition or sputtering on the Nb thin film 64 and then patterned in the form of a channel.

[0097] Next, as shown in FIG. 13, a H.sub.2S gas is injected at high temperature using a low-pressure chemical vapor deposition system. In this process, the Nb thin film 64 is synthesized into NbS.sub.2 which forms electrodes 65 and 75, and the Mo thin film 31 disposed in the channel part is replaced and doped with Nb, and is synthesized into a p-type MoS.sub.2 thin film 32. In this case, the synthesis process may be carried at a temperature ranging from 600° C. to 1000° C.

[0098] Through this process, a side-surface contact type back-gate type device can be formed, as shown in FIG. 2. For this purpose, as mentioned above, a separate gate electrode may be provided under the substrate shown in FIG. 2.

[0099] Meanwhile, as shown in FIG. 14, a gate insulator 91 and a gate electrode 90 may also be formed on the p-type MoS.sub.2 thin film 32 to manufacture a top-gate type device. The gate electrode 90 may be formed using gold (Au).

[0100] As mentioned above, a separate metal electrode may be formed on the NbS.sub.2 electrodes 65 and 75. At this time, the metal electrodes may be connected through a via hole.

[0101] FIG. 15 is a graph showing a transfer curve of a metal chalcogenide device.

[0102] FIG. 15 shows a transfer curve of a metal chalcogenide device exhibiting properties of a p-type semiconductor.

[0103] Meanwhile, although embodiments according to the present invention disclosed in the specification and the drawings have been provided as specific examples for illustrative purposes, they should not be construed as limiting the scope of the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

INDUSTRIAL APPLICABILITY

[0104] According to the present invention, a metal chalcogenide layer having p-type conductivity can be provided and contact resistance of the electrode of the metal chalcogenide device can be greatly reduced.