Scanning drive circuit and display device including the same

Abstract

A display device including a display area including a plurality of pixel circuits, a peripheral area including a scanning circuit, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of third scanning lines, and a scanning circuit. The scanning circuit facing to a first side of the display area and configured to drive the pixel circuits via the first, the second and the third scanning lines.

Claims

1. A display device, comprising: a plurality of pixel circuits in a display area; a plurality of first scanning lines; a plurality of second scanning lines; and a plurality of third scanning lines; a scanning circuit facing to a first side of the display area and configured to drive the plurality of pixel circuits via the plurality of first scanning lines, the plurality of second scanning lines, and the plurality of third scanning lines: wherein the scanning circuit includes a plurality of stages and is configured such that: (a) a first stage of the plurality of stages receives an input pulse; (b) each of the plurality of stages receives a first pulse signal, a second pulse signal, and a third pulse signal; (c) the first pulse signal and the second pulse signal are rectangular waves having a same frequency and a phase difference between the first pulse signal and the second pulse signal is approximately 180 degrees, and (d) the scanning circuit supplies a plurality of output signals in response to the received first, seconds and third pulse signals, wherein each of the plurality of pixel circuits includes a write transistor, a drive transistor, a first switching transistor, a second switching transistor, a capacitor, and a light emitting element, and wherein a duration of a light emitting period of the respective light emitting element in each of the plurality of pixel circuits within one frame period is variably controlled by changing a width of the input pulse, a drive current is supplied from a voltage line to the light emitting element via the first switching transistor and the drive transistor, an initializing potential is supplied from an initializing voltage line to the capacitor via the second switching transistor, a data potential is supplied from a video signal line to the capacitor via the write transistor, a gate terminal of the first switching transistor is connected to the scanning circuit via one of the plurality of first scanning lines, a gate terminal of the write transistor is connected to the scanning circuit via one of the plurality of second scanning lines, and a gate terminal of the second switching transistor is connected to the scanning circuit via one of the plurality of third scanning lines; wherein the each of the plurality of stages is configured to receive a fourth pulse signal, the third pulse signal and the fourth pulse signal are rectangular waves having a same frequency and a phase difference between the third pulse signal and the fourth pulse signal is approximately 180 degrees.

2. The display device according to claim 1, wherein the first pulse signal and the second pulse signal are enable signals.

3. The display device according to claim 1, wherein the third pulse signal is a clock signal.

4. The display device according to claim 1, wherein the first pulse signal has a first number of pulses within said one frame period, the second pulse signal has a second number of pulses within said one frame period, the first number being a same number as the second number.

5. The display device according to claim 1, wherein the light emitting element includes an anode electrode, a light emitting layer, and a cathode electrode, the anode electrode is provided on a first insulation layer covering a plurality of drive circuits, and the cathode electrode is provided on a second insulation layer which is arranged on the first insulation layer, and the cathode electrode is connected to a second power-supply line via a first contact and a second contact.

6. The display device according to claim 5, wherein the first contact is formed in the first insulation layer, and the second contact is formed in the second insulation layer.

7. The display device according to claim 1, wherein the scanning circuit includes a plurality of shift registers configured to shift the input pulse, each of the plurality of shift registers corresponding to the each of the plurality of stages.

8. The display device according to claim 1, wherein changing the width of the input pulse does not affect a conductive state of the write transistor.

9. The display device according to claim 1, wherein changing the width of the input pulse does not affect a conductive state of the write transistor and the second switching transistor.

10. The display device according to claim 1, wherein a ratio between the light emitting period and a non-light emitting period is adjusted by changing the width of the input pulse.

11. A scanner circuit for driving a display device including a plurality of pixels having light emitting elements, the scanner circuit comprising: a plurality of stages, and output terminals connected to scanning lines each of which controls a duration of a light emitting period of the respective light emitting element in each of the plurality of pixels; wherein the plurality of the stages are configured such that: (a) a first stage of the plurality of stages receives an input pulse; (b) each of the plurality of stages receives a first pulse signal, a second pulse signal and a third pulse signal; (c) the first pulse signal and the second pulse signal are rectangular waves having a same frequency and a phase difference between the first pulse signal and the second pulse signal is approximately 90 degrees 180 degrees, and (d) the output terminals supply output signals in response to the received first, second, and third pulse signals, wherein the duration of the light emitting period of the respective light emitting element in each of the plurality of pixel circuits within one frame period is variably controlled by changing a width of the input pulse; wherein the each of the plurality of stages is configured to receive a fourth pulse signal, the third pulse signal and the fourth pulse signal are rectangular waves having a same frequency and a phase difference between the third pulse signal and the fourth pulse signal is approximately 180 degrees.

12. The scanner circuit according to claim 11, wherein the first pulse signal and the second pulse signal are enable signals.

13. The scanner circuit according to claim 11, wherein the third pulse signal is a clock signal.

14. The scanner circuit according to claim 11, wherein the first pulse signal has a first number of pulses within said one frame period, the second pulse signal has a second number of pulses within said one frame period, the first number being a same number as the second number.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram showing a configuration of a scanning drive circuit according to Embodiment 1 of the present invention;

(2) FIG. 2 is a conceptual block diagram showing a configuration of a display device, according to Embodiment 1 of the present invention, including the scanning drive circuit shown in FIG. 1;

(3) FIG. 3 is a schematic timing chart explaining an operation of the scanning drive circuit shown in FIG. 1;

(4) FIG. 4 is an equivalent circuit diagram showing a configuration of a drive circuit composing a display element belonging to an m-th row and an n-th column in the display device shown in FIG. 2;

(5) FIG. 5 is a schematic cross sectional view showing a structure of a part of a display element composing the display device shown in FIG. 2;

(6) FIG. 6 is a schematic timing chart explaining an operation for driving the display element belonging to the m-th row and the n-th column;

(7) FIGS. 7A to 7F are respectively equivalent circuit diagrams schematically showing ON/OFF states and the like of transistors in the drive circuit composing the display element belonging to the m-th row and the n-th column;

(8) FIG. 8 is a schematic timing chart explaining an operation of the scanning drive circuit of Embodiment 1 when a timing of falling of a start pulse is changed;

(9) FIG. 9 is a schematic timing chart explaining an operation of the display element belonging to the m-th row and the n-th column on the assumption that the start pulse rises between commencement and termination of a time period T.sub.9;

(10) FIG. 10 is a circuit diagram showing a configuration of a scanning drive circuit according to Comparative Example of Embodiment 1;

(11) FIG. 11 is a schematic timing chart explaining an operation of the scanning drive circuit of Comparative Example shown in FIG. 10 when a start pulse rises between commencement and termination of a time period T.sub.1, and falls between commencement and termination of a time period T.sub.5;

(12) FIG. 12 is a schematic timing chart explaining an operation of the scanning drive circuit of Comparative Example shown in FIG. 10 when the start pulse falls between commencement and termination of a time period T.sub.9;

(13) FIG. 13 is a circuit diagram showing a configuration of a scanning drive circuit according to Embodiment 2 of the present invention;

(14) FIG. 14 is a schematic timing chart explaining an operation of the scanning drive circuit of Embodiment 2 shown in FIG. 13;

(15) FIG. 15 is a schematic timing chart explaining an operation of the scanning drive circuit of Embodiment 2 when the timing at which the start pulse falls is changed;

(16) FIG. 16 is a circuit diagram showing a configuration of a scanning drive circuit according to Comparative Example of Embodiment 2;

(17) FIG. 17 is a schematic timing chart explaining an operation of the scanning drive circuit of Comparative Example shown in FIG. 16 when a start pulse rises between commencement and termination of a time period T.sub.1, and falls between commencement and termination of a time period T.sub.9;

(18) FIG. 18 is a schematic timing chart explaining an operation of the scanning drive circuit of Comparative Example shown in FIG. 16 when the start pulse falls between commencement and termination of a time period T.sub.17;

(19) FIG. 19 is an equivalent circuit diagram showing a configuration of a drive circuit composing a display element belonging to an m-th row and an n-th column in an existing display device having display elements two-dimensionally disposed in a matrix; and

(20) FIGS. 20A, and 20B to 20D are respectively a schematic timing chart of signals on an initialization control line, a scanning line and a display control line, and equivalent circuit diagrams schematically showing ON/OFF states and the like of six transistors composing the drive circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(21) The preferred embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings.

Embodiment 1

(22) A scanning drive circuit of the present invention, and a display device including the same will now be described based on Embodiment 1 thereof. The display device of Embodiment 1 is a display device using a display element including a light emitting portion and a circuit for driving the light emitting portion.

(23) FIG. 1 is a circuit diagram showing a configuration of the scanning drive circuit 110 of Embodiment 1. FIG. 2 is a conceptual block diagram showing a configuration of the display device 1 of Embodiment 1 including the scanning drive circuit 110 shown in FIG. 1. FIG. 3 is a schematic timing chart explaining an operation of the scanning drive circuit 110 shown in FIG. 1. Also, FIG. 4 is an equivalent circuit diagram of a drive circuit 11 composing a display element 10 belonging to an m-th row (m=1, 2, 3, . . . , M) and an n-th column (n=1, 2, 3, . . . , N) in the display device 1 shown in FIG. 2. Firstly, an outline of the display device 1 will be described.

(24) As shown in FIG. 2, the display device 1 includes:

(25) (1) the display elements 10 two-dimensionally disposed in a matrix;

(26) (2) scanning lines SCL extending in a first direction, initialization control lines AZ through which the display elements 10 are initialized, and display control lines CL through which display states/non-display states of the display elements 10 are controlled;

(27) (3) data lines DTL extending in a second direction different from the first direction; and

(28) (4) the scanning drive circuit 110.

(29) The scanning lines SCL, the initialization control lines AZ, and the display control lines CL are each connected to the scanning drive circuit 110. The data lines DTL are connected to a signal outputting circuit 100. It should be noted that although FIG. 2 shows the (33) display elements 10 with the display element 10 belonging to the m-th row and the n-th column as a center, this configuration is merely illustrated as an example. In addition, illustrations of power supply lines PS.sub.1, PS.sub.2 and PS.sub.3 shown in FIG. 4 are omitted in FIG. 2.

(30) The N display elements are displayed every row in the first direction, and the M display elements are displayed every column in the second direction different from the first direction. Also, the display device 1 includes {(N/3)M} pixels two-dimensionally disposed in a matrix. One pixel includes three sub-pixels, that is, a red light emitting sub-pixel for emitting a red light, a green light emitting sub-pixel for emitting a green light, and a blue light emitting sub-pixel for emitting a blue light. The display elements 10 composing the pixels, respectively, are driven in a line-sequential manner, and a display frame rate is FR (times/second). That is to say, the display elements 10 composing (N/3) pixels (N sub-pixels), respectively, disposed in the m-th row are simultaneously driven. In other words, in the display elements 10 composing one row, a timing of light emission/light non-emission thereof is controlled in units of the row to which these display elements 10 belong.

(31) As shown in FIG. 4, each of the display elements 10 includes a drive circuit 11 including a write transistor TR.sub.W, a drive transistor TR.sub.D, and a capacitor portion C.sub.1, and a light emitting portion ELP through which a current is caused to flow via the drive transistor TR.sub.D. The light emitting portion ELP is configured in the form of an organic EL light emitting portion. The display element 10 has a structure in which the light emitting portion ELP is laminated above the drive circuit 11. Although the drive circuit 11 further includes a first transistor TR.sub.1, a second transistor TR.sub.2, a third transistor TR.sub.3, and a fourth transistor TR.sub.4, the first to fourth transistors TR.sub.1, TR.sub.2, TR.sub.3, and TR.sub.4 will be described later.

(32) In the display element 10 belonging to the m-th row and the n-th column, in the write transistor TR.sub.W, one source/drain region is connected to a data line DTL.sub.n, and a gate electrode is connected to a scanning line SCL.sub.m. In the drive transistor TR.sub.D, one source/drain region is connected to the other source/drain region of the write transistor TR.sub.W, thereby composing a first node ND.sub.1. One terminal of the capacitor portion C.sub.1 is connected to a power supply line PS.sub.1. In the capacitor portion C.sub.1, a predetermined reference voltage (a predetermined drive voltage V.sub.CC which will be described later in Embodiment 1) is applied to the one terminal, and the other terminal, and a gate electrode of the drive transistor TR.sub.D are connected to each other, thereby composing a second node ND.sub.2. The write transistor TR.sub.W is controlled in accordance with a signal supplied from the scanning line SCL.sub.m.

(33) A video signal (a drive signal or a luminance signal) V.sub.sig in accordance with which a luminance in the light emitting portion ELP is controlled is applied from the signal outputting circuit 100 to the data line DTL.sub.n. Details thereof will be described later.

(34) The drive circuit 11 further includes a first switch circuit portion SW.sub.1 connected between the second node ND.sub.2, and the other source/drain region of the drive transistor TR.sub.D. The first switch circuit portion SW.sub.1 includes the first transistor TR.sub.1. In the first transistor TR.sub.1, one source/drain region is connected to the second node ND.sub.2, and the other source/drain region is connected to the other source/drain region of the drive transistor TR.sub.D. A gate electrode of the first transistor TR.sub.1 is connected to the scanning line SCL.sub.m, and thus the first transistor TR.sub.1 is controlled in accordance with a signal supplied from the scanning line SCL.sub.m.

(35) The drive circuit 11 further includes a second switch circuit portion SW.sub.2 connected between the second node ND.sub.2, and a power source supply line PS.sub.3 to which a predetermined initialization voltage V.sub.Ini which will be described later is applied. The second switch circuit portion SW.sub.2 includes the second transistor TR.sub.2. In the second transistor TR.sub.2, one source/drain region is connected to a power supply line PS.sub.3, and the other source/drain region is connected to the second node ND.sub.2. A gate electrode of the second transistor TR.sub.2 is connected to the initialization control line AZ.sub.m. Thus, the second transistor TR.sub.2 is controlled in accordance with a signal supplied from the initialization control line AZ.sub.m.

(36) The drive circuit 11 further includes a third switch circuit portion SW.sub.3 connected between the first node ND.sub.1, and the power supply line PS.sub.1 to which the drive voltage V.sub.CC is applied. The third switch circuit portion SW.sub.3 includes the third transistor TR.sub.3. In the third transistor TR.sub.3, one source/drain region is connected to the power supply line PS.sub.1, and the other source/drain region is connected to the first node ND.sub.1. A gate electrode of the third transistor TR.sub.3 is connected to the display control line CL.sub.m. Thus, the third transistor TR.sub.3 is controlled in accordance with a signal supplied from the display control line CL.sub.m.

(37) The drive circuit 11 further includes a fourth switch circuit portion SW.sub.4 connected between the other source/drain region of the drive transistor TR.sub.D, and the one terminal of the light emitting portion ELP. The fourth switch circuit portion SW.sub.4 includes the fourth transistor TR.sub.4. In the fourth transistor TR.sub.4, one source/drain region is connected to the other source/drain region of the drive transistor TR.sub.D, and the other source/drain region is connected to the one terminal of the light emitting portion ELP. A gate electrode of the fourth transistor TR.sub.4 is connected to the display control line CL.sub.m. Thus, the fourth transistor TR.sub.4 is controlled in accordance with a signal supplied from the display control line CL.sub.m. The other terminal (cathode electrode) of the light emitting portion ELP is connected to the power supply line PS.sub.2, and a voltage V.sub.cat which will be described later is applied to the other terminal of the light emitting portion ELP. In FIG. 4, reference symbol C.sub.EL designates a parasitic capacitance of the light emitting portion ELP.

(38) The drive transistor TR.sub.D is configured in the form of a p-channel TFT, and the write transistor TR.sub.W is also configured in the form of the p-channel TFT. In addition, each of the first transistor TR.sub.1, the second transistor TR.sub.2, the third transistor TR.sub.3, and the fourth transistor TR.sub.4 is also configured in the form of the p-channel TFT. It is noted that each of the write transistor TR.sub.W and the like may be configured in the form of an n-channel TFT. Although a description will be given below on the assumption that each of those transistors TR.sub.1 to TR.sub.4, TR.sub.D and TR.sub.W is of a depletion type, the present invention is by no means limited thereto.

(39) The well known configurations and structures may be adopted as the configurations and structures of the signal outputting circuit 100, the scanning lines SCL, the initialization control lines AZ, the display control lines CL, and the data lines DTL.

(40) The power supply lines PS.sub.1, PS.sub.2 and PS.sub.3 extending in the first direction similarly to the case of the scanning lines SCL are each connected to a power source portion (not shown). The drive voltage V.sub.CC is applied to the power supply line PS.sub.1, the voltage V.sub.cat is applied to the power supply line PS.sub.2, and the initialization voltage V.sub.Ini is applied to the power supply line PS.sub.3. The well known configurations and structures may also be adopted as the configurations and structures of the power supply lines PS.sub.1, PS.sub.2 and PS.sub.3.

(41) FIG. 5 is a schematic cross sectional view showing a structure of a part of the display element 10 composing the display device 1 shown in FIG. 2. Although a detailed description will be given later, each of the transistors TR.sub.1 to TR.sub.4, TR.sub.D and TR.sub.W, and the capacitor portion C.sub.1 composing the drive circuit 11 of the display element 10 is formed on a supporting body 20, and the light emitting portion ELP, for example, is formed above each of the transistors TR.sub.1 to TR.sub.4, TR.sub.D and TR.sub.W, and the capacitor portion C.sub.1 composing the drive circuit 11 through an interlayer insulating layer 40. The light emitting portion ELP has the well known configuration and structure, for example, so as to include an anode electrode, a hole transporting layer, a light emitting layer, an electron transporting layer, a cathode electrode, and the like. It is noted that only the drive transistor TR.sub.D is illustrated in FIG. 5. Other transistors TR.sub.1 to TR.sub.4, and TR.sub.W are blocked from view. In addition, although the other source/drain region of the drive transistor TR.sub.D is connected to the anode electrode of the light emitting portion ELP through the fourth transistor TR.sub.4 (not shown), a connection portion between the fourth transistor TR.sub.4, and the anode electrode of the light emitting portion ELP is also blocked from view.

(42) The drive transistor TR.sub.D includes a gate electrode 31, a gate insulating layer 32, and a semiconductor layer 33. More specifically, the drive transistor TR.sub.D includes one source/drain region 35 and the other source/drain region 36 which are provided in the semiconductor layer 33, and a channel formation region 34 to which a portion of the semiconductor layer 33 between one source/drain region 35 and the other source/drain region 36 corresponds. Each of other transistors TR.sub.1 to TR.sub.4, and TR.sub.W (not shown) has the same structure as that of the drive transistor TR.sub.D.

(43) The capacitor portion C.sub.1 includes an electrode 37, a dielectric layer including an extension portion of the gate insulating layer 32, and an electrode 38. It is noted that a connection portion between the electrode 37, and the gate electrode 31 of the drive transistor TR.sub.D, and a connection portion between the electrode 38 and the power supply line PS.sub.1 are each blocked from view.

(44) The gate electrode 31, a part of the gate insulating layer 32, and the electrode 37 composing the capacitor portion C.sub.1 are all formed on the supporting body 20. The drive transistor TR.sub.D, the capacitor portion C.sub.1, and the like are covered with the interlayer insulating layer 40. Also, the light emitting portion ELP including the anode electrode 51, the hole transporting layer, the light emitting layer, the electron transporting layer, and the cathode electrode 53 is provided on the interlayer insulating layer 40. It should be noted that in FIG. 5, the hole transporting layer, the light emitting layer, and the electron transporting layer are collectively illustrated as one layer 52. A second interlayer insulating layer 54 is provided on a portion, of the interlayer insulating layer 40, having no light emitting portion ELP provided thereon, and a transparent substrate 21 is disposed over the second interlayer insulating layer 54 and the cathode electrode 53. Thus, a light emitted from the light emitting layer of the light emitting portion ELP is transmitted through the transparent substrate 21 to be emitted to the outside. The cathode electrode 53, and a wiring 39 composing the power supply line PS.sub.2 are connected to each other through contact holes 56 and 55 which are provided in the second interlayer insulating layer 54 and the interlayer insulating layer 40, respectively.

(45) A method of manufacturing the display device shown in FIG. 5 will be described hereinafter. Firstly, the various wirings such as the scanning lines, the electrodes composing the capacitor portion C.sub.1, the transistors TR.sub.1 to TR.sub.4, TR.sub.D and TR.sub.W including the semiconductor layers, the interlayer insulating layer 40, the contact holes 55 and 56, and the like are suitably formed by utilizing the well known methods. Next, the film deposition and the patterning are carried out by utilizing the well known methods, thereby forming the light emitting portions ELP disposed in a matrix. Also, the supporting body 20 and the transparent substrate 21 after completion of the processes described above are made to face each other, and a periphery thereof is sealed. Also, the connection to the signal outputting circuit 100 and the scanning drive circuit 110 is carried out, thereby making it possible to complete the display device.

(46) Next, the scanning drive circuit 110 will be described. Note that, for the sake of convenience of the description, the description of the operation of the scanning drive circuit 110 is given on the assumption that the scanning signals which are supplied to the scanning lines SCL.sub.1 to SCL.sub.31, respectively, are successively generated. This also applies to other embodiments.

(47) As shown in FIG. 1, the scanning drive circuit 110 includes:

(48) (A) a shift register portion 111; and

(49) (B) a logical circuit portion 112.

(50) In this case, the shift register portion 111 includes P stages (P is a natural number of 3 or more, and so forth on) of shift registers SR.sub.1 to SR.sub.P. The start pulse STP inputted to the shift register portion 111 is successively shifted, and output signals ST.sub.1 to ST.sub.P are outputted from the P stages of shift registers SR.sub.1 to SR.sub.P, respectively. Also, the logical circuit portion 112 operates based on the output signals ST.sub.1 to ST.sub.P in the shift register portion 111, and enable signals (a first enable signal EN.sub.1, and a second enable signal EN.sub.2 which will be described later in Embodiment 1).

(51) When the output signal supplied from the shift register SR.sub.p in the p-th stage (p=1, 2, 3, . . . , P1, and so forth on) is expressed by ST.sub.p, as shown in FIG. 3, commencement of the start pulse STP in the output signal ST.sub.p+1 supplied from the shift register SR.sub.p+1 in the (p+1)-th stage is located between commencement and termination of the start pulse STP in the output signal ST.sub.p. The shift register portion 111 operates based on the clock signal CK and the start pulse STP so as to fulfill the above condition.

(52) Specifically, the start pulse STP inputted to the shift register SR.sub.1 in the first stage is a pulse which rises between the commencement and the termination of the time period T.sub.1 shown in FIG. 3, and falls between the commencement and the termination of the time period T.sub.29. Each of the time periods, such as the time period T.sub.1, shown in FIG. 3, and other corresponding figures which will be described later corresponds to one horizontal scanning time period (so-called 1H). The clock signal CK is a rectangular wave-like signal a polarity of which is inverted every two horizontal scanning time periods (2H). The start pulse in the output signal ST.sub.1 supplied from the shift register SR.sub.1 in the first stage is a pulse which rises at the commencement of the time period T.sub.3, and falls at the termination of the time period T.sub.30. Also, the start pulses in the output signals ST.sub.2, ST.sub.3, etc. from the shift registers in and after the shift register SR.sub.2 in the second stage are pulses which are obtained by successively shifting the original start pulse STP by the two horizontal scanning time periods.

(53) In addition, one first enable signal to one Q-th enable signal (Q is a natural number of 2 or more, and so forth on) exist individually between the commencement of the start pulse STP in the output signal ST.sub.p, and the commencement of the start pulse STP in the output signal ST.sub.p+1. Since Q=2 in Embodiment 1, one first enable signal EN.sub.1 and one second enable signal EN.sub.2 exist individually between the commencement of the start pulse STP in the output signal ST.sub.p, and the commencement of the start pulse STP in the output signal ST.sub.p+1. In other words, the first enable signal EN.sub.1 and the second enable signal EN.sub.2 are signals which are generated so as to fulfill the above condition, and are also basically rectangular wave-like signals which have the same period, and are different in phase from each other.

(54) Specifically, the first enable signal EN.sub.1 and the second enable signal EN.sub.2 are the rectangular wave-like signals each having two horizontal scanning time periods as one period. In Embodiment 1, the first enable signal EN.sub.1 and the second enable signal EN.sub.2 are inverted in polarities thereof every one horizontal scanning time period, and are 180 out of phase with each other. It should be noted that although each of high levels of the first enable signal EN.sub.1 and the second enable signal EN.sub.2 are expressed so as to continue for one horizontal scanning time period in FIG. 3, the present invention is by no means limited thereto. That is to say, each of the first enable signal EN.sub.1 and the second enable signal EN.sub.2 may also be a rectangular wave-like signal a high level of which continues for a time period shorter than one horizontal scanning time period.

(55) For example, one first enable signal EN.sub.1 in the time period T.sub.3, and one second enable signal EN.sub.2 in the time period T.sub.4 exist individually between the commencement of the start pulse STP in the output signal ST.sub.1 (that is, the commencement of the time period T.sub.3), and the commencement of the start pulse STP in the output signal ST.sub.2 (that is, the commencement of the time period T.sub.5). Similarly, one first enable signal EN.sub.1 and one second enable signal EN.sub.2 exist individually between the commencement of the start pulse STP in the output signal ST.sub.2, and the commencement of the start pulse STP in the output signal ST.sub.3. This also applies to any of the output signals in and after the output signal ST.sub.4.

(56) As shown in FIG. 1, the logical circuit portion 112 includes {(P2)Q} negative AND circuits 113. Specifically, the logical circuit portion 112 includes (1, 1)-th to (P2, 2)-th negative AND circuits 113.

(57) When a q-th enable signal (q is an arbitrary natural number of 1 to Q, and so forth on) is expressed by EN.sub.q, as shown in FIGS. 1 and 3, a (p, q)-th negative AND circuit 113 (p is an arbitrary natural number of 1 to (P2), and so forth on) generates a scanning signal based on an output signal ST.sub.p, a signal obtained by inverting a polarity of an output signal ST.sub.p+1, and the q-th enable signal EN.sub.q. More specifically, the output signal ST.sub.p+1 is inverted in polarity thereof by a negative AND circuit 114 shown in FIG. 1, and the resulting signal is transmitted to an input side of the (p, q)-th negative AND circuit 113. Also, the output signal ST.sub.p and the q-th enable signal EN.sub.q are directly transmitted to an input side of the (p, q)-th negative AND circuit 113.

(58) As shown in FIG. 1, a signal outputted from a (1, 2)-th negative AND circuit 113 is supplied to a scanning line SCL.sub.1 connected to the display element 10 belonging to the first row, and a signal outputted from a (2, 1)-th negative AND circuit 113 is supplied to a scanning line SCL.sub.2 connected to the display element 10 belonging to the second row. This also applies to any of other scanning lines SCL. That is to say, a signal outputted from the (p, q)-th negative AND circuit 113 (the case of p=1 and q=1 is excluded) is supplied to a scanning line SCL.sub.m connected to the display element 10 belonging to the m-th row {m=Q(p1)+(q1)}.

(59) Also, in the display element 10 to which the signal based on the scanning signal from the (p, q)-th negative AND circuit 113 is supplied through the scanning line SCL.sub.m, when q=1, a signal based on a scanning signal outputted from a (p1, q)-th negative AND circuit (q is one natural number of 1 to Q, and so forth on) is supplied from the initialization control line AZ.sub.m connected to the display element 10 concerned. Also, when q>1, a signal based on a scanning signal from a (p, q)-th negative AND circuit 113 (q is one natural number of 1 to (q1), and so forth on) is supplied from the initialization control line AZ.sub.m connected to the display element 10 concerned.

(60) More specifically, in Embodiment 1, in the display element 10 to which the signal based on the scanning signal outputted from the (p, q)-th negative AND circuit 113 is supplied through the scanning line SCL.sub.m, when q=1, the signal based on the scanning signal outputted from a (p1, q)-th negative AND circuit 113 is supplied from the initialization control line AZ.sub.m connected to the display element 10 concerned. Also, when q>1, a signal based on a scanning signal outputted from a (p, q1)-th negative AND circuit 113 is supplied from the initialization control line AZ.sub.m connected to the display element 10 concerned.

(61) In addition, when q=1, a signal based on an output signal ST.sub.p+1 outputted from a (p+1)-th shift register SR.sub.p+1 is supplied to the display control line CL.sub.m connected to the display element 10 concerned. Also, when q>1, a signal based on an output signal ST.sub.p+2 outputted from a (p+2)-th shift register SR.sub.p+2 is supplied to the display control line CL.sub.m connected to the display element 10 concerned. It is noted that since each of the third transistor TR.sub.3 and the fourth transistor TR.sub.4 shown in FIG. 4 is the p-channel TFT, the signal is supplied to the display control line CL.sub.m through the negative logical circuit 115.

(62) A more detailed description will now be given with reference to FIG. 1. For example, here, attention is paid to the display element 10 to which a signal based on a scanning signal outputted from a (5, 1)-th negative AND circuit 113 is supplied through a scanning line SCL.sub.8. In this case, a signal based on a scanning signal outputted from a (4, 2)-th negative AND circuit 113 is supplied to an initialization control line AZ.sub.8 connected to the display element 10 concerned. Also, a signal based on an output signal ST.sub.6 from a sixth shift register SR.sub.6 is supplied to a display control line CL.sub.8 connected to the display element 10 concerned. In addition, here, attention is paid to the display element 10 to which a signal based on a scanning signal outputted from a (5, 2)-th negative AND circuit 113 is supplied through a scanning line SCL.sub.9. In this case, a signal based on a scanning signal outputted from a (5, 1)-th negative AND circuit 113 is supplied to an initialization control line AZ.sub.9 connected to the display element 10 concerned. Also, a signal based on an output signal ST.sub.7 from a seventh shift register SR.sub.7 is supplied to a display control line CL.sub.9 connected to the display element 10 concerned.

(63) Next, an operation of the display device 1 will be described in relation to an operation of the display element 10, belonging to the m-th row and the n-th column, to which the signal outputted from the (p, q)-th negative AND circuit 113 is supplied through the scanning line SCL.sub.m. The display element 10 concerned will be referred below to as the (n, m)-th display element 10 or the (n, m)-th sub-pixel. In addition, the horizontal scanning time period for the display elements 10 disposed in the m-th row (more specifically, the m-th horizontal scanning time period in the current display frame) will be simply referred below to as the m-th horizontal scanning time period. This also applies to Embodiment 2 which will be described later.

(64) FIG. 6 is a schematic timing chart explaining an operation for driving the display element 10 belonging to the m-th row and the n-th column. FIGS. 7A to 7F are respectively equivalent circuit diagrams schematically showing ON/OFF states and the like of the first to fourth transistors TR.sub.1 to TR.sub.4, the drive transistor TR.sub.D, and the write transistor TR.sub.W in the drive circuit 11 composing the display element 10 belonging to the m-th row and the n-th column.

(65) Note that, when the schematic timing chart shown in FIG. 6 is compared with the schematic timing chart shown in FIG. 3, for the sake of convenience of the description, reference is made to the timing chart of the initialization control line AZ.sub.8, the scanning line SCL.sub.8, and the display control line CL.sub.8 shown in FIG. 3 on the assumption that, for example, p=5 and q=1, and m=8.

(66) In the light emission state of the display element 10, the drive transistor TR.sub.D is driven so as to cause the drain current I.sub.ds to flow through the light emitting portion ELP in accordance with Expression (5):
I.sub.ds=k.Math..Math.(V.sub.gsV.sub.th).sup.2(5)

(67) where is an effective mobility, V.sub.gs is a voltage developed across the source region and the gate electrode of the drive transistor TR.sub.D, and k is a constant.

(68) Here, the constant k is given by Expression (6):
k=().Math.(W/L).Math.C.sub.ox(6)

(69) where L is a channel length, W is a channel width, and Cox=(relative permeability of gate insulating layer)(permittivity of vacuum)/(thickness of gate insulating layer).

(70) In the light emission state of the display element 10, one source/drain region of the drive transistor TR.sub.D functions as the source region, and the other source/drain region thereof functions as the drain region. For the sake of convenience of the description, in the following description, one source/drain region of the drive transistor TR.sub.D will be simply referred below to as the source region, and the other source/drain region thereof will be simply referred below to as the drain region in some cases.

(71) Although in the description of Embodiment 1, and Embodiment 2 which will be described later, values of the voltages or potentials are set as follows, these values are merely values for the description, and thus the present invention is by no means limited thereto.

(72) V.sub.sig: the video signal in accordance with which the luminance in the light emitting portion ELP 0 V (maximum luminance) to 8 V (minimum luminance) V.sub.CC: the drive voltage 10 V V.sub.Ini: the initialization voltage in accordance with which the potential at the second node ND.sub.2 is initialized 4 V V.sub.th: the threshold voltage of the drive transistor TR.sub.D 2 V V.sub.cat: the voltage applied to the power supply line PS.sub.2 10 V
[Time Period-TP(1).sub.2] (Refer to FIGS. 6 and 7A)

(73) [Time Period-TP(1).sub.2] is a time period for which the (n, m)-th display element 10 is in the light emission state in response to the video signal V.sub.sig formerly written. For example, when m=8, [Time Period-TP(1).sub.2] corresponds to a time period up to the termination of the time period T.sub.8 shown in FIG. 3. Each of the potentials of the initialization control line AZ.sub.8 and the scanning line SCL.sub.8 is held at the high level, and the potential of the light emission control line CL.sub.8 is held at the low level.

(74) Therefore, each of the write transistor TR.sub.W, the first transistor TR.sub.1, and the second transistor TR.sub.2 is held in the OFF state. Each of the third transistor TR.sub.3 and the fourth transistor TR.sub.4 is held in the ON state. A drain current I.sub.ds based on Expression (5) which will be expressed later is caused to flow through the light emitting portion ELP in the display element 10 composing the (n, m)-th sub-pixel. Also, the luminance of the display element 10 composing the (n, m)-th sub-pixel is a value corresponding to the drain current I.sub.ds concerned. [Time Period-TP(1).sub.1] (refer to FIGS. 6 and 7B)

(75) The display element 10 composing the (n, m)-th sub-pixel is held in the non-light emission state for a time period from [Time Period-TP(1).sub.1] to [Time Period-TP(1).sub.2] which will be described later. The termination of [Time Period-TP(1).sub.1] is termination of an (m2)-th horizontal scanning time period in the current display frame. For example, when m=8, [Time Period-TP(1).sub.1] corresponds to the time period T.sub.9 shown in FIG. 3. Each of the potentials of the initialization control line AZ.sub.8 and the scanning line SCL.sub.8 is held at the high level, and the potential of the light emission control line CL.sub.8 becomes the high level.

(76) Therefore, each of the write transistor TR.sub.W, the first transistor TR.sub.1, and the second transistor TR.sub.2 is held in the OFF state. Each of the third transistor TR.sub.3 and the fourth transistor TR.sub.4 is changed from the ON state to the OFF state. As a result, the first node ND.sub.1 is separated from the power supply line PS.sub.1, and the light emission portion ELP and the drive transistor TR.sub.D are separated from each other. Therefore, no current is caused to flow through the light emitting portion ELP, so that the light emitting portion ELP becomes the non-light emission state.

(77) [Time Period-TP(1).sub.0] (Refer to FIGS. 6 and 7C)

(78) [Time Period-TP(1).sub.0] is the (m1)-th horizontal scanning time period in the current display frame. For example, when m=8, [Time Period-TP(1).sub.0] corresponds to the time period T.sub.10 shown in FIG. 3. Each of the potentials of the scanning line SCL.sub.8 and the light emission control line CL.sub.8 is held at the high level. The potential of the initialization control line AZ.sub.8 becomes the high level at the termination of the time period T.sub.10 after having become the low level.

(79) For [Time Period-TP(1).sub.0], each of the first switch circuit portion SW.sub.1, the third switch circuit portion SW.sub.3, and the fourth switch circuit portion SW.sub.4 is held in the OFF state. After the predetermined initialization voltage V.sub.Ini is applied from the power supply line PS.sub.3 to the second node ND.sub.2 through the second switch circuit portion SW.sub.2 held in the ON state, the second switch circuit portion SW.sub.2 is turned OFF, thereby setting the potential at the second node ND.sub.2 at the predetermined reference potential. In the manner as described above, the initialization processing is executed.

(80) That is to say, each of the write transistor TR.sub.W, the first transistor TR.sub.1, the third transistor TR.sub.3, and the fourth transistor TR.sub.4 is held in the OFF state. The second transistor TR.sub.2 is changed from the OFF state to the ON state, so that the predetermined initialization voltage V.sub.Ini is applied from the power supply line PS.sub.3 to the second node ND.sub.2 through the second transistor TR.sub.2 held in the ON state. Also, the second transistor TR.sub.2 is turned OFF at the termination of [Time Period-TP(1).sub.0]. Since the drive voltage V.sub.CC is applied to one terminal of the capacitor portion C.sub.1, and thus the potential at one terminal of the capacitor portion C.sub.1 is held, the potential at the second node ND.sub.2 is set at the predetermined reference potential (4 V) in accordance with the initialization voltage V.sub.Ini.

(81) [Time Period-TP(1).sub.1] (Refer to FIGS. 6 and 7D)

(82) [Time Period-TP(1).sub.1] is the m-th horizontal scanning time period in the current display frame. For example, when m=8, [Time Period-TP(1).sub.1] corresponds to the time period T.sub.11 shown in FIG. 3. Each of the potentials of the initialization control line AZ.sub.8 and the light emission control line CL.sub.8 is held at the high level, and the potential of the scanning line SCL.sub.8 becomes the low level.

(83) For [Time Period-TP(1).sub.1], each of the second switch circuit SW.sub.2, the third switch circuit portion SW.sub.3, and the fourth switch circuit portion SW.sub.4 is held in the OFF state, and the first switch circuit portion SW.sub.1 is turned ON. In a state in which the second node ND.sub.2, and the other source/drain region of the drive transistor TR.sub.D are electrically connected to each other through the first switch circuit portion SW.sub.1 held in the ON state, the video signal V.sub.sig is applied from the data line DTL.sub.n to the first node ND.sub.1 through the write transistor TR.sub.W held in the ON state in accordance with the signal supplied from the scanning line SCL.sub.m. As a result, the potential at the second node ND.sub.2 is changed toward a potential obtained by subtracting the threshold voltage V.sub.th of the drive transistor TR.sub.D from the potential of the video signal V.sub.sig. In the manner as described above, the writing process is carried out.

(84) That is to say, each of the second transistor TR.sub.2, the third transistor TR.sub.3, and the fourth transistor TR.sub.4 is held in the OFF state. Each of the write transistor TR.sub.W and the first transistor TR.sub.1 is turned ON in accordance with the signal supplied from the scanning line SCL.sub.m. Also, the second node ND.sub.2, and the other source/drain region of the drive transistor TR.sub.D are electrically connected to each other through the first transistor TR.sub.1 held in the ON state. In addition, the video signal V.sub.sig is applied from the data line DTL.sub.n to the first node ND.sub.1 through the write transistor TR.sub.W held in the ON state. As a result, the potential at the second node ND.sub.2 is changed toward a potential obtained by subtracting the threshold voltage V.sub.th of the drive transistor TR.sub.D from the potential of the video signal V.sub.sig.

(85) That is to say, by carrying out the initializing process described above, the potential at the second node ND.sub.2 is initialized so that the drive transistor TR.sub.D is turned ON at the commencement of [Time Period-TP(1).sub.1]. Therefore, the potential at the second node ND.sub.2 changes toward the potential of the video signal V.sub.sig applied to the first node ND.sub.1. However, when a difference in potential between the gate electrode and one source/drain region of the drive transistor TR.sub.D reaches the threshold voltage V.sub.th thereof, the drive transistor TR.sub.D is turned OFF. In this state, the potential at the second node ND.sub.2 is approximately expressed by (V.sub.sigV.sub.th). A potential V.sub.ND2 at the second node ND.sub.2 is expressed by Expression (7):
V.sub.ND2(V.sub.sigV.sub.th)(7)

(86) Each of the write transistor TR.sub.W and the first transistor TR.sub.1 is turned OFF in accordance with the signal supplied from the scanning line SCL.sub.m before the (m+1)-th horizontal scanning time period starts.

(87) [Time Period-TP(1).sub.2] (Refer to FIGS. 6 and 7E)

(88) For [Time Period-TP(1).sub.2] is a time period up to start of the light emission time period after completion of the writing process, and the (n, m)-th display element 10 is in a non-light emission state. For example, when m=8, [Time Period-TP(1).sub.2] corresponds to the time period T.sub.12 shown in FIG. 3. The potential of the scanning line SCL.sub.8 becomes the high level, and each of the potentials of the initialization line AZ.sub.8 and the light emission control line CL.sub.8 is held at the high level.

(89) That is to say, each of the write transistor TR.sub.W and the first transistor TR.sub.1 is turned OFF, and each of the second transistor TR.sub.2, the third transistor TR.sub.3, and the fourth transistor TR.sub.4 is held in the OFF state. The first node ND.sub.1 is kept being separated from the power supply line PS.sub.1, and the light emitting portion ELP and the drive transistor TR.sub.D are kept being separated from each other. Also, the potential V.sub.ND2 at the second node ND.sub.2 is held so as to fulfill Expression (7).

(90) [Time Period-TP(1).sub.3] (Refer to FIGS. 6 and 7F)

(91) For [Time Period-TP(1).sub.3], each of the first switch circuit portion SW.sub.1 and the second switch circuit portion SW.sub.2 is held in the OFF state. The other source/drain region of the drive transistor TR.sub.D, and one terminal of the light emitting portion ELP are electrically connected to each other through the fourth switch circuit portion SW.sub.4 held in the ON state. Also, the predetermined drive voltage V.sub.CC is applied from the power supply line PS.sub.1 to the first node ND.sub.1 through the third switch circuit portion SW.sub.3 held in the ON state. As a result, the drain current I.sub.ds is caused to flow through the light emission portion ELP through the drive transistor TR.sub.D, thereby driving the light emission portion ELP. In the manner as described above, the light emission process is carried out.

(92) For example, when m=8, [Time Period-TP(1).sub.3] corresponds to a time period from the commencement of the time period T.sub.13 shown in FIG. 3 to the termination of the time period T.sub.8 in the next frame. Each of the potentials of the initialization control line AZ.sub.8 and the scanning line SCL.sub.8 is held at the high level, and the potential of the display control line CL.sub.8 becomes the low level.

(93) That is to say, each of the first transistor TR.sub.1 and the second transistor TR.sub.2 is held in the OFF state, and each of the third transistor TR.sub.3 and the fourth transistor TR.sub.4 is changed from the OFF state to the ON state in accordance with a signal supplied from the display control line CL.sub.m. The predetermined drive voltage V.sub.CC is applied to the first node ND.sub.1 through the third transistor TR.sub.3 held in the ON state. In addition, the other source/drain region of the drive transistor TR.sub.D, and one terminal of the light emitting portion ELP are electrically connected to each other through the fourth transistor TR.sub.4 held in the ON state. As a result, the drain current I.sub.ds is caused to flow through the light emitting portion ELP via the drive transistor TR.sub.D, thereby driving the light emitting portion ELP.

(94) Also, Expression (8) is obtained as follows based on Expression (7):
V.sub.gsV.sub.CC(V.sub.sigV.sub.th)(8)

(95) Therefore, Expression (5) can be transformed into Expression (9):

(96) $\begin{array}{cc}\begin{array}{c}{I}_{\mathrm{ds}}=k.Math..Math.{\left(V_{\mathrm{gs}}-V_{\mathrm{th}}\right)}^2\\ =k.Math..Math.{\left(V_{\mathrm{CC}}-V_{\mathrm{sig}}\right)}^2\end{array}& \left(9\right)\end{array}$

(97) Therefore, the drain current I.sub.ds caused to flow through the light emitting portion ELP is proportional to a square of a value of a potential difference between the drive voltage V.sub.CC and the video signal V.sub.sig. In other words, the drain current I.sub.ds caused to flow through the light emitting portion ELP does not depend on the threshold voltage V.sub.th of the drive transistor TR.sub.D. That is to say, an amount of luminescence (luminance) of the light emitting portion ELP is free from an influence of the threshold voltage V.sub.th of the drive transistor TR.sub.D. Also, the luminance of the (n, m)-th display element 10 is a value corresponding to the drive current I.sub.ds.

(98) The light emission state of the light emitting portion ELP continues up to a time period corresponding to the termination of [Time Period-TP(1).sub.2] in the next frame.

(99) The operation for the light emission of the display element 10 composing the (n, m)-th sub-pixel is completed through the processes described above.

(100) The lengths of the non-light emission time periods are identical to one another irrespective of the value of m. However, a rate of occupation of [Time Period-TP(1).sub.1] and [Time Period-TP(1).sub.2] in the non-light emission time period changes depending on the value of m. This also applies to Embodiment 2 which will be described later. For example, [Time Period-TP(1).sub.1] does not exist in the timing chart of the signals on the scanning lines SCL.sub.C and the like shown in FIG. 3. It should be noted that even when there is no [Time Period-TP(1).sub.1], there is no particular obstacle in the operation of the display device 1.

(101) The scanning drive circuit 110 of Embodiment 1 is a circuit, having an integrated configuration, for supplying the signals to the scanning lines SCL, the initialization control lines AZ, and the display control lines CL, respectively. As a result, it is possible to realize the reduction of the layout area occupied by the circuits, and the reduction of the circuit cost.

(102) In the display device 1 including the scanning drive circuit 110 of Embodiment 1, even when the termination of the start pulse STP shown in FIG. 3 is changed, the signals applied to the initialization control lines AZ and the scanning lines SCL, respectively, are free from an influence of the change in termination of the start pulse STP. A description thereof will now be given with reference to FIGS. 3, 8 and 9.

(103) Referring to FIG. 3, the start pulse STP is the pulse which rises between the commencement and the termination of the time period T.sub.1, and falls between the commencement and the termination of the time period T.sub.29. FIG. 8 is a schematic timing chart explaining an operation of the scanning drive circuit 110 when the timing at which the start pulse STP falls is changed. Specifically, that timing, for example, is changed in a way that the start pulse STP falls between the commencement and the termination of the time period T.sub.9.

(104) As described above, in the scanning drive circuit 110, the (p, q)-th negative AND circuit generates the scanning signal based on the output signal ST.sub.p, the signal obtained by inverting the polarity of the output signal ST.sub.p+1, and the q-th enable signal EN.sub.q. Therefore, even when the falling of the start pulse STP is changed, the signals applied to the initialization control lines AZ, and the scanning lines SCL, respectively, are the same as those shown in FIG. 3. As apparent from comparison of the schematic timing chart shown in FIG. 8 with the schematic timing chart shown in FIG. 3, only the waveform of the signals supplied to the display control lines CL, respectively, change in the case of the schematic timing chart shown in FIG. 8.

(105) FIG. 9 corresponds to FIG. 6, and is a schematic timing chart explaining an operation for driving the display element 10 belonging to the m-th row and the n-th column when the start pulse STP falls between the commencement and the termination of the time period T.sub.9. In the display device 1, the time period for which each of the potentials of the display control lines CL is held at the high level is the non-light emission time period shown in FIG. 6 or FIG. 8. For example, in FIG. 6, when m=8, the non-light emission time period ranges from the time period T.sub.9 to the time period T.sub.12. On the other hand, in FIG. 9, the non-light emission time period ranges from the previous time period T.sub.21 to the time period T.sub.12. By adopting the easy method of changing the width of the start pulse STP in the manner as described above, the setting of the widths of the pulses supplied to the display control lines CL, respectively, can be readily changed without exerting an influence on the signals supplied to the scanning lines SCL and the initialization control lines AZ, respectively.

(106) A description will be further given in contrast with Comparative Example. FIG. 10 is a circuit diagram of a scanning drive circuit 120 of Comparative Example. In the scanning drive circuit 120, the configuration of a logical circuit portion 122 is different from that of the logical circuit portion 112 of the scanning drive circuit 110 of Embodiment 1. A configuration of a shift register portion 121 of the scanning drive circuit 120 is the same as that of the shift register 111 of the scanning drive circuit 110.

(107) More specifically, in the scanning drive circuit 120 of Comparative Example, the negative logical circuits 114 and 115 shown in FIG. 1 are both omitted. In addition, when q=1, a signal based on an output signal ST.sub.p outputted from the p-th shift register SR.sub.p is supplied to the display element 10 to which the signal based on the scanning signal outputted from the (p, q)-th negative AND circuit 123 is supplied through the corresponding one, of the display control lines CL, connected to the display element 10. Also, when q>1, a signal based on an output signal ST.sub.p+1 from the (p+1)-th shift register SR.sub.p+1 is supplied to the display element 10 concerned.

(108) In the scanning drive circuit 120 having the configuration described above, a (p, q)-th negative AND circuit 123 generates the scanning signal based on the output signal ST.sub.p the output signal ST.sub.p+1, and the q-th enable signal EN.sub.q. Therefore, when a plurality of q-th enable signals EN.sub.q exist within a time period for which the start pulse of the output signal ST.sub.p, and the start pulse of the output signal ST.sub.p+1 overlap each other, a plurality of scanning signals are generated for the overlapping time period. For this reason, if the start pulse STP rises between the commencement and the termination of the time period T.sub.1, the start pulse STP needs to be set so as to fall between the commencement and the termination of the time period T.sub.5.

(109) FIG. 11 is a schematic timing chart explaining an operation of the scanning drive circuit 120 shown in FIG. 10 when the start pulse STP rises between the commencement and the termination of the time period T.sub.1, and falls between the commencement and the termination of the time period T.sub.5. As apparent from comparison of the schematic timing chart shown in FIG. 11 with the schematic timing chart shown in FIG. 3, although there are phase shifts in the signals, the same signals as those shown in FIG. 3 are supplied to the initialization control lines AZ, the scanning lines SCL, and the display control lines CL, respectively.

(110) Next, FIG. 12 shows a schematic timing chart explaining an operation of the scanning drive circuit 120 when, for example, the start pulse STP falls between the commencement and the termination of the time period T.sub.9. In this case, a plurality of scanning signals are generated for the time period for which the start pulse of the output signal ST.sub.p, and the start pulse of the output signal ST.sub.p+1 overlap each other. As has been described above, in the scanning drive circuit 120 of Comparative Example, the changing of the width of the start pulse STP exerts an influence on the signals supplied to the scanning lines SCL and the initialization control line AZ, respectively, and affects the operation of the display device.

(111) As has been described, in the scanning drive circuit 120 of Comparative Example, the changing of the width of the start pulse STP may make it impossible to change the widths of the pulses supplied to the display control lines CL, respectively. However, there is no such a limit to the scanning drive circuit 110 of Embodiment 1.

Embodiment 2

(112) A scanning drive circuit and a display device including the same according to the present invention will be described in detail hereinafter based on Embodiment 2. As shown in FIG. 2, the display device 2 of Embodiment 2 has the same configuration as that of the display device 1 of Embodiment 1 except that a scanning drive circuit 210 of the display device 2 of Embodiment 2 is different in configuration from the scanning drive circuit 110 of the display device 1 of Embodiment 1. Therefore, a description of the display device 2 is omitted in Embodiment 2 for the sake of simplicity.

(113) FIG. 13 is a circuit diagram showing a configuration of the scanning drive circuit 210 of Embodiment 2. Also, FIG. 14 is a schematic timing chart explaining an operation of the scanning drive circuit 210 of Embodiment 2 shown in FIG. 13.

(114) The scanning drive circuit 110 of Embodiment 1 uses the first enable signal EN.sub.1, and the second enable signal EN.sub.2. On the other hand, the scanning drive circuit 210 of Embodiment 2 uses a third enable signal EN.sub.3 and a fourth enable signal EN.sub.4 in addition to the first enable signal EN.sub.1, and the second enable signal EN.sub.2. As a result, the number of constituent stages in a shift register portion composing the scanning drive circuit 210 can be reduced as compared with the case of the scanning drive circuit 110 of Embodiment 1.

(115) As shown in FIG. 13, the scanning drive circuit 210 also includes:

(116) (A) a shift register portion 211; and

(117) (B) a logical circuit portion 212.

(118) In this case, the shift register portion 211 includes P stages of shift registers SR.sub.1 to SR.sub.p. The start pulse STP inputted to the shift register portion 211 is successively shifted, and output signals ST are outputted from the P stages of shift registers SR.sub.1 to SR.sub.P, respectively. Also, the logical circuit portion 212 operates based on the output signals ST supplied from the P stages of shift registers SR.sub.1 to SR.sub.p, respectively, and the enable signals (the first enable signal EN.sub.1, the second enable signal EN.sub.2, the third enable signal EN.sub.3, and the fourth enable signal EN.sub.4 which will be described later in Embodiment 2).

(119) When the output signal outputted from the shift register SR.sub.p in the p-th stage is expressed by ST.sub.p, as shown in FIG. 14, the commencement of the start pulse STP in the output signal ST.sub.p+1 outputted from the shift register SR.sub.p+1 in the (p+1)-th stage is located between the commencement and the termination of the start pulse STP in the output signal ST.sub.p. The shift register portion 211 operates based on the clock signal CK and the start pulse STP so as to fulfill the above condition.

(120) The start pulse STP is a pulse which rises between the commencement and the termination of the time period T.sub.1 shown in FIG. 14, and, for example, falls between the commencement and the termination of the time period T.sub.24.

(121) In Embodiment 1, the clock signal CK is the rectangular wave-like signal the polarity of which is inverted every two horizontal scanning time periods. On the other hand, in Embodiment 2, the clock signal CK is a rectangular wave-like signal a polarity of which is inverted every four horizontal scanning time periods. The start pulse STP in the output signal ST.sub.1 from the shift register SR.sub.1 is a pulse which rises at the commencement of the time period T.sub.3, and falls at the termination of the time period T.sub.25. Also, the start pulse STP in the output signal ST.sub.2, ST.sub.3, etc. from the shift registers in and after the shift register SR.sub.2 in the second stage are a pulse which is obtained by successively shifting the previous pulse by the four horizontal scanning time periods.

(122) In addition, one first enable signal to one Q-th enable signal exist individually between the commencement of the start pulse STP in the output signal ST.sub.p, and the commencement of the start pulse STP in the output signal ST.sub.p+1. Since Q=4 in Embodiment 2, one first enable signal EN.sub.1, one second enable signal EN.sub.2, one third enable signal EN.sub.3, and one fourth enable signal EN.sub.4 exist individually between the commencement of the start pulse STP in the output signal ST.sub.p, and the commencement of the start pulse STP in the output signal ST.sub.p+1. In other words, the first enable signal EN.sub.1, the second enable signal EN.sub.2, the third enable signal EN.sub.3, and the fourth enable signal EN.sub.4 are signals which are generated so as to fulfill the above condition, and are also basically rectangular wave-like signals which have the same period, and are different in phase from one another.

(123) Specifically, the first enable signal EN.sub.1 is the rectangular wave-like signal having the four horizontal scanning time periods as one period. The second enable signal EN.sub.2 is a signal which lags the first enable signal EN.sub.1 by a phase difference corresponding to one horizontal scanning time period. The third enable signal EN.sub.3 is a signal which lags the first enable signal EN.sub.1 by a phase difference corresponding to two horizontal scanning time periods. The fourth enable signal EN.sub.4 is a signal which lags the first enable signal EN.sub.1 by a phase difference corresponding to three horizontal scanning time periods. It should be noted that although in FIG. 14 as well, each of the first to fourth enable signals EN.sub.1, EN.sub.2, EN.sub.3, and EN.sub.4 is expressed in the form of the rectangular wave-like signal so as to be continuously held at the high level for one horizontal scanning time period, the present invention is by no means limited thereto. That is to say, each of the first to fourth enable signals EN.sub.1, EN.sub.2, EN.sub.3, and EN.sub.4 may be a rectangular wave-like signal so as to be continuously held at the high level for a time period shorter than one horizontal scanning time period.

(124) Also, for example, one first enable signal EN.sub.1 in the time period T.sub.3, one second enable signal EN.sub.2 in the time period T.sub.4, one third enable signal EN.sub.3 in the time period T.sub.5, and one fourth enable signal EN.sub.4 in the time period T.sub.6 exist individually between the commencement of the start pulse STP in the output signal ST.sub.1 (that is, the commencement of the time period T.sub.2), and the commencement of the start pulse in the output signal ST.sub.2 (that is, the commencement of the time period T.sub.7). Similarly, one first enable signal EN.sub.1, one second enable signal EN.sub.2, one third enable signal EN.sub.3, and one fourth enable signal EN.sub.4 exist individually between the commencement of the start pulse in the output signal ST.sub.2, and the commencement of the start pulse STP in the output signal ST.sub.3. This also applies to any of the output signals in and after the output signal ST.sub.4.

(125) As shown in FIG. 13, the logical circuit portion 212 includes {(P2)Q} negative AND circuits 213. Specifically, the logical circuit portion 112 includes (1, 1)-th to (P2, 4)-th negative AND circuits 213.

(126) When a q-th enable signal is expressed by EN.sub.q, as shown in FIGS. 13 and 14, a (p, q)-th negative AND circuit 213 generates a scanning signal based on an output signal ST.sub.p, a signal obtained by inverting a polarity of an output signal ST.sub.p+1, and a q-th enable signal EN.sub.q. More specifically, the output signal ST.sub.p+1 is inverted by a plurality of a negative AND circuit 214 shown in FIG. 13, and the resulting signal is transmitted to an input side of the (p, q)-th negative AND circuit 213. Also, the output signal ST.sub.p and the q-th enable signal EN.sub.q are both directly transmitted to an input side of the (p, q)-th negative AND circuit 213.

(127) As shown in FIG. 13, a signal outputted from a (1, 2)-th negative AND circuit 213 is supplied to a scanning line SCL.sub.1 connected to the display element 10 belonging to the first column, and a signal outputted from a (1, 3)-th negative AND circuit 213 is supplied to a scanning line SCL.sub.2 connected to the display element 10 belonging to the second column. This also applies to any of other scanning lines SCL. That is to say, similarly to the description given with respect to Embodiment 1, a signal supplied from a (p, q)-th negative AND circuit 213 (the case of p=1 and q=1 is excluded) is supplied to a scanning line SCL.sub.m connected to the display element 10 belonging to the m-th row {m=Q(p1)+(q1)}.

(128) Also, in the display element 10 to which the signal based on the scanning signal outputted from the (p, q)-th negative AND circuit 213 is supplied through the scanning line SCL.sub.m, when q=1, a signal based on a scanning signal outputted from a (p1, q)-th negative AND circuit 213 is supplied from the initialization control line AZ.sub.m connected to the display element 10 concerned. Also, when q>1, a signal based on a scanning signal outputted from a (p, q)-th negative AND circuit 213 is supplied from the initialization control line AZ.sub.m connected to the display element 10 concerned.

(129) More specifically, in the display element 10 to which the signal based on the scanning signal outputted from the (p, q)-th negative AND circuit 213 is supplied through the scanning line SCL.sub.m, when q=1, the signal based on the scanning signal outputted from the (p1, q)-th negative AND circuit 213 is supplied from the initialization control line AZ.sub.m connected to the display element 10 concerned. Also, when q>1, the signal based on the scanning signal outputted from the (p, q1)-th negative AND circuit 213 is supplied from the initialization control line AZ.sub.m connected to the display element 10 concerned.

(130) In addition, when q=1, a signal based on an output signal ST.sub.p+1 outputted from a (p+1)-th shift register SR.sub.p+1 is supplied to the display control line CL.sub.m connected to the display element 10 concerned. Also, when q>1, a signal based on an output signal ST.sub.p+2 outputted from a (p+2)-th shift register SR.sub.p+2 is supplied to the display control line CL.sub.m connected to the display element 10 concerned. It should be noted that since each of the third transistor TR.sub.3 and the fourth transistor TR.sub.4 shown in FIG. 4, although being described in Embodiment 1 as well, is the p-channel TFT, the signal is supplied to the display control line CL.sub.m through the negative logical circuit 215.

(131) A more detailed description will now be given with reference to FIG. 13. For example, here, attention is paid to the display element 10 to which a signal based on a scanning signal outputted from a (3, 1)-th negative AND circuit 213 is supplied through a scanning line SCL.sub.8. In this case, a signal based on a scanning signal outputted from a (2, 4)-th negative AND circuit 213 is supplied to an initialization control line AZ.sub.8 connected to the display element 10 concerned. Also, a signal based on an output signal ST.sub.4 outputted from a fourth shift register SR.sub.4 is supplied to a display control line CL.sub.8 connected to the display element 10 concerned. In addition, here, attention is paid to the display element 10 to which a signal based on a scanning signal outputted from a (3, 2)-th negative AND circuit 213 is supplied through a scanning line SCL.sub.9. In this case, a signal based on a scanning signal outputted from a (3, 1)-th negative AND circuit 213 is supplied to an initialization control line AZ.sub.9 connected to the display element 10 concerned. Also, a signal based on an output signal ST.sub.5 outputted from a fifth shift register SR.sub.5 is supplied to a display control line CL.sub.9 connected to the display element 10 concerned.

(132) Similarly to the description given with respect to Embodiment 1, even when the termination of the start pulse STP shown in FIG. 14 is changed in the scanning drive circuit 210 of Embodiment 2, the signals applied to the initialization control lines AZ and the scanning lines SCL, respectively, are free from an influence of the change in start pulse STP shown in FIG. 14. FIG. 15 is a schematic timing chart explaining an operation of the scanning drive circuit 210 when a timing at which the start pulse STP falls is changed. Specifically, for example, the timing at which the start pulse STP falls is changed so that the start pulse STP falls between the commencement and the termination of the time period T.sub.9. As apparent from comparison of the schematic timing chart shown in FIG. 15 with the schematic timing chart shown in FIG. 14, in the case of the schematic timing chart shown in FIG. 15, only the waveforms of the signals supplied to the display control lines CL, respectively, change.

(133) FIG. 16 is a circuit diagram showing a configuration of a scanning drive circuit 220 of Comparative Example. The scanning drive circuit 220 corresponds to the scanning drive circuit 120 of Comparative Example described in contrast with Embodiment 1. In the scanning drive circuit 220, the configuration of a logical circuit portion 222 is different from that of the logical circuit portion 212 of the scanning drive circuit 210 of Embodiment 2. A configuration of a shift register 221 of the scanning drive circuit 220 is the same as that of the shift register 211 of the scanning drive circuit 210.

(134) Similarly to the description given with respect to Embodiment 1, the negative logical circuits 214 and 215 shown in FIG. 13 are both omitted in the scanning circuit 220 of Comparative Example. In addition, when q=1, a signal based on an output signal ST.sub.p outputted from the p-th shift register SR.sub.p is supplied from the corresponding one, of the display control lines, connected to the display element 10 to the display element 10 to which the signal based on the scanning signal outputted from the (p, q)-th negative AND circuit 223 is supplied through the corresponding one of the scanning lines SCL. Also, when q>1, a signal based on an output signal ST.sub.p+1 outputted from the (p+1)-th shift register SR.sub.p+1 is supplied to the display element 10 concerned.

(135) Similarly to the description given with respect to Embodiment 1, in the scanning drive circuit 220 having the configuration described above, a (p, q)-th negative AND circuit 223 generates the scanning signal based on the output signal ST.sub.p, the output signal ST.sub.p+1, and the q-th enable signal EN.sub.q. Therefore, when a plurality of q-th enable signals EN.sub.q exist within a time period for which the start pulse STP of the output signal ST.sub.p, and the start pulse STP of the output signal ST.sub.p+1 overlap each other, a plurality of scanning signals are generated for the overlapping time period. For this reason, if the start pulse STP rises between the commencement and the termination of the time period T.sub.1, the start pulse STP needs to be set so as to fall between the commencement and the termination of the time period T.sub.9.

(136) FIG. 17 is a schematic timing chart explaining an operation of the scanning drive circuit 220 shown in FIG. 16 when the start pulse STP rises between the commencement and the termination of the time period T.sub.1, and falls between the commencement and the termination of the time period T.sub.9. As apparent from comparison of the schematic timing chart shown in FIG. 17 with the schematic timing chart shown in FIG. 14, although there are phase shifts in the signals, signals which are approximately the same as those shown in FIG. 3 are supplied to the initialization control lines AZ, the scanning lines SCL, and the display control lines CL, respectively.

(137) Next, FIG. 18 shows a schematic timing chart explaining an operation of the scanning drive circuit 220 when, for example, the start pulse STP falls between the commencement and the termination of the time period T.sub.17. In this case, a plurality of scanning signals are generated for the time period for which the start pulse STP of the output signal ST.sub.p, and the start pulse STP of the output signal ST.sub.p+1 overlap each other. As has been described above, in the scanning drive circuit 220 of Comparative Example, the changing of the width of the start pulse STP exerts an influence on the signals supplied to the scanning lines SCL and the initialization control line AZ, respectively, and affects the operation of the display device.

(138) It should be noted that although the present invention has been described so far based on the preferred embodiments, the present invention is by no means limited thereto. The scanning drive circuits and the display devices described in Embodiments 1 and 2, the configuration and the structures of the various kinds of constituent elements composing the display element, and the processes in the operations of the display devices are illustrative only, and thus can be suitably changed.

(139) For example, in the drive circuit 11 composing the display element 10 shown in FIG. 4, when each of the third transistor TR.sub.3 and the fourth transistor TR.sub.4 is configured in the form of an n-channel TFT, the negative logical circuit 15 shown in FIG. 1, and the negative logical circuit 215 shown in FIG. 13 are unnecessary. In such a manner, the polarities of the signals outputted from the scanning drive circuit may suitably be set in accordance with the configuration of the display element, and thus the resulting signals may be supplied to the scanning lines, the initialization control lines, and the display control lines, respectively.

(140) The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2008-149171 filed in the Japan Patent Office on Jun. 6, 2008, the entire content of which is hereby incorporated by reference.

(141) It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factor in so far as they are within the scope of the appended claims or the equivalents thereof.