Phase locked loop using direct digital frequency synthesizer

Abstract

The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system. The present invention suggests a new structure based on a hardware description language (HDL), and thus reduces a chip area of a frequency synthesizer while obtaining a wide frequency operation range. Furthermore, since only the HDL is used, the entire frequency synthesizer becomes all-synthesizable, and auto layout (auto P&R) can be achieved through a tool, which makes it possible to reduce a design cost of a designer.

Claims

1. A phase locked loop (PLL) using a phase-locked direct digital synthesizer, comprising: a free-running oscillator configured to generate a free-running oscillation signal; a phase-locked direct digital synthesizer configured to generate an output clock signal and an output phase signal whose phases are locked, using the free-running oscillation signal; and a phase interpolator configured to reduce out-of-band noise by processing the output clock signal, wherein the phase-locked direct digital synthesizer comprises: a sampling D flip-flop configured to sample the output phase signal with a synchronization reference clock signal, and output a phase difference signal corresponding to a phase difference between the output clock signal and the synchronization reference clock signal; a digital loop filter configured to generate a first frequency code for adjusting a frequency of the output clock signal by filtering the phase difference signal; a rotational accumulator configured to accumulate a sum frequency code in each period of the free-running oscillation signal through a modulus method, the sum frequency code corresponding to a sum of the first frequency code and a second frequency code, and output a most significant bit (MSB) of an accumulated output value as the output clock signal; a retimer configured to generate the synchronization reference clock signal synchronized with the free-running oscillation signal by sampling a reference clock signal with the free-running oscillation signal; and a coarse frequency lock configured to generate the second frequency code and output the second frequency code to an input side of the rotational accumulator, in order to prevent harmonic lock which occurs when the output clock signal is sub-sampled, and wherein the coarse frequency lock is configured to generate an offset value of the sum frequency code that decides an initial frequency of the output clock signal before the PLL operates as a fine lock loop.

2. The PLL of claim 1, wherein the digital loop filter is configured to generate the first frequency code by filtering the phase difference signal when the phase difference signal is outputted from the sampling D flip-flop.

3. The PLL of claim 1, wherein the phase-locked direct digital synthesizer comprises a fractional accumulator configured to accumulate a fractional frequency code in each period of the synchronization reference clock signal, and compensate for the phase difference signal with a fractional accumulated value.

4. The PLL of claim 1, wherein the sampling D flip-flop and the rotational accumulator are configured to serve to remove nonlinearity which occurs while digital-analog conversion and analog-digital conversion are performed in the PLL.

5. The PLL of claim 1, wherein the rotational accumulator is configured to continuously accumulate an input value through the modulus method even though the accumulated output value exceeds a preset maximum value.

6. The PLL of claim 1, wherein the retimer is configured to generate the synchronization reference clock signal using a D flip-flop.

7. The PLL of claim 1, wherein the output clock signal outputted from the phase interpolator is expressed as the following equation: $f_{\mathrm{OUT}}=\frac{f_{\mathrm{CODE}}}{2^M}{f}_{\mathrm{OSC}}=\left(N+f\right).Math.f_{\mathrm{REF}}$ where f.sub.CODE represents the sum frequency code, f.sub.OSC represents the free-running oscillation signal, M represents a bit number of the rotational accumulator (RACC), N represents an integer to be divided, f represents a fraction to be divided, and f.sub.REF represents the reference clock signal.

8. The PLL of claim 1, wherein the retimer comprises a D flip-flop configured to generate the synchronization reference clock signal synchronized with the free-running oscillation signal by sampling a reference clock signal with the free-running oscillation signal, in order to synchronize the free-running oscillation signal and the synchronization reference clock signal, which have independent frequencies, as one clock signal.

9. A phase locked loop (PLL) using a phase-locked direct digital synthesizer, comprising: a free-running oscillator configured to generate a free-running oscillation signal; a phase-locked direct digital synthesizer configured to generate an output clock signal and an output phase signal whose phases are locked, using the free-running oscillation signal; and a phase interpolator configured to reduce out-of-band noise by processing the output clock signal, wherein the phase-locked direct digital synthesizer comprises: a sampling D flip-flop configured to sample the output phase signal with a synchronization reference clock signal, and output a phase difference signal corresponding to a phase difference between the output clock signal and the synchronization reference clock signal; a digital loop filter configured to generate a first frequency code for adjusting a frequency of the output clock signal by filtering the phase difference signal; a rotational accumulator configured to accumulate a sum frequency code in each period of the free-running oscillation signal through a modulus method, the sum frequency code corresponding to a sum of the first frequency code and a second frequency code, and output a most significant bit (MSB) of an accumulated output value as the output clock signal; a retimer configured to generate the synchronization reference clock signal synchronized with the free-running oscillation signal by sampling a reference clock signal with the free-running oscillation signal; and a coarse frequency lock configured to generate the second frequency code and output the second frequency code to an input side of the rotational accumulator, in order to prevent harmonic lock which occurs when the output clock signal is sub-sampled, wherein the sampling D flip-flop, the digital loop filter and the rotational accumulator form a fine lock loop, wherein the coarse frequency lock and the rotational accumulator form a coarse lock loop, and wherein the fine lock loop is configured to start an operation after the coarse frequency lock generates an offset value of the sum frequency code.

10. A phase locked loop (PLL) using a phase-locked direct digital synthesizer, comprising: a free-running oscillator configured to generate a free-running oscillation signal; a phase-locked direct digital synthesizer configured to generate an output clock signal and an output phase signal whose phases are locked, using the free-running oscillation signal; and a phase interpolator configured to reduce out-of-band noise by processing the output clock signal, wherein the phase-locked direct digital synthesizer comprises: a sampling D flip-flop configured to sample the output phase signal with a synchronization reference clock signal, and output a phase difference signal corresponding to a phase difference between the output clock signal and the synchronization reference clock signal; a digital loop filter configured to generate a first frequency code for adjusting a frequency of the output clock signal by filtering the phase difference signal; a rotational accumulator configured to accumulate a sum frequency code in each period of the free-running oscillation signal through a modulus method, the sum frequency code corresponding to a sum of the first frequency code and a second frequency code, and output a most significant bit (MSB) of an accumulated output value as the output clock signal; a retimer configured to generate the synchronization reference clock signal synchronized with the free-running oscillation signal by sampling a reference clock signal with the free-running oscillation signal; and a coarse frequency lock configured to generate the second frequency code and output the second frequency code to an input side of the rotational accumulator, in order to prevent harmonic lock which occurs when the output clock signal is sub-sampled, and wherein the phase interpolator is configured to perform phase interpolation using lower bits of the output phase signal.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1A is a block diagram of an analog phase locked loop (PLL) according to a related art.

(2) FIG. 1B is a waveform diagram of each unit in the PLL of FIG. 1A.

(3) FIG. 2 is a block diagram of a digital PLL according to a related art.

(4) FIG. 3 is a block diagram of a PLL using a phase-locked direct digital synthesizer in accordance with an embodiment of the present invention.

(5) FIG. 4 illustrates the principle that a sampling D flip-flop extracts a phase using phase information of a digital code-based output phase signal.

(6) FIG. 5A is a diagram for describing the operation principle of a rotational accumulator.

(7) FIG. 5B is a table showing an output frequency of the rotational accumulator based on a frequency code.

(8) FIG. 6A is a flowchart illustrating the operation principle of a coarse frequency lock.

(9) FIG. 6B is a graph illustrating the principle that a coarse lock loop is switched to a fine lock mode.

(10) FIG. 7A is a peripheral circuit diagram for describing the operation principle of a fractional accumulator.

(11) FIG. 7B is a waveform diagram illustrating the operation principle of the fractional accumulator.

(12) FIG. 7C is a table showing output examples of fractional values based on fractional frequency codes.

(13) FIG. 8A is a diagram for describing the phase interpolation principle of a phase interpolator.

(14) FIG. 8B is a circuit diagram illustrating an implementation example of the phase interpolator.

(15) FIG. 8C is a diagram illustrating an example in which a phase interpolation unit is implemented as a tri-state buffer.

MODE FOR INVENTION

(16) Hereafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(17) FIG. 3 is a block diagram illustrating a phase locked loop (PLL) using a PLDDS (Phase-Locked Direct Digital Synthesizer) in accordance with an embodiment of the present invention. As illustrated in FIG. 3, the PLL 300 includes a free-running oscillator 310, a PLDDS 320 and a PI (Phase Interpolator) 330.

(18) The free-running oscillator 310 generates an oscillation signal f.sub.OSC at a pre-designed frequency, in order to operate an RACC (Rotational Accumulator) 323.

(19) The PLDDS 320 generates a low-noise digital output phase signal A.sub.OUT whose phase is locked, using the oscillation signal f.sub.OSC supplied from the oscillator 310. Hereafter, the low-noise digital output phase signal A.sub.OUT will be referred to as an output phase signal.

(20) For this operation, the PLDDS 320 includes a sampling D flip-flop 321, a DLF (Digital Loop Filter) 322, the RACC 323, a fractional accumulator 324, a retimer 325 and a CFL (Coarse Frequency Lock) 326.

(21) In the PLDDS 320, the sampling D flip-flop 321, the DLF 322 and the RACC 323 form a fine lock loop, and the CFL 326 and the RACC 323 form a coarse lock loop. FIG. 4 illustrates the principle that the sampling D flip-flop 321 extracts a phase using phase information of a digital code-based output phase signal A.sub.OUT.

(22) Referring to FIG. 4, the sampling D flip-flop 321 extracts a phase difference signal PD.sub.OUT corresponding to a phase error by sampling the phase information of the output phase signal A.sub.OUT with a synchronization reference clock signal f.sub.REF.sup.R, the output phase signal A.sub.OUT being a digital output value outputted from the RACC 323. That is, the sampling D flip-flop 321 outputs the phase difference signal PD.sub.OUT corresponding to a phase difference between the output clock signal A.sub.OUT[MSB] and the synchronization reference clock signal f.sub.REF.sup.R by sampling the output phase signal A.sub.OUT with the synchronization reference clock signal f.sub.REF.sup.R. Therefore, the sampling D flip-flop 321 can perform the function of the TDC (Time to Digital Converter) 210 of FIG. 2.

(23) The DLF 322 generates a first frequency code f.sub.CODE,DLF for adjusting the frequency of the output clock signal A.sub.OUT[MSB] outputted from the RACC 323 by filtering the phase difference signal PD.sub.OUT supplied from the sampling D flip-flop 321.

(24) The RACC 323 receives the oscillation signal f.sub.OSC, and accumulates a sum frequency code f.sub.CODE in each period of the oscillation signal f.sub.OSC, the sum frequency code f.sub.CODE corresponding to the sum of the first frequency code f.sub.CODE,DLF outputted from the DLF 322 and a second frequency code f.sub.CODE,CFL outputted from the CFL 326. When the RACC 323 is configured as an M-bit accumulator, the RACC 323 continuously accumulates digital input values through a modulus method, even though the accumulated value exceeds the maximum value (2.sup.M1). Thus, since the M bits outputted from the RACC 323 have periodicity, the RACC 323 may output the final output waveform of output phase signal A.sub.OUT. The most significant bit (MSB) of the output phase signal A.sub.OUT is selected as the output waveform, and the output phase signal A.sub.OUT averagely has a frequency of f.sub.CODE/2.sup.M.Math.f.sub.OSC. The other lower bits of the output phase signal A.sub.OUT represent digital phase information of the MSB waveform.

(25) Referring to FIGS. 5A and 5B, the operation of the RACC 323 that performs the function of the DCO (Digitally Controlled Oscillator) 230 of FIG. 2 will be described as follows. FIG. 5A is based on the supposition that the RACC 323 is configured as a three-bit accumulator and the value of the input sum frequency code f.sub.CODE is 3.

(26) Referring to FIG. 5A, the RACC 323 accumulates the sum frequency code f.sub.CODE of 3 at each clock of the sum frequency code f.sub.CODE, and outputs the output phase signal A.sub.OUT as a digital code of 0 (=3b000), 3 (=3b011) or 6 (=3b110). The next digital code in the RACC 323 becomes 9, but becomes 1 (=3b001) through a modulus operation. According to such a principle, digital codes are formed as a repeating pattern of 0, 3, 6, 1, 4, 7, 2, 5, 0, . . . in the RACC 323. The RACC 323 outputs the MSBs of the 3-bit digital codes having the above-described repeating pattern as the output clock signal A.sub.OUT[MSB]. As a result, the RACC 323 generates three pulses for a time of 8T.sub.OSC. This indicates that the RACC 323 generates the output clock signal A.sub.OUT[MSB] having an average frequency of 3/(8T.sub.OSC). Therefore, the RACC 323 outputs the output clock signal A.sub.OUT[MSB] following an equation of f.sub.CODE/2.sup.M.Math.f.sub.OSC according to a digital control value referred to as the sum frequency code f.sub.CODE.

(27) FIG. 5B is a table showing the frequency of the output clock signal A.sub.OUT[MSB] based on the sum frequency code f.sub.CODE, when the frequency of the oscillation signal f.sub.OSC inputted to the RACC 323 is 1 GHz. When the output clock signal A.sub.OUT[MSB] is generated as illustrated in FIG. 5A, the frequency of the output clock signal A.sub.OUT[MSB] becomes 375 MHz.

(28) As publicly known, phase information is obtained by integrating a frequency component. Therefore, since the RACC 323 integrates the sum frequency code f.sub.CODE indicating a frequency component and outputs the output clock signal A.sub.OUT[MSB] according to the integration result, the output phase signal A.sub.OUT of the RACC 323 indicates phase information.

(29) In the PLDDS 320, the RACC 323 directly receives the oscillation signal f.sub.OSC from the oscillator 310, and the sampling D flip-flop 321 receives the synchronization reference clock signal f.sub.REF.sup.R from the retimer 325. However, since the two clock signals f.sub.REF.sup.R and f.sub.OSC have completely independent frequencies, the PLDDS 320 requires a process of synchronizing the two clock signals as one clock signal in order to synthesize the two clock signals. For this operation, a D flip-flop DFF1 of the retimer 325 generates the synchronization reference clock signal f.sub.REF.sup.R synchronized with the oscillation signal f.sub.OSC by sampling a reference clock signal f.sub.REF based on the oscillation signal f.sub.OSC.

(30) The PLDDS 320 requires two loops for locking the phase of the output clock signal A.sub.OUT[MSB]. One of the two loops is the coarse lock loop, and the other is the fine lock loop. The PLL 300 detects a phase by directly sampling the output phase signal A.sub.OUT which does not pass through the divider. In this case, the PLDDS 320 requires the CFL 326 to prevent harmonic lock which occurs when the output phase signal A.sub.OUT is sub-sampled.

(31) The CFL 326 includes a counter and a logic circuit, and outputs the second frequency code f.sub.CODE,CFL to an input side of the RACC 323 in order to prevent harmonic lock which occurs when the output clock signal A.sub.OUT[MSB] is sub-sampled.

(32) FIG. 6A is a flowchart illustrating the operation principle that the CFL 326 outputs the second frequency code f.sub.CODE,CFL, and FIG. 6B is a graph illustrating the principle that the coarse lock mode is switched to the fine lock mode. Referring to FIGS. 6A and 6B, the operation of the coarse lock loop will be described as follows.

(33) The logic circuit enables the counter at each predefined time, i.e. in each high period of a synchronization divided reference clock signal f.sub.REF_DIV.sup.R, such that the counter performs a count operation on an edge of the output clock signal A.sub.OUT[MSB]. Then, the logic circuit compares an output value of the counter to a limit value proportional to N which is a preset integer division value. At this time, when it is determined that the count value is lower than the limit value, the logic circuit increases the second frequency code f.sub.CODE,CFL to raise the frequency of the output clock signal A.sub.OUT[MSB]. However, when it is determined that the count value exceeds the limit value, the logic circuit stops the update operation of the second frequency code f.sub.CODE,CFL by stopping the count operation of the counter. Thus, the operation loop is switched from the coarse lock loop to the fine lock loop. Finally, when the coarse lock loop is ended, the CFL 326 retains the offset value referred to as the second frequency code f.sub.CODE,CFL, and outputs the offset value to the RACC 323.

(34) Through such a process, the CFL 326 generates the second frequency code f.sub.CODE,CFL in the coarse lock loop, the second frequency code f.sub.CODE,CFL indicating the offset value of the sum frequency code fCODE that decides the initial oscillation frequency of the output clock signal A.sub.OUT[MSB] before the PLL 300 operates as the fine lock loop.

(35) After the CFL 326 generates the second frequency code f.sub.CODE,CFL for preventing harmonic lock, the fine lock loop constituted by the sampling D flip-flop 321, the DLF 322 and the RACC 323 starts to operate. Then, when the sampling D flip-flop 321 detects a phase error and outputs a phase difference signal PD.sub.OUT based on the detected phase error, the DLF 322 generates the remaining value f.sub.CODE,DLF except the offset value of the sum frequency code f.sub.CODE by filtering the phase difference signal PD.sub.OUT.

(36) The fractional accumulator 324 added to the fine lock loop serves to synthesize a fractional frequency. Referring to FIGS. 7A to 7C, the operation of the fractional accumulator 324 will be described as follows.

(37) When the fractional accumulator 324 operates as an integer-N accumulator, a fractional frequency code f.sub.CODE,FRAC f inputted to the fractional accumulator 324 is set to 0. When the fractional frequency code f.sub.CODE,FRAC is not 0, the fractional accumulator 324 operates as a fractional-N accumulator. The fractional accumulator 324 accumulates the fractional frequency code f.sub.CODE,FRAC in each period of the synchronization reference clock signal f.sub.REF.sup.R. The fractional accumulated value outputted from the accumulator 324 is added to the phase difference signal PD.sub.OUT, and the resultant signal is supplied as an input value of the DLF 322 and thus compensates for a fractional phase.

(38) For example, when an M-bit fractional frequency code f.sub.CODE,FRAC is 0100 . . . 0000 (f=), the fractional accumulated value of the fractional accumulator 324 becomes 00 . . . 0, 01 . . . 0, 10 . . . 0 and 11 . . . 0. Such a digital code corresponds to phase information of 0, /2, and 3/2. At this time, the fine lock loop adjusts the sum frequency code f.sub.CODE such that an input of the DLF 322 becomes 0. Then, the phase difference signal PD.sub.OUT is outputted as 0, /2, and 3/2 corresponding to the opposite phase of the above-described digital code.

(39) The fractional accumulator 324 may be used to generate a fractional frequency as described above. FIG. 7C illustrates an output example of a fractional value based on the fractional frequency code f.sub.CODE,FRAC.

(40) The RACC 323 of the PLDDS 320 is an NCO (Numerical Controlled Oscillator) that generates the output phase signal A.sub.OUT as a whole digital signal. The RACC 323 serves to remove nonlinearity which occurs while digital-analog conversion and analog-digital conversion are performed in the PLL 300. The RACC 323 is a direct digital synthesizer that serves to exhibit ideal linearity and reduce in-band fractional spur.

(41) However, when the RACC 323 outputs only the MSB as the output clock signal A.sub.OUT[MSB], quantization noise has an influence on out-of-band noise. In order to compensate for such noise, the PI 330 is installed at an output terminal of the PLDDS 320.

(42) The PI 330 serves to reduce out-of-band noise by processing the output clock signal A.sub.OUT[MSB] outputted from the PLDDS 320. FIG. 8A illustrates the principle that the PI 330 performs phase interpolation using the other lower bits LSBs of the output phase signal A.sub.OUT, and FIG. 8B is a circuit diagram illustrating an implementation example of the PI 330.

(43) The lower bits of the output phase signal A.sub.OUT contain fractional phase information of the MSB. The PI 330 uses the MSB output A.sub.OUT[MSB] of the output phase signal A.sub.OUT and a signal A.sub.OUT[MSB].sub.D obtained by delaying the MSB output A.sub.OUT[MSB] by T.sub.OSC. The interpolation ratio of the two signals (a and b) may be obtained when the output of the MSB transitions from 0 to 1.

(44) FIG. 8C illustrates an example in which a phase interpolation unit 331 is implemented with a tri-state buffer.

(45) The output clock signal f.sub.OUT outputted from the PI 330 is expressed as [Equation 1] below.

(46) $\begin{array}{cc}{f}_{\mathrm{OUT}}=\frac{f_{\mathrm{CODE}}}{2^M}{f}_{\mathrm{OSC}}=\left(N+f\right).Math.f_{\mathrm{REF}}& \left[\mathrm{Equation}1\right]\end{array}$

(47) In Equation 1, f.sub.CODE represents the sum frequency code, f.sub.OSC represents the oscillation signal, M represents the bit number of the RACC, N represents an integer to be divided, f represents a fraction to be divided, and f.sub.REF represents the reference clock signal.

(48) While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the disclosure described herein should not be limited based on the described embodiments.