Integrated electronic device comprising a temperature sensor and sensing method

Abstract

A method of sensing a temperature includes providing a voltage to reverse bias a PN junction of a junction diode. The PN junction has a junction capacitance. The method includes providing a reverse bias voltage change across the PN junction and detecting a value of the junction capacitance in response to the reverse bias voltage change. The value of the junction capacitance is a function of a temperature of the PN junction. An output signal is generated based on the detected junction capacitance, where the output signal indicates a temperature of an environment containing the junction diode.

Claims

1. A sensing method, comprising: applying a reverse biasing voltage across a junction diode, the junction diode having an anode and a cathode, and the junction diode having a junction capacitance that varies as a function of temperature; applying a voltage to the cathode that is positive with respect to a voltage on the anode; switching the voltage applied to the cathode between a low value and a high value to apply a reverse voltage step across the anode and cathode of the junction diode; detecting a change in the junction capacitance of the junction diode as a function of temperature in response to the reverse voltage step; and generating an output signal having a value based on the detected change in junction capacitance, the output signal indicating a temperature of the junction diode.

2. The method of claim 1, wherein detecting a change in the junction capacitance of the junction diode comprises detecting a charge flowing through the junction diode responsive to a change in the reverse biasing voltage.

3. The method of claim 2, wherein detecting a change in the junction capacitance of the junction diode further comprises detecting a charge flowing through a reference capacitor responsive to the change in the reverse biasing voltage, the reference capacitor having a value that is approximately equal to the value of the junction capacitance of the junction diode at room temperature.

4. The method of claim 3, wherein detecting the charge flowing through the junction diode and the reference capacitor comprises: applying a first reverse bias voltage across the junction diode and the reference capacitor; generating a first value of the output signal responsive to applying the first reverse bias voltage across the junction diode and reference capacitor; applying a second reverse bias voltage across the junction diode and the reference capacitor, the second reverse bias voltage being different than the first reverse bias voltage; generating a second value of the output signal responsive to applying the second reverse bias voltage across the junction diode and reference capacitor; and detecting the temperature of the junction diode based on the first and second values of the output signal.

5. The method of claim 4, further comprising compensating for a leakage current through the junction diode.

6. The method of claim 5, wherein the anode of the junction diode is coupled to a first node, and wherein compensating for the leakage current through the junction diode further comprises providing a symmetry capacitance on the first node.

7. The method of claim 6, wherein the reference capacitor is coupled to a second node, and wherein compensating for the leakage current through the junction diode further comprises coupling an anode of a compensation diode to the second node.

8. A method, comprising: providing a voltage to reverse bias a PN junction of a junction diode, the PN junction having a junction capacitance; providing a reverse bias voltage change across the PN junction; detecting a value of the junction capacitance in response to the reverse bias voltage change, the value of the junction capacitance being a function of a temperature of the PN junction; and generating an output signal based on the detected junction capacitance, the output signal indicating a temperature of an environment containing the junction diode.

9. The method of claim 8, wherein detecting a value of the junction capacitance of the PN junction comprises detecting a charge flowing through the PN junction responsive to a change in the voltage provided to reverse bias the PN junction.

10. The method of claim 8, further comprising compensating for a leakage current through the PN junction.

11. The method of claim 10, wherein the leakage current through the PN junction is compensated with a compensation current corresponding to a leakage current of a compensation diode, the compensation current being approximately equal to the leakage current through the PN junction.

12. The method of claim 8, further comprising charging first and second nodes to a first reference voltage, the first node being coupled to the junction diode, the second node being coupled to a reference capacitor.

13. The method of claim 12, further comprising, after charging the first node to the first reference voltage, providing a charge flowing through the PN junction to the first node responsive to a change in the voltage provided to reverse bias the PN junction.

14. The method of claim 13, further comprising, after charging the second node to the first reference voltage, providing a charge flowing through the reference capacitor to the second node.

15. The method of claim 14, further comprising providing a compensation current to the second node to compensate for a leakage current through the PN junction.

16. The method of claim 15 further comprising providing an additional capacitance on the first node having value that is approximately equal to a capacitance of the reference capacitor.

17. A sensing method, comprising: applying a reverse biasing voltage across a junction diode, the junction diode having an anode coupled to a first node and having a cathode coupled to a second node, and the junction diode having a junction capacitance that varies as a function of temperature; charging the first node to a first reference voltage; applying a biasing voltage to the second node that is positive with respect to the first biasing voltage on the first node; switching the biasing voltage between a low value and a high value to apply a reverse voltage step across the anode and cathode of the junction diode; providing a charge from the second node through the junction diode to charge the first node in response to the biasing voltage switching between the low and high values; charging a third node to the first reference voltage; providing a charge from the second node through a reference capacitance to the third node in response to the biasing voltage switching between the low and high values; and generating an output signal indicating temperature of the junction diode based on voltages on the first and second nodes.

18. The method of claim 17, wherein generating the output signal comprises taking a difference between a voltage on the first node and a voltage on the third node.

19. The method of claim 17, wherein the charging of the first and third nodes occurs during a reset phase of operation, and the providing of the charge from the second node through the junction diode to charge the first node and the providing of the charge from the second node through the reference capacitance to the third node, and the generating of the output signal, occur during a sensing phase of operation.

20. The method of claim 17, further comprising providing a compensating capacitance on the first node, the compensating capacitance having a value that is approximately equal to a value of the reference capacitance.

21. The method of claim 20, further comprising providing a leakage current to the third node, the leakage current being approximately equal to a leakage current through the junction diode.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) For a better understanding of the present disclosure preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:

(2) FIG. 1 shows the plot of the junction capacitance C.sub.j of a junction diode as a function of the voltage applied V.sub.d;

(3) FIG. 2 shows the variation of junction capacitance C.sub.j of a junction diode as a function of temperature;

(4) FIG. 3 shows a simplified circuit diagram of a present device according to a first embodiment of the present disclosure;

(5) FIG. 4 shows the plot of electrical signals in the circuit of FIG. 3;

(6) FIG. 5 shows a simplified circuit diagram of a present device according to a second embodiment of the present disclosure;

(7) FIG. 6 shows the plot of electrical signals in the circuit of FIG. 5;

(8) FIG. 7 shows the plot of the output voltage V.sub.o of the circuit of FIG. 5; and

(9) FIG. 8 shows a possible implementation of a temperature sensor according to the embodiments of FIGS. 3 and 5.

DETAILED DESCRIPTION

(10) Present sensors according to embodiments of the present disclosure exploit the dependence upon temperature of the capacitance of a reverse biased PN-junction diode.

(11) In fact, as is known, the contact potential (or built-in voltage) V.sub.bi of a reverse biased PN diode is given by:

(12) $\begin{matrix} V_{bi} (T) = \frac{k .Math. T}{q} .Math. \ln (\frac{N_{A} .Math. N_{D}}{n_{i} (T)}) & (1) \end{matrix}$
where K is Boltzmann's constant, T is the temperature in degrees Kelvin, q is the charge of the electron, N.sub.A is the concentration of acceptor atoms, N.sub.D is the concentration of donor atoms, and n.sub.i(t) is the concentration of the intrinsic carriers in the PN diode. In particular, the concentration n.sub.i of the intrinsic carriers depends upon the temperature T on the basis of Eq. (2):

(13) $\begin{matrix} n_{i}^{2} = 0.961 .Math. 10^{33} .Math. T^{3} .Math. e^{\frac{- E_{Geff} (T)}{k .Math. T}} & (2) \end{matrix}$
where E.sub.Geff is the energy gap of the material used for integration of the diode. In a PN diode, by applying a reverse voltage V.sub.d thereto, a charge Q.sub.j is stored on the junction:

(14) $\begin{matrix} Q_{j} (T) = \sqrt{2 .Math. q .Math. {.Math.}_{S} .Math. \frac{N_{D} .Math. N_{A}}{N_{D} + N_{A}} .Math. [V_{bi} (T) - V_{d}]} & (3) \end{matrix}$
where .sub.s is the dielectric constant of the semiconductor. As may be noted, the accumulated charge depends upon the temperature through the contact potential V.sub.bi, as well as upon the reverse voltage V.sub.d.

(15) The junction capacitance C.sub.j of the diode is thus:

(16) $\begin{matrix} C_{j} (T, Vd) = A_{D} .Math. \frac{{dQ}_{j} (T, V)}{dV} = A_{D} .Math. \frac{Q_{j} (T, Vd) - Q_{j} (T, Vd - dV)}{dV} & (4) \end{matrix}$
where A is the area of the PN junction.

(17) In practice, a PN diode formed in a silicon substrate has a junction capacitance depending both upon the biasing voltage and the temperature, as illustrated respectively in FIG. 1 (with a solid line) and in FIG. 2, calculated respectively at constant temperature (T=25 C.) and at constant reverse biasing voltage (V.sub.r=0.625V). FIG. 1 also shows with a dashed line the plot of the junction capacitance determined using more accurate calculations.

(18) In particular, as may be noted from FIG. 2, in temperature ranges wherein integrated circuits normally operate, the junction capacitance C.sub.j has an approximately linear plot as a function of temperature. Consequently, to a first approximation, the reading of the junction capacitance C.sub.j of a reverse biased PN diode has a relation of direct proportionality with the local temperature, and reading of the junction capacitance and/or of its variation supplies direct information on the temperature or on the temperature variation.

(19) FIG. 3 shows a temperature sensor 1 that exploits the principle explained above.

(20) In detail, the temperature sensor 1 comprises a sensor input 2 supplied with a sensor excitation signal, i.e., the timed biasing voltage DRH. A sensing diode 3, of a PN-junction type, has its cathode coupled to the sensor input 2 and its anode coupled to an inverting input 7 of an operational amplifier 4. A reference capacitor 5, having a reference capacitance C.sub.R, is coupled between the sensor input 2 and a non-inverting input 8 of the operational amplifier 4. The reference capacitance C.sub.R is chosen so as to have the same value as the junction capacitance C.sub.j at room temperature.

(21) The inputs 7, 8 of the operational amplifier 4 are both coupled to a first reference potential line 10, set at a first common mode potential V.sub.CMin, through a respective input switch 11. The input switches 11 are controlled by a same reset signal R.

(22) The operational amplifier 4 is of a fully differential type, has a pair of outputs 15, 16 and has a capacitive feedback formed by a first and a second feedback capacitors 17, 18, which have the same feedback capacitance C.sub.i. In detail, the first feedback capacitor 17 is coupled between the first output 15 and the inverting input 7, and the second feedback capacitor 18 is coupled between the second output 16 and the non-inverting input 8 of the operational amplifier 4. The outputs 15, 16 of the operational amplifier 4 are further coupled to a second reference potential line 20, set at a second common mode potential V.sub.CMout, through a respective output switch 21. The output switches 21 are controlled by the reset signal R.

(23) A timed biasing voltage DRH is supplied on the input 2 and switches between a low value (for example, 0.625 V) and a high value V.sub.DRH (for example, 1.25V). In particular, the low value is in any case positive for keeping the sensing diode 3 (which has its anode coupled to the virtual ground on the inverting input 7 of the operational amplifier 4) reverse biased in all the sensing phases, and the high value is chosen for generating a voltage step V of a preset value, as explained in detail hereinafter.

(24) In practice, in the temperature sensor 1 of FIG. 3, the sensing diode 3 and the reference capacitor 5 form a sensing element 25 and the operational amplifier 4, with the capacitive feedback, forms a switched capacitor differential amplifier stage of a known type and widely used, for example, in reading of MEMS structures.

(25) The operational amplifier 4 and the relevant feedback network 17, 18, 11, 21 may be incorporated in an ASIC (Application Specific Integrated Circuit) 28.

(26) The sensing diode 3 and the reference capacitor 5 may be formed in a semiconductor material chip, as described in greater detail with reference to FIG. 8.

(27) The outputs 15 and 16 of the operational amplifier 4 are coupled to a processing stage 30, generally external to the temperature sensor 1 but possibly also integrated in the ASIC. The processing stage 30 may comprise circuits for amplification of the output voltage V.sub.o and for analog-to-digital conversion.

(28) Finally, a timing stage 31 generates biasing/timing signals for the temperature sensor 1 and for the processing stage 30, such as the reset signal R, the timed biasing voltage DRH, and a reading acquisition signal S for the processing stage 30.

(29) Sensing of the output voltage V.sub.o of the operational amplifier 4 is obtained according to the timing, illustrated in FIG. 4, which includes the succession of a reset phase and a sensing phase that follow each other in an acquisition period T.sub.1 equal to one half of a sensing period T.sub.2=2.Math.T.sub.1, as described in detail hereinafter. In particular, the reset signal R and the reading acquisition signal S have the same period, but different duty cycle. For this reason, hereinafter the sensing period T.sub.2 is considered as being divided into two half periods T.sub.11 and T.sub.12, corresponding to two successive periods of the acquisition period T.sub.1.

(30) Reset PhaseFirst Half Period

(31) At instant t.sub.0 the reset signal R switches to the high state, causing the input switches 11 and of the output switches 21 to switch off. Consequently, the inputs 7, 8 of the operational amplifier 4 are coupled to the first common mode potential V.sub.CMin (for example, 0.625 V, i.e., to the low value of the timed biasing voltage DRH), and the outputs 15, 16 of the operational amplifier 4 are coupled to the second common mode potential V.sub.CMout (for example, 1 V), thus resetting the operational amplifier 4.

(32) In this step, the timed biasing voltage DRH (for example, 0.625 V) is low, as likewise is the reading acquisition signal S. The output voltage V.sub.o is thus not acquired by the signal processing stage 30.

(33) Next, at instant t.sub.1, the reset signal R switches to the low state, causing opening of the input and output switches 11, 21 and causing the input nodes 7, 8 and output nodes 15, 16 of the operational amplifier 4 to be independent. The timed biasing voltage DRH is low, as is the reading acquisition signal S.

(34) The step t.sub.1-t.sub.2 may be adopted in case of use of the correlated double sampling (CDS) technique. During this step, in fact, with the technique referred to, offset sampling is carried out, which may then be subtracted during the sensing phase. In this way, it is possible to reduce the offset.

(35) Sensing PhaseFirst Half Period T.sub.11

(36) At the instant t.sub.2, the timed biasing voltage DRH has a rising edge and reaches a value that reverse biases the sensing diode 3, for example, at 1.25 V. In this condition, neglecting possible losses, a reverse current flows in the sensing diode 3. Further, a reference current flows in the reference capacitor 5. There is thus a charge displacement Q.sub.1 (according to the law in Eq. (3), where V.sub.d is here the timed biasing voltage DRH) from the sensing diode 3 to the operational amplifier 4 and a charge displacement Q.sub.2 (according to the law Q=C/V, where V is the step of the timed biasing voltage DRH) from the reference capacitor 5 to the operational amplifier 4. As a result of the half bridge configuration of the sensing element 25 and of the feedback network of the amplifier 26, the latter is traversed by a differential charge Q.sub.2-Q.sub.1 that is a function of the amplitude of the step V of the timed biasing voltage DRH, of the capacitance difference C (difference between the junction capacitance C.sub.j of the sensing diode, and the capacitance C.sub.R of the reference capacitor 5), and of the capacitances C.sub.i of the feedback capacitors 17, 18.

(37) Consequently, between the outputs 15 and 16 of the operational amplifier 4 there is an output voltage V.sub.o

(38) $\begin{matrix} V_{o} (t) \frac{C}{C_{i}} V & (5) \end{matrix}$
which is acquired by the signal processing stage by virtue of the high value of reading acquisition signal S.

(39) In this connection, since the time plot of the output voltage V.sub.o has a transient step, acquisition of the output voltage V.sub.o is made during the subsequent steady state step regime, and the involved time is calculated taking into account the bandwidth of the operational amplifier 4.

(40) This step terminates at instant t.sub.3, where a new period T.sub.1 of the reading acquisition signal S and of the reset signal R and the second half period T.sub.12 of the sensing signal DRH start.

(41) Reset PhaseSecond Half Period T.sub.12

(42) At instant t.sub.3, the reset signal R switches to high, and the reading acquisition signal S switches to low. The operational amplifier 4 is thus reset again, in a way generally similar to what described for the reset phase of the first half period T.sub.11, with the only difference that, now, the timed biasing voltage DRH is high. This value does not, however, affect the reset phase since, as before, the operational amplifier 4 is reset, and the output voltage V.sub.o is not acquired by the signal processing stage 30.

(43) At instant t.sub.4, the reset signal R switches again to low.

(44) Sensing PhaseSecond Half Period T.sub.12

(45) At the instant t.sub.5, the timed biasing voltage DRH has a falling edge, thus causing a charge displacement opposite to that of the sensing phase in the first half period. Consequently, the output voltage V.sub.o has a value

(46) $\begin{matrix} V_{o} (t) \frac{C}{C_{i}} V & (6) \end{matrix}$
with a opposite sign to Eq. (5), since in this half period T.sub.12 the step V of the timed biasing voltage DRH is a down step and is equal to V.sub.DRH.

(47) Also in this step, the value of the output voltage V.sub.o is acquired from the signal processing stage 30 thanks to the high value of the reading acquisition signal S. The signal processing stage 30 thus modifies the sign of the output voltage V.sub.o in one of the two half periods T.sub.11 and T.sub.12, in a way synchronized with the sensing period T.sub.2.

(48) This step terminates at instant t.sub.3, where a new period T.sub.1 of the reading acquisition signal S and of the reset signal R starts, as well as a new period T.sub.2 of the sensing signal DRH.

(49) The solution illustrated in FIG. 3 thus enables detection of the absolute temperature in the area of the sensing diode 3 on the basis of the variation of its reverse junction capacitance, using a simple voltage biased capacitive bridge. This solution presents the advantage of having a zero current consumption and a very simple structure, which does not require use of MEMS capacitive structures.

(50) However, the sensing diode 3 intrinsically presents a current leakage that, in some situations, may reduce reading precision in an undesirable way.

(51) In fact, the aforesaid current leakage of the sensing diode 3 determines a variation of the charge Q.sub.1. In fact, during the sensing phase, the sensing diode 3 undergoes a displacement of charge equal to Q.sub.1Q.sub.L, where Q.sub.L is the charge due to the leakage current. A more precise approximation of the output voltage V.sub.o is thus the following:

(52) $\begin{matrix} V_{o} (t) \frac{C}{C_{i}} V + I_{L} .Math. C_{i} .Math. \frac{T_{1}}{2} & (7) \end{matrix}$
where I.sub.L is the leakage current of the sensing diode 3.

(53) FIG. 5 shows an embodiment wherein the leakage current I.sub.L of the sensing diode 3 is compensated.

(54) In particular, the temperature sensor of FIG. 5 has the same basic structure as the temperature sensor of FIG. 3, where a compensation diode 40 and a symmetry capacitor 41, having a capacitance equal to the capacitance C.sub.R of the reference capacitor 5, have been added. The elements in common with those of FIG. 3 are thus designated by the same reference numbers.

(55) In detail, the compensation diode 40 has its anode coupled to the non-inverting input 8 of the operational amplifier 4 and its cathode coupled to a third reference potential line 43, set at a non-constant biasing potential V.sub.STB, and the symmetry capacitor 41 is coupled between the inverting input 7 of the operational amplifier 4 and the third reference potential line 43.

(56) The biasing potential V.sub.STB switches between two positive values, for example between 0 V and 2.5 V, to be surely higher than the potential on the inputs 7 and 8 of the operational amplifier 4 and keep the compensation diode 40 reverse biased.

(57) Two current generators 45 are also illustrated in FIG. 5 and represent the leakage currents I.sub.L of the sensing diode 3 and of the compensation diode 40. In practice, the sensing diode 3, the reference capacitor 5, the compensation diode 40, and the symmetry capacitor 41 form a capacitive bridge 44.

(58) As illustrated in the timing diagram of FIG. 6, where the signals R, DRH, S have the same meaning as in FIG. 4, and the switching instants t.sub.0-t.sub.5 correspond to the above, the biasing potential V.sub.STB switches at the rising edge of the reset signal R, thus at frequency f.sub.2=1/T.sub.2 equal to one half of the frequency (f.sub.1=1/T.sub.1) of the reset signal R and equal to the frequency of the sensing signal DRH. It follows that the effects of switching of the biasing potential V.sub.STB do not affect the operational amplifier 4 since, during the reset phase, the inputs 7, 8 of the latter are coupled to the first common mode potential V.sub.CMin. Furthermore, the biasing potential V.sub.STB has the same sign as the timed biasing voltage DRH during the sensing phase; namely, it is positive with respect to the virtual ground on the inputs 7 and 8 of the operational amplifier 4 for keeping the compensation diode 40 reverse biased in all the sensing phases and to have a voltage step V equal to the step of the sensing signal DHR in order to keep the compensation diode 40 in the same operating conditions as the sensing diode 3.

(59) In this way, during the sensing phase (both in the first half period T.sub.11 and in the second half period T.sub.12 of the sensing signal DRH), the feedback capacitors 17 and 18 are traversed by the following currents:

(60) a current due to the differential charge generated by the switching edge of the timed biasing voltage DRH and depending on the difference of capacitance in the capacitive bridge 44;

(61) a leakage current I.sub.L1 in the sensing diode 3; and

(62) a leakage current I.sub.L2 in the compensation diode 40.

(63) Consequently, the output voltage V.sub.o of the temperature sensor of FIG. 5 may be expressed as follows:

(64) $\begin{matrix} V_{o} (t) \frac{C}{C_{i}} V + I_{L 1} .Math. C_{i} .Math. \frac{T_{1}}{2} - I_{L 2} .Math. C_{i} .Math. \frac{T_{1}}{2} & (8) \end{matrix}$

(65) By manufacturing the compensation diode 40 in the same way and with the same parameters as the sensing diode 3, due also to the same reverse biasing of the diodes 3 and 40, they generate leakage currents I.sub.L1 and I.sub.L2 that are the same so that in Eq. (8) the two contributions of the leakage currents I.sub.L1 and I.sub.L2 cancel out, and the output voltage V.sub.o may be expressed again by Eq. (6).

(66) The effect of cancelling out of the leakage currents in the sensing diode 3 is visible in the simulation of FIG. 7, which reproduces the voltages on the non-inverting output 15 and on the inverting output 16 of the operational amplifier 4 in case of compensation of the leakage current of the sensing diode 3 (solid lines) and in the case without compensation (dashed lines).

(67) As may be noted, the output voltage V.sub.o of the operational amplifier 4 without compensation has a reading error proportional both to the leakage current and to the integration time. Instead, the output voltage V.sub.o with compensation, after a transient, is insensitive to the above parameters.

(68) FIG. 8 shows a possible implementation of the compensation diode 40 and of the symmetry capacitor 41. In the example illustrated, the temperature sensor 1 is formed in a chip 60 of semiconductor material, such as silicon, having a substrate 50 of a P type, accommodates a well 51 of an N type, which forms the cathode K of the compensation diode 40. The well 51 in turn accommodates a tap 52, of a P type, forming the anode A of the compensation diode 40.

(69) An insulating layer 55 extends over the substrate 50 and accommodates two metal regions 56, 57, arranged on top of each other and formed, for example, in two different metallization levels of the chip 60. The metal regions 56, 57 form, together with the portion of the insulating layer 55 arranged in between, the reference capacitor 5.

(70) The compensation diode 40 and the symmetry capacitor 41 may be formed in a similar way.

(71) The described temperature sensor comprises only a few simple components of a capacitive type (sensing diode 3, reference capacitor 5, possibly a capacitive bridge 44) that may easily be integrated and require only a small area, which cooperate with a sensing network (operational amplifier 4 and corresponding feedback network) that may be manufactured using standard CMOS technology. The sensor has a zero d.c. biasing voltage, and thus a low current consumption.

(72) The temperature sensor 1 may be compensated with respect to the current leakages by a few simple components (compensation diode 40, symmetry capacitor 41), thus supplying a particularly precise output.

(73) Finally, it is clear that modifications and variations may be made to the embodiments of a temperature sensor described and illustrated herein, without thereby departing from the scope of the present disclosure. In particular, the switched capacitor differential amplifier 26 may be replaced by another type of sensing circuit, and/or be formed in a different way from what illustrated, for example be formed as a non-fully differential amplifier.

(74) The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

(75) These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Integrated electronic device comprising a temperature sensor and sensing method

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Abstract

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Description