Method for managing transactions routing between source equipment and target equipment

Abstract

A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.

Claims

1. A system on chip, comprising: an interconnect circuit comprising an input interface and a plurality of output interfaces; a source device coupled to the input interface; a target device comprising a sectorized addressable memory space and a plurality of access ports respectively coupled to the plurality of output interfaces, the source device being configured to deliver a transaction containing an address word to the target device; and a programmable controller coupled to the source device and comprising: a table that is configured to indicate one of the plurality of access ports for each sector of the sectorized addressable memory space once the programmable controller has been programmed; and a control circuit configured to deliver a control word designating a selected access port indicated in the table based on the address word contained in the transaction to the interconnect circuit and in a presence of the transaction originating from the source device, wherein the interconnect circuit is configured to route the transaction from the input interface to a respective output interface that is coupled to the selected access port and to deliver the transaction to the selected access port; and wherein content of the transaction delivered to the selected access port is identical to content of the transaction delivered by the source device regardless of the selected access port designated by the control word.

2. The system on chip according to claim 1, wherein the programmable controller is programmable by the source device.

3. The system on chip according to claim 1, further comprising a plurality of other source devices respectively coupled to a plurality of corresponding other controllers, the interconnect circuit comprising a plurality of other input interfaces respectively coupled to the plurality of other source devices, wherein each of the plurality of corresponding other controllers is programmable by one of the plurality of other source devices.

4. The system on chip according to claim 3, wherein the one of the plurality of other source devices comprises a programmable core or a microprocessor.

5. The system on chip according to claim 3, wherein the one of the plurality of other source devices incorporates a software application containing instructions intended to program each table contained in each of the plurality of corresponding other controllers.

6. The system on chip according to claim 1, wherein the target device comprises a multiport memory.

7. A system on chip, comprising: an interconnect circuit comprising an input interface and a plurality of output interfaces; a source device coupled to the input interface; a target device comprising a sectorized addressable memory space and a plurality of access ports respectively coupled to the plurality of output interfaces, the source device being configured to deliver a transaction containing an address word to the target device; and a programmable controller coupled to the source device and comprising: a table that is configured to indicate one of the plurality of access ports for each sector of the sectorized addressable memory space once the programmable controller has been programmed; and a control circuit configured to deliver a control word designating a selected access port indicated in the table based on the address word contained in the transaction to the interconnect circuit and in a presence of the transaction originating from the source device, wherein the interconnect circuit is configured to route the transaction from the input interface to a respective output interface that is coupled to the selected access port and to deliver the transaction to the selected access port; wherein content of the transaction delivered to the selected access port is identical to content of the transaction delivered by the source device regardless of the selected access port designated by the control word; wherein the transaction is routed conjointly with the control word to the respective output interface; and wherein the respective output interface is configured to not deliver the control word to the selected access port.

8. The system on chip according to claim 7, wherein the transaction is incorporated within a main word of n bits, and wherein the control word comprises m additional bits, a value of m being at least equal to one and depending on a number of the plurality of access ports.

9. The system on chip according to claim 8, wherein the control circuit is configured to adjust a value of the m additional bits so as to designate the selected access port based on the address word contained in the transaction and based on the table, wherein the input interface is configured to receive an overall word of n+m bits including the main word and the control word, wherein the interconnect circuit is configured to route the overall word to the respective output interface, and wherein the respective output interface is configured to not deliver the control word to the selected access port.

10. The system on chip according to claim 9, wherein the input interface is coupled to the source device by an input bus of n tracks and to the programmable controller by a control bus of m tracks, wherein the overall word of n+m bits is to be routed over a network of internal buses of n+m tracks within the interconnect circuit, wherein the respective output interface is configured to receive an internal bus of n+m bits and is coupled to the selected access port by an output bus of n tracks, wherein m tracks of the internal bus of n+m tracks leading to the respective output interface is not connected to the selected access port.

11. A method for managing routing of transactions, the method comprising: having a system on chip comprising a source device and a target device comprising a sectorized addressable memory space and a plurality of access ports, the source device delivering the transactions to the target device, each of the transactions comprising a respective address word, wherein the system on chip is equipped with an interconnect circuit comprising an input interface and a plurality of output interfaces and wherein the input interface is coupled to the source device and the plurality of output interfaces are respectively coupled to the plurality of access ports; receiving, at the input interface, a transaction originating from the source device and a control word of programmable value associated with the transaction; routing the transaction and the control word to a respective output interface of the plurality of output interfaces depending on a value of the control word; delivering the transaction to a selected access port coupled to the respective output interface and so that the control word is not limited to the selected access port; programming, for the source device, a table indicating a respective access port for each sector of the sectorized addressable memory space; and adjusting, for the transaction, the value of the control word depending on the address word contained in the transaction and on content of the table.

12. The method according to claim 11, further comprising loading, into the source device, a software application containing instructions for programming the table, and programming the table by executing the software application.

13. The method according to claim 11, wherein the table is comprised in a programmable controller coupled to the source device and the input interface.

14. The method according to claim 11, further comprising receiving a plurality of other transactions from a plurality of other source devices respectively coupled to a plurality of corresponding other controllers, the interconnect circuit comprising a plurality of other input interfaces respectively coupled to the plurality of other source devices, wherein each of the plurality of corresponding other controllers is programmable by one of the plurality of other source devices.

15. The method according to claim 14, wherein the one of the plurality of other source devices comprises a programmable core or a microprocessor.

16. The method according to claim 14, wherein the target device comprises a multiport memory.

17. The method according to claim 11, further comprising conjointly routing the transaction with the control word to the respective output interface, and wherein the respective output interface is configured to not deliver the control word to the selected access port.

18. The method according to claim 17, wherein the transaction is incorporated within a main word of n bits, and wherein the control word comprises m additional bits, a value of m being at least equal to one and depending on a number of the plurality of access ports.

19. The method according to claim 18, further comprising: adjusting a value of the m additional bits so as to designate the selected access port based on the address word contained in the transaction and based on the table; receiving, at the input interface, an overall word of n+m bits including the main word and the control word; and routing the overall word to the respective output interface without delivering the control word to the selected access port.

20. The method according to claim 19, wherein the input interface is coupled to the source device by an input bus of n tracks and to a programmable controller by a control bus of m tracks, wherein the overall word of n+m bits is to be routed over a network of internal buses of n+m tracks within the interconnect circuit, wherein the respective output interface is configured to receive an internal bus of n+m bits and is coupled to the selected access port by an output bus of n tracks, wherein m tracks of the internal bus of n+m tracks leading to the respective output interface is not connected to the selected access port.

21. The system on chip according to claim 1, wherein the transaction is incorporated within a main word of n bits, and wherein the control word comprises m additional bits, a value of m being at least equal to one and depending on a number of the plurality of access ports.

22. The system on chip according to claim 21, wherein the control circuit is configured to adjust a value of the m additional bits so as to designate the selected access port based on the address word contained in the transaction and based on the table, wherein the input interface is configured to receive an overall word of n+m bits including the main word and the control word, wherein the interconnect circuit is configured to route the overall word to the respective output interface, and wherein the respective output interface is configured to not deliver the control word to the selected access port.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent from the completely non-limiting detailed description of implementations and embodiments, and the appended drawings, in which:

(2) FIGS. 1 to 6 schematically illustrate implementations and embodiments of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(3) Implementations and embodiments of the invention relate to the routing of transactions between at least one source device and at least one target device, for example but non-limitingly a multiport memory, within a system on chip (SoC), and more particularly to the management of the routing of such transactions with the aim of addressing a sectorized memory space of the target device.

(4) In FIG. 1, the reference 1 designates a system on chip including a plurality of source devices ES1-ESp that may be of different types/natures.

(5) Thus, one of the devices, for example the device ES1, may be an LCD screen controller, another device, for example the device ES2, may be a processor for signal processing, another source device may for example be a decoder and another source device, for example the device ESp, may be a microprocessor, for example a microprocessor sold by the company STMicroelectronics under the reference STM32.

(6) The system on chip 1 also includes at least one target device EC, for example a multiport random access memory, here a memory including three access ports PA0, PA1 and PA2.

(7) Of course, a plurality of target devices, of different or identical nature, may be provided on the system on chip 1.

(8) In order to interconnect circuit the source devices ESi with the target device EC, the system on chip 1 also includes an interconnect circuit ICN.

(9) This interconnect circuit ICN includes input interfaces IE1-IEp respectively coupled to the source devices ES1-ESp and output interfaces IS0-IS2 respectively coupled to the access ports PA0-PA2 of the target device EC.

(10) Such an interconnect circuit ICN is capable of routing transactions between the various source devices and the one or more target devices.

(11) Transactions may for example be write transactions or read transactions in the memory EC.

(12) The structure of such an interconnect circuit ICN, which is in general a multilayer interconnect circuit, and the protocol allowing the exchange and routing of transactions in the interior of the interconnect circuit are well known to those skilled in the art.

(13) The latter can, for example, refer to an article by Venkateswara Rao et al. entitled A Frame work on AMBA bus based Communication Architecture to improve the Real Time Computing Performance in MPSoC, International Journal of Computer Applications (0975-8887), Volume 91No. 5, April 2014; or a general presentation of these interconnect circuits given in 2015 by A. Gerstlauer and available at the Internet address http://users.ece.utexas.edu/gerstl/ee382v_f14/lectures/lecture_12.pdf.

(14) Moreover, by way of non-limiting indication, it is for example possible to use the interconnect sold by the company ARM under the reference NIC-400 (version Rop3).

(15) As illustrated in FIG. 1, each input interface IEi of the interconnect circuit ICN is connected to a corresponding/respective source device ESi by an n-bit bus BSi.

(16) In the example described here, the bus is a 32-bit bus.

(17) Each transaction originating from a source device ESi is incorporated into an n-bit word called the main word, which is transmitted over the bus BSi.

(18) As is known in the art, a transaction, for example a write transaction, in particular contains an address field and control bits and a field of data to be written.

(19) For example, the address contained in the transaction may be coded on 16 bits.

(20) The system on chip 1 moreover includes control modules MCMi, more details on the structure and function of which will be given below, that are respectively assigned and coupled to the various source devices ES1-ESp and respectively connected to the corresponding input interfaces IE1-IEp by m-bit control buses BC1-BCp.

(21) Each of the input interfaces IE1-IEp is therefore coupled to an n+m bit bus.

(22) The size of the m of each bus BCi depends on the number of access ports of the one or more target devices EC.

(23) In the present case, since the device EC has three access ports PA0, PA1 and PA2, for the device E, m equals 2.

(24) Each control module therefore delivers 2 bits forming a control word that will be transmitted over the corresponding bus BCi conjointly with the 32-bit main word containing the transaction.

(25) As will be seen in more detail below, the control modules MCMi are programmable.

(26) In the example described here, the control modules are programmed by one of the source devices, in the present case the source device ESp, which here, for example, is an STM 32 microprocessor.

(27) The 32-bit main word and the 2-bit control word form a 34-bit overall word.

(28) Generally, the various 34-bit overall words BSGi are transmitted to the various output interfaces IS0-IS2 by a network of n+m track internal buses.

(29) In the example described here (n=32 and m=2), the various 34-bit overall words BSGi are transmitted to the various output interfaces IS0-IS2 by a network of 34-track internal buses.

(30) Each output interface is therefore configured to receive an n+m bit internal bus (34-bit bus in this example), in the present case internal bus BSGS0 for the interface IS0, internal bus BSGS1 for the interface IS1 and internal bus BSGS2 for the interface IS2.

(31) In contrast, as illustrated in FIG. 1, only the n tracks (n=32 in this example) of the buses BSGS0, BSGS1 and BSGS2 intended to contain the transaction are connected to the access ports PA0, PA1, PA2.

(32) In other words, the m tracks (here the 33rd and 34th tracks) that transmit the m-bit control word (here the 2-bit control word) are not connected to the corresponding access port.

(33) Thus, the transaction delivered to an access port is identical to the transaction originating from a source device, whatever the selected access port.

(34) Depending on the value of the control word delivered by the corresponding control module MCMi, the transaction originating from the corresponding source device will be routed either to the output interface IS0, and therefore to the access port PA0, or to the exit interface IS1 and therefore to the access port PA1, or to the exit interface IS2 and therefore to the access port PA2.

(35) Thus, by way of non-limiting example, in the case where m=2, if the value of the control word is equal to bit sequence 00, the transaction will be routed to the access port PA0, whereas, if the value of the control word is equal to bit sequence 01, the transaction will be routed to the access port PA1, and if the value of the control word is equal to bit sequence 10, the transaction will be routed to the access port PA2.

(36) In fact, in practice, the control bits are for example the two most significant bits of the address word contained in the transaction.

(37) Thus, if the address word contained in the transaction is a 16-bit word, the address word transmitted over the network of internal buses of the interconnect circuit ICN is an 18-bit word. The interconnect circuit ICN therefore interprets the 18-bit word as an 18-bit address. The interconnect circuit ICN is then configured to route this 18-bit word either to the output interface IS0 or to the output interface IS1 or to the output interface IS2 depending on the value of the two most significant bits.

(38) An interconnect circuit ICN is configured in a conventional way, for example in VHDL. Then this VHDL is converted into a hardware circuit including a control circuit, switches and buses and the various paths of which are defined by the configuration of the interconnect circuit ICN.

(39) Reference is now more particularly made to FIGS. 2 to 5 to detail an example of management of the routing of transactions.

(40) The target element EC, in the present case the multiport memory, includes an addressable memory space EMM that is sectorized or partitioned. Thus, in the example illustrated in FIG. 2, the memory space EMM includes sectors SCT0-SCTk. The number of sectors depends on the size of the memory space.

(41) Depending on the envisaged application and/or on the nature of the one or more source elements, one or more sectors may be assigned a high priority with respect to other sectors assigned a low priority. The priority order may for example depend on the content stored in a sector. Thus, if one or more sectors include a program code that must always be accessible by one or more source elements, for example the microprocessor, whatever the density of the traffic in the interior of the interconnect circuit ICN, then the one or more sectors in question of the memory space will be assigned a high priority.

(42) Furthermore, one of the access ports of the target device EC will for example be assigned to these priority sectors whereas the other sectors will be associated with the other access ports.

(43) This correspondence between the sectors and access ports is stored, as illustrated in FIG. 3, in a table (look-up table) TBi. In practice there is one table TBi per source device. The content of the table may differ from one table to the next or be identical between certain at least of the tables.

(44) As illustrated in FIG. 4, the table TBi belongs to the control module MCMi associated with and coupled to the source element ESi.

(45) This table TBi is programmable by one of the source devices, in the present case the source device ESp, which is the programmable core or the microprocessor.

(46) The control module MCMi also includes a control circuit CCMi, produced for example using logic circuits, and configured to communicate with the table TBi and to receive the address word ADRi contained in each transaction Ti originating from the source element ESi.

(47) Furthermore, as illustrated in FIG. 5, from the address word ADRi, the control circuit CCMi determines to which sector of the memory space EMM this address word ADRi corresponds and therefore for which access port the transaction Ti is intended.

(48) Knowing the destination access port, for example the access port PA2, the control circuit CCMi is then configured to generate the value of the control word MCi that will be delivered over the control bus BCi.

(49) In the present case, since the access port PA2 is designated, the value of the control word MCi is equal to bit sequence 10 thereby allowing the interconnect circuit ICn to route the transaction Ti to the output interface IS2 and therefore to the access port PA2.

(50) The programming of the tables TBi by the user, depending on the envisaged application, allows a great flexibility in the use of the system on chip. Thus, not only is it possible to change orders of priority depending on the application but it is also possible for other applications to assign, for one or more source devices for example, a given access port for all the sectors of the memory space EMM of the target device. This then amounts to assigning one access port to one source device and to routing all the transactions originating from this source device to this access port.

(51) It is thus possible, depending on the nature of the source devices, to decide to route all the transactions from a source device to one access port and for example to route all the transactions originating from the other source devices to one or more other access ports.

(52) An example of management of the routing of transactions is illustrated in FIG. 6.

(53) In a first step S20, the interconnect circuit ICN is coupled to the various source devices ESi, to the various access ports PAj, and to the control modules MCMi.

(54) Next, in a step S21, the interconnect circuit ICN is configured so that the routing of a transaction to an access port depends on the logic value of the control word associated with this transaction.

(55) Although in FIG. 6 step S21 is shown after step S20, it would of course be entirely possible to first configure the interconnect circuit ICN so as to produce it in hardware form, then to couple this interconnect circuit ICN with the source devices ESi, the access ports PAj, and the control modules MCMi.

(56) In a step S22, a software application that contains instructions for programming the tables TBi of the control modules MCMi is loaded into the source device ESp, which in the present case is a microprocessor.

(57) Thus, when the software application is executed (step S23), the modules MCMi and more particularly the tables TBi are programmed (step S24).