Output impedance calibration of integrated switched-mode power amplifiers

Abstract

Systems and methods for reducing variability in the output impedance of an integrated switch-mode power amplifier (PA) split the output impedance between passive resistor, which may be on-chip, and a MOSFET switch of the amplifier. The PA may have a single-ended configuration or a differential configuration having two single-ended structures operating with opposite phases. In one implementation, the size of the MOSFET switch is larger than that of the MOSFET switch implemented in a conventional PA, but the size is still acceptable to operate the PA at a desired frequency. In addition, a calibration approach may be utilized to ensure that the MOSFET switch has a controlled and calibrated ON resistance, thereby providing stable output power levels of the PA and ensuring consistency and repeatability in NMR measurements.

Claims

1. Circuitry for reducing variability of an output impedance of an integrated switch-mode power amplifier (PA), the circuitry comprising: a PA driver comprising one or more PMOS components and one or more NMOS components; a pre-driver for facilitating activation and deactivation of the PA driver; a passive resistor coupled to the PA driver so as to split the output impedance between the PA driver and the passive resistor; and a calibration circuit comprising a replica circuit of the PA driver and a load resistor for calibrating an ON resistance of the PA driver so as to provide stable output power levels, the replica circuit comprising one or more PMOS components and one or more NMOS components identical to the components of the PA driver.

2. The circuitry of claim 1, wherein the passive resistor has an impedance that does not depend on temperature or voltage.

3. The circuitry of claim 1, wherein the calibration circuit further comprises an on-chip voltage divider for generating a reference voltage.

4. The circuitry of claim 3, wherein the calibration circuit further comprises a comparator for comparing the reference voltage with an output voltage of the replica circuit and the load resistor.

5. The circuitry of claim 1, wherein the passive resistor is on-chip.

6. The circuitry of claim 1, wherein the passive resistor is off-chip.

7. The circuitry of claim 1, wherein the calibration circuit is configured to adjust the ON resistance of the replica circuit until an output voltage of the replica circuit crosses a threshold voltage corresponding to a target value of the ON resistance of the replica circuit.

8. The circuitry of claim 7, wherein the target value of the ON resistance of the replica circuit satisfies an equation:
R.sub.ON+R.sub.D=R.sub.CAL/2 where R.sub.ON denotes the target value of the ON resistance of the replica circuit, R.sub.D denotes a resistance of the passive resistor, and R.sub.CAL denotes a resistance of the load resistor.

9. An NMR apparatus comprising: an NMR coil configured to enclose a sample; an integrated switch-mode PA coupled to the NMR coil; and circuitry for reducing variability of an output impedance of the PA; wherein the circuitry comprises (i) a PA driver comprising one or more PMOS components and one or more NMOS components, (ii) a pre-driver for facilitating activation and deactivation of the PA driver, (iii) a passive resistor coupled to the PA driver for splitting the output impedance between the PA driver and the passive resistor, and (iv) a calibration circuit comprising a replica circuit of the PA driver and a load resistor for calibrating an ON resistance of the PA driver so as to provide stable output power levels, the replica circuit comprising one or more PMOS components and one or more NMOS components identical to the components of the PA driver.

10. The NMR apparatus of claim 9, wherein the passive resistor has an impedance that does not depend on temperature or voltage.

11. The NMR apparatus of claim 9, wherein the calibration circuit further comprises an on-chip voltage divider for generating a reference voltage.

12. The NMR apparatus of claim 11, wherein the calibration circuit further comprises a comparator for comparing the reference voltage with an output voltage of the replica circuit and the load resistor.

13. The NMR apparatus of claim 9, wherein the calibration circuit is configured to adjust the ON resistance of the replica circuit until an output voltage of the replica circuit crosses a threshold voltage corresponding to a target value of the ON resistance of the replica circuit.

14. The NMR apparatus of claim 13, wherein the target value of the ON resistance of the replica circuit satisfies an equation:
R.sub.ON+R.sub.D=R.sub.CAL/2 where R.sub.ON denotes the target value of the ON resistance of the replica circuit, R.sub.D denotes a resistance of the passive resistor, and R.sub.CAL denotes a resistance of the load resistor.

15. A method of reducing variability of an output impedance of an integrated switch-mode power amplifier (PA), the method comprising: providing a PA driver having one or more PMOS components and one or more NMOS components; providing a pre-driver for facilitating activation and deactivation of the PA driver; providing a calibration circuit comprising a replica circuit of the PA driver and a load resistor for calibrating an ON resistance of the PA driver, the replica circuit comprising one or more PMOS components and one or more NMOS components identical to the components of the PA driver; adjusting a first number of stripes of the replica circuit such that the ON resistance thereof has a desired impedance; and adjusting a second number of stripes of the PA driver based at least in part on the adjusted first number of stripes to provide the desired impedance.

16. The method of claim 15, wherein the first number of stripes of the replica circuit is adjusted until an output voltage of the replica circuit crosses a threshold voltage corresponding to a target value of the ON resistance of the replica circuit.

17. The method of claim 16, wherein the target value of the ON resistance of the replica circuit satisfies an equation:
R.sub.ON+R.sub.D=R.sub.CAL/2 where R.sub.ON denotes the target value of the ON resistance of the replica circuit, R.sub.D denotes a resistance of the passive resistor, and R.sub.CAL denotes a resistance of the load resistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, with an emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which:

(2) FIG. 1 schematically illustrates a conventional NMR device.

(3) FIG. 2 schematically illustrates a conventional class-D power amplifier.

(4) FIG. 3A schematically illustrates a circuit comprising an exemplary class-D PA interface coupled to an NMR probe in accordance with various embodiments of the present invention.

(5) FIG. 3B schematically illustrates an exemplary circuit for adjusting ON resistance.

(6) FIG. 4 schematically illustrates a calibration circuit in accordance with various embodiments of the present invention.

(7) FIG. 5 is a flow chart illustrating a representative approach for calibrating PA output impedance.

DETAILED DESCRIPTION

(8) Refer first to FIG. 3A, which depicts an exemplary differential class-D PA interface 300 coupled to an NMR probe 302 in accordance with various embodiments of the present invention. The PA is implemented as a part of a CMOS (Complementary Metal Oxide Semiconductor) application-specific integrated circuit (ASIC) chip. The NMR probe 302 includes a coil 102 and capacitors CM_P, CM_M, CT. Capacitor CT in combination with inductance of coil 102 creates a parallel resonant circuit 303. Capacitor CM_P and CM_M provide a matching network that transforms the impedance of parallel resonant circuit 303 to the passive differential impedance R.sub.T at the excitation frequency at the output of the PA. The PA 300 is implemented as a discrete chip or a part of a larger application specific integrated circuit (ASIC) including a pair of pre-drivers 304, 306, each coupled to output driver P-type and N-type MOSFET devices 308, 310, which are connected in series with an on-chip resistor 312 having a resistance R.sub.D and function as the PA circuit. The pre-drivers 304, 306 receive, respectively, the pulse sequence, its inverse and the carrier signal, and include logical NAND and NOR gates. In a typical switched-mode power amplifier, the sizes of the PMOS device 308 and NMOS device 310 are chosen to produce a desired PA output power for operation at a target frequency. A fundamental tradeoff exists between the amount of power provided by such PA and its bandwidth due to the parasitic capacitances of devices 308, 310, which reduce the PA bandwidth as their sizes are increased to boost output PA power and vice versa.

(9) In CMOS manufacturing process, ON resistances (R.sub.ON)i.e., the resistance across the drain/source path of the MOSFET with the gate terminal configured to operate the MOSFET in a strong inversion linear regimeis a function of many parameters, such as supply voltage, operating temperature, variations in manufacturing parameters including lithography, chemical etching, and electron mobility (among others). As a result, a switching-mode power amplifier using MOSFET devices 308, 310 as switches in the in configuration shown in FIG. 3A will exhibit a large variation of up to 30% in both output power and bandwidth due to variation in the MOSFET ON resistance from one instance of circuit 300 to another and over the full range of environmental conditions. To minimize this variation a calibration approach, as further described below, is utilized to adjust the ON resistance of the PMOS device 308 and NMOS device 310 and keep it at a constant value suited to the particular application.

(10) Because the devices 308, 310 are each connected in series with the resistor 312, the target ON resistance of devices 308, 310 is R.sub.ON so as to provide a combined differential PA output impedance of R.sub.T=2(R.sub.ON+R.sub.D). In a typical NMR instrument, NMR probe 302 presents a passive 50 load to the PA that is expected to have an output impedance of the same value. This promotes optimal power delivery from the PA to probe 302 and avoids electrical reflections that can damage the PA. Without loss of generality, other interface impedance values can be chosen; for example, smaller interface impedance values will result in larger power delivery by the PA. In this case, the value of resistor 312 is reduced and the values of matching capacitors CM_P, CM_M are adjusted appropriately to satisfy the power-matching condition and the lower interface impedance.

(11) FIG. 3B illustrates a circuit for adjusting the ON resistance by changing the total width of the output MOSFET devices 308, 310 driving the output of the PA. In one embodiment, PA output devices are configured as a parallel connection of plurality of MOSFET devices (stripes) each having a width equal to the total desired width of the MOSFET device divided by the chosen number of parallel devices. Without loss of generality, in the embodiment shown in FIG. 3B, the number of parallel MOSFET devices is indicated as NSTRIPES. In some embodiments, the number of stripes in PMOSFET devices can differ from the number of stripes in NMOSFET devices to accommodate different variabilities of P-type and N-type MOSFETs. Unlike the conventional class-D PA illustrated in FIG. 3A, the gate terminals of the output MOSFETS shown in FIG. 3B can be individually controlled using the illustrated stripe-selection logic circuits 320, 322. In particular, the desired number of stripes is selected by driving HI the appropriate number of bits in the digital control signals SELECT_P_STRIPES and SELECT_N_STRIPES, which are digital signals of width NSTRIPES bits. The value of NSTRIPES is chosen in such that when all stripes of the output MOSFET device are selected, the ON resistance of the MOSFET device is less than the target RON value for the worst-case manufacturing variation, resulting in lowest ON resistance of the typical MOSFET in the chosen manufacturing process, lowest desired operating temperature and highest operating power supply voltage.

(12) The resistance R.sub.D of the on-chip resistors 312 typically does not depend significantly on temperature and voltage, but may vary in a range of 15% as a result of the manufacturing process variations. Thus, total single-ended output impedance of the PA, R.sub.ON+R.sub.D, may vary in the range of 30%; this necessitates a calibration approach to provide stable PA output power levels to ensure consistency and repeatability during NMR measurements.

(13) FIG. 4 illustrates a calibration circuit 400 in accordance with various embodiments of the present invention. The calibration circuit 400 utilizes sensors integrated on the same chip as the PA circuit 300 to accurately measure a DC ON resistance of the switch MOSFET devices of the PA. In various embodiments, the ON resistance is measured using a PA driver replica circuit 402 having PMOSFET and NMOSFET switches 404, 406 with on-chip resistors R.sub.D and loaded with external resistors 408, 410, respectively; each of the resistors 408, 410 has an impedance of R.sub.CAL precisely. Devices 404, 406 have identical total width and length and have the same number of stripes (NSTRIPES) as devices 308, 310 shown in FIG. 3B. In various embodiments, the calibration approach implements an on-chip voltage reference 412 for generating a reference voltage and a comparator 414 for comparing the reference voltage with the output voltage of the sense PMOSFET or NMOSFET 404, 406 generated by a resistive divider from V.sub.DDPA to V.sub.SSPA. The resistive dividers may be formed by the resistors 408, 410, which have a precise impedance of R.sub.CAL, resistors R.sub.D connected in series with the drain terminal of the PMOSFET and NMOSFET sensors of the calibration circuit, and the ON resistance of the MOSFET devices 404, 406.

(14) In various embodiments, a decision value of the comparator 414 is stored in one of a bank of control registers 416, which are accessible to a digital interface 418. (All of these components may reside on the ASIC 300 shown in FIG. 3B.) In addition, a finite state machine may be utilized to adjust the corresponding ON resistance of the replica half driver 402 until the output voltage of the sense PMOSFET or NMOSFET crosses a threshold voltage corresponding to a target value of the ON resistance. For the PMOSFET sensor circuit, the comparator threshold voltage is chosen to be (2/3)V.sub.DDPA where V.sub.DDPA is the PA supply voltage. For the NMOSFET sensor circuit, comparator threshold voltage is chosen to be (1/3)V.sub.DDPA. The finite state machine may be implemented on or outside the chip 300 in hardware and/or software. In some embodiments, the threshold voltages can be generated internally on the chip using the resistive divider string formed by three identical resistors connected in series from V.sub.DDPA to V.sub.SSPA. Given the generated threshold voltages, the comparator output will change when the following condition is met for either one of the MOSFET sensors: R.sub.ON+R.sub.D=(R.sub.CAL/2).

(15) In various embodiments, the PA half-replica impedance sensor 402 is controlled by two control registers (e.g., CENSN and CENSP in a Model WG1000 provided by WaveGuide Corporation). Writing logic 1 to either one of these registers may enable one or both sense devices 404, 406. In addition, two registers (e.g., CDSN and CDSP) may be used to drive the gates of the MOS sensor devices 404, 406 to an appropriate value required for the calibration approach. In some embodiments, a register (e.g., SELCALREF) is used to select which one of the sense PMOSFET and NMOSFET devices and which reference voltages are connected to the inputs of the decision comparator 414. For example, writing logic 0 may select the output from the sense PMOS 404 and (2/3)V.sub.DDPA reference voltage, whereas writing logic 1 may select the output from the sense NMOS 406 and (1/3)V.sub.DDPA reference voltage.

(16) FIG. 5 illustrates a representative flow chart 500 illustrating operation of the calibration circuit 400 for calibrating a PA output impedance. In a preferred embodiment, the output impedance of the PA is calibrated, before each NMR experiment, during the so called recycle delay or after the chip is powered up. While no specific algorithm update rate is specified for the steps of the flow chart 500, it is expected that a minimal progression time interval in the finite state machine is determined based on the settling time constants of capacitors in a low-pass filter that are used to remove high-frequency noise at the inputs of the decision comparator 414 arising during switching between different comparison thresholds.

(17) With reference to FIGS. 3B, 4 and 5, in a first step 502, the circuit 400 is enabled. The NMOSFET leg 406 of the circuit 400 is disabled and the comparator reference 412 is set to (2/3) V.sub.DDPA reference voltage (step 504). At this point, no stripes of the PMOSFET sense circuit 404 are selected (step 506). If the output of the comparator 414 is low, additional stripe is enabled in the PMOSFET sense circuit 404 (step 508). If the output of the comparator 414 is high and the procedure 500 has just been entered, an error condition exists where either target R.sub.ON value of the PMOSFET device is too large and cannot be achieved by selecting even single stripe of the calibration sensor PMOSFET 404 or comparator threshold value was chosen incorrectly for the target R.sub.ON value; otherwise, the current number of stripes is written the register bank 416 (step 510). At this point the PMOSFET leg 404 of the circuit 400 is disabled and the NMOSFET leg 406 is enabled, and the comparator reference 412 is set to (1/3)V.sub.DDPA reference voltage (step 512). All 15 stripes of the NMOS sense circuit are selected (step 514). If the output of the comparator 414 is now low, the number of stripes selected for the NMOS sense circuit is progressively decremented until the comparator output is high (step 516). Once again, if the comparator output is high and the procedure 500 has just been entered, an error condition exists where either target R.sub.ON value of the NMOSFET device is too small (i.e., cannot be achieved by selecting all stripes of the calibration sense NMOSFET 406) or the comparator threshold value was chosen incorrectly for the target R.sub.ON value; otherwise, the current number of stripes is written the register bank 416 (step 518) and the procedure ends. The target value of the ON resistances having thus been established and set, the NMR circuit is ready for operation.

(18) The calibration method 500 may be implemented in the controller 110. Controller 110 may be implemented in hardware, software or a combination of the two. For embodiments in which the functions of the controller are provided as one or more software programs, the programs may be written in any of a number of high level languages such as PYTHON, PASCAL, JAVA, C, C++, C#, BASIC, various scripting languages, and/or HTML. Additionally, the software can be implemented in an assembly language directed to the microprocessor resident on a target computer; for example, the software may be implemented in Intel 8086 assembly language if it is configured to run on an IBM PC or PC clone. The software may be embodied on an article of manufacture including, but not limited to, a floppy disk, a jump drive, a hard disk, an optical disk, a magnetic tape, a PROM, an EPROM, EEPROM, field-programmable gate array, or CD-ROM. Embodiments using hardware circuitry may be implemented using, for example, one or more FPGA, CPLD or ASIC processors. Controller 110 may be implemented in hardware, software or a combination of the two. For embodiments in which the functions are provided as one or more software programs, the programs may be written in any of a number of high level languages such as PYTHON, PASCAL, JAVA, C, C++, C#, BASIC, various scripting languages, and/or HTML. Additionally, the software can be implemented in an assembly language directed to the microprocessor resident on a target computer; for example, the software may be implemented in Intel 8086 assembly language if it is configured to run on an IBM PC or PC clone. The software may be embodied on an article of manufacture including, but not limited to, a floppy disk, a jump drive, a hard disk, an optical disk, a magnetic tape, a PROM, an EPROM, EEPROM, field-programmable gate array, or CD-ROM. Embodiments using hardware circuitry may be implemented using, for example, one or more FPGA, CPLD or ASIC processors.

(19) Approaches described herein may be particularly suitable for implementation in a low-field NMR system where multiple transceivers are integrated on the same semiconductor substrate such that multiple simultaneous NMR measurements can be performed at once. A single replica half circuit described above may be used to independently calibrate all on-chip PAs without the need for providing numerous external resistors to match the impedance of each individual PA.

(20) In addition, approaches described herein may be suitable for implementation in a low-field NMR system where an NMR coil is integrated on the same silicon substrate as the NMR transceiver, or on a separate silicon substrate but is encapsulated in the same package. In this situation, the calibration techniques described herein may provide precise and robust power delivery to the NMR coil without directly accessing and configuring the interface between the PA and NMR coil.

(21) An additional benefit is that this technique may also allow class-D PAs to be used with NMR probes having a significantly lower impedance. The ability to precisely control the output impedance at lower absolute impedance values is important because the same absolute variations of PA output impedance may result in larger relative variations of the delivered output power. In micro-NMR, it is desirable to shift from a 50 system to a lower-impedance system so as to increase the total available PA and delivered power for the same supply voltage V.sub.DDPA.

(22) The terms and expressions employed herein are used as terms and expressions of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described or portions thereof. In addition, having described certain embodiments of the invention, it will be apparent to those of ordinary skill in the art that other embodiments incorporating the concepts disclosed herein may be used without departing from the spirit and scope of the invention. Accordingly, the described embodiments are to be considered in all respects as only illustrative and not restrictive.