DISPLAY PANEL CONTROL METHOD AND DRIVING CIRCUIT THEREOF

Abstract

A display panel control method for a display panel. The display panel includes at least one common electrode line and a plurality of data lines. The method provides a timing control signal including an active interval and a vertical blanking interval. The timing control signal is used to make the display panel either enter the active interval or enter the vertical blanking interval to execute corresponding operation procedures. When the display panel is in the active interval, the method provides corresponding data voltage to every data line according to the image data. When the display panel is in the vertical blanking interval, the method provides a blanking data voltage to every data line. The blanking data voltage is determined according to the polarity of the corresponding data voltage of the corresponding data line and a common voltage of the at least one common electrode line.

Claims

1. A display panel driving method, adapted to a display panel that has a plurality of data lines and at least one common electrode line, the method comprising: providing a timing control signal, comprising an active interval and a vertical blanking interval, and configured to control the display panel in the active interval or in the vertical blanking interval to execute corresponding operation procedures; providing, when the display panel is in the active interval, a corresponding data voltage to each of the plurality of data lines according to image data; and providing, when the display panel is in the vertical blanking interval, a blanking data voltage to each of the plurality of data lines, wherein each blanking data voltage of the plurality of data lines is determined according to a polarity of the corresponding data voltage of every data line and a common voltage of the at least one common electrode line.

2. The method according to claim 1, wherein when the data voltage is positive, the blanking data voltage is a positive blanking data voltage; when the data voltage is negative, the blanking data voltage is a negative blanking data voltage; and an absolute difference value between the positive blanking data voltage and the common voltage is substantially equal to an absolute difference value between the negative blanking data voltage and the common voltage.

3. The method according to claim 2, wherein the positive blanking data voltage is greater than the common voltage, and the negative blanking data voltage is less than the common voltage.

4. The method according to claim 3, wherein the absolute difference value between the positive blanking data voltage and the common voltage is substantially equal to the absolute difference value between the negative blanking data voltage and the common voltage.

5. The method according to claim 3, wherein in any two adjacent data lines, when a data voltage of one data line is positive relative to the common voltage, a corresponding blanking data voltage is the positive blanking data voltage, a data voltage of the other data line is negative relative to the common voltage, and a corresponding blanking data voltage is the negative blanking data voltage.

6. A driving circuit, adapted to drive a display panel that has a plurality of data lines and at least one common electrode line, the driving circuit comprising: a blanking interval detector, configured to generate a selection signal, wherein the selection signal is configured to indicate an active interval or a vertical blanking interval; a source driver, electrically connected to the plurality of data lines; and a first multiplexer, electrically connected to the source driver and the blanking interval detector, wherein the first multiplexer is configured to control, according to the selection signal, the source driver to selectively provide a data voltage or a blanking data voltage to the source driver.

7. The driving circuit according to claim 6, wherein the source driver converts a data signal into a corresponding drive data voltage according to a polarity signal and a reference voltage that is received from the first multiplexer, wherein the first multiplexer comprises a plurality of sub-multiplexers, each of the plurality of sub-multiplexers of the first multiplexer comprising: a first input terminal, electrically connected to a corresponding data reference voltage source; a second input terminal, electrically connected to a corresponding blanking reference voltage source; a selection terminal, configured to receive the selection signal; and an output terminal, electrically connected to the source driver, wherein when the selection signal indicates the active interval, the first input terminal is conducted to the source driver, and when the selection signal indicates the vertical blanking interval, the second input terminal is conducted to the source driver.

8. The driving circuit according to claim 7, wherein the corresponding data reference voltage source is different from the corresponding blanking reference voltage source.

9. The driving circuit according to claim 6, wherein the first multiplexer comprises: a first input terminal, configured to receive a data signal; a second input terminal, configured to receive a blanking drive signal; a selection terminal, configured to receive the selection signal; and an output terminal, electrically connected to the source driver, wherein when the selection signal indicates the active interval, the output terminal is configured to output a data drive signal to the source driver according to the data signal, and when the selection signal indicates the vertical blanking interval, the output terminal is configured to output a positive blanking drive signal or a negative blanking drive signal to the source driver according to the blanking drive signal.

10. The driving circuit according to claim 9, further comprising a second multiplexer, wherein the second multiplexer comprises: a first input terminal, configured to receive the positive blanking drive signal; a second input terminal, configured to receive the negative blanking drive signal; a selection terminal, configured to receive a polarity signal; and an output terminal, electrically connected to the second input terminal of the first multiplexer, wherein when the polarity signal indicates positive, the output terminal is configured to output the positive blanking drive signal to the first multiplexer, and when the polarity signal indicates negative, the output terminal is configured to output the negative blanking drive signal to the first multiplexer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings illustrate one or more embodiments of the present disclosure and together with the written description, serve to explain the principles of the present disclosure. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment, and wherein:

[0013] FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0014] FIG. 2 is an equivalent circuit diagram of a pixel unit in FIG. 1 according to the present disclosure;

[0015] FIG. 3 is a schematic timing diagram of control signals of a display panel according to a comparative embodiment of the present disclosure;

[0016] FIG. 4A is a schematic diagram of a direction of charge transfer caused by capacitive coupling between pixel units and data lines under control timing of FIG. 3;

[0017] FIG. 4B is a schematic diagram of another direction of charge transfer caused by the capacitive coupling between the pixel units and the data lines under the control timing of FIG. 3;

[0018] FIG. 5 is a flowchart of a display panel control method according to an embodiment of the present disclosure;

[0019] FIG. 6 is a schematic timing diagram of control signals of a display panel according to an embodiment of a display panel control method of the present disclosure;

[0020] FIG. 7A is a schematic diagram of a direction of charge transfer caused by capacitive coupling between pixel units and data lines under control timing of FIG. 6;

[0021] FIG. 7B is a schematic diagram of another direction of charge transfer caused by the capacitive coupling between the pixel units and the data lines under the control timing of FIG. 6;

[0022] FIG. 8 is a schematic timing diagram of control signals of a display panel according to another embodiment of a display panel control method of the present disclosure;

[0023] FIG. 9 is a schematic functional block diagram of a driving circuit according to an embodiment of the present disclosure;

[0024] FIG. 10 is a schematic functional block diagram of a driving circuit according to another embodiment of the present disclosure; and

[0025] FIG. 11 is a schematic diagram of voltage levels illustrated according to data reference voltage sources and blanking reference voltage sources in FIG. 10.

DETAILED DESCRIPTION

[0026] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

[0027] Referring to FIG. 1, FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure. As shown in FIG. 1, a display panel 1000 has a display module 1100, a source driver 1200, a gate driver 1300, and a timing controller 1400. The display module 1100 is electrically connected to the source driver 1200 and the gate driver 1300, and the timing controller 1400 is electrically connected to the source driver 1200 and the gate driver 1300. Further, the display module 1100 has a plurality of data lines D.sub.1-D.sub.M, a plurality of gate lines G.sub.1-G.sub.N, and a plurality of pixel units P.sub.11-P.sub.NM. Each of the pixel units P.sub.11-P.sub.NM is electrically connected to one of the data lines D.sub.1-D.sub.M and one of the gate lines G.sub.1-G.sub.N. A first subscript of a reference sign of a pixel unit represents a row, and a second subscript represents a column, for example, the pixel unit P.sub.32 represents that the pixel unit is located at the third row and the second column. The pixel units P.sub.11-P.sub.NM are controlled by the source driver 1200 through the data lines D.sub.1-D.sub.M to which the pixel units are electrically connected, and the pixel units P.sub.11-P.sub.NM are controlled by the gate driver 1300 through the gate lines G.sub.1-G.sub.N to which the pixel units are electrically connected, where N and M are positive integers. The timing controller 1400 is configured to provide, according to an input signal S.sub.in, a corresponding data signal DAT, a start signal STB, or a polarity signal POL to the source driver 1200. The timing controller 1400 is further configured to provide, according to the input signal S.sub.in, a corresponding gate control signal GCT to the gate driver 1300, so as to enable the source driver 1200 and the gate driver 1300 to operate normally. Relevant details are known to a person of ordinary skill in the art, and are not described herein.

[0028] Referring to FIG. 2, FIG. 2 is an equivalent circuit diagram of a pixel unit in FIG. 1 according to the present disclosure. In FIG. 2, a pixel unit P.sub.nm is used as an example for description, where n is a positive integer less than N, m is a positive integer less than M, n represents that the pixel unit P.sub.nm is located at the nth row, and m represents that the pixel unit Pnm is located at the mth column. As shown in FIG. 2, an equivalent circuit of the pixel unit P.sub.nm has a thin film transistor (TFT) T, a storage capacitor C.sub.S, and a liquid crystal capacitor C.sub.LC. A first terminal of the TFT T is electrically connected to a data line D.sub.m, a second terminal of the TFT T is electrically connected to one end of the storage capacitor C.sub.S and one end of the liquid crystal capacitor C.sub.LC, and a control terminal of the TFT T is electrically connected to a gate line G.sub.n. As described earlier, one end of the storage capacitor C.sub.S and one end of the liquid crystal capacitor C.sub.LC are electrically connected to the second terminal of the TFT T, the other end of the storage capacitor C.sub.S is electrically connected to a first common electrode line COM1, so as to receive a first common voltage V.sub.COM1, and the other end of the liquid crystal capacitor C.sub.LC is electrically connected to a second common electrode line COM2, so as to receive a second common voltage V.sub.COM2. In an embodiment, a first common electrode line COM1 is electrically connected to a common electrode layer of an active element array, for example, and a second common electrode line COM2 is electrically connected to a common electrode layer of an opposite substrate or a color filter substrate, but the present disclosure is not limited thereto. In practice, the first common voltage V.sub.COM1 and the second common voltage V.sub.COM2 may be the same, or may be different, and the description below is made by using an example that the first common voltage V.sub.COM1 and the second common voltage V.sub.COM2 are the same.

[0029] The TFT T is selectively conducted according to a voltage level of the gate line G.sub.n. When the TFT T is conducted, the storage capacitor C.sub.S and the liquid crystal capacitor C.sub.LC are coupled to the data line D.sub.m, and therefore, at this time, a data signal on the data line D.sub.m is written into the storage capacitor C.sub.S and the liquid crystal capacitor C.sub.LC, so as to selectively charge a capacitor electrode or a pixel electrode in the pixel unit P.sub.nm according to the data signal. From another perspective, the gate driver 1300 sequentially provides, through the gate lines G.sub.1-G.sub.N, scan signals to the rows of pixel units P.sub.11-P.sub.NM, so as to sequentially conduct the TFTs of the pixel units P.sub.11-P.sub.NM in the rows of pixel units P.sub.11-P.sub.NM. When the TFTs are conducted, the capacitor electrodes or pixel electrodes in the pixel units P.sub.11-P.sub.NM are selectively charged according to the data signals on the data lines D.sub.1-D.sub.M to which the pixel units P.sub.11-P.sub.NM are electrically connected.

[0030] Besides, the equivalent circuit of the pixel unit P.sub.nm further has capacitors C.sub.gs, C.sub.pd, and C.sub.pd′. The capacitor C.sub.gs is a parasitic capacitor between the control terminal and the second terminal of the TFT T, the capacitor C.sub.pd is a coupling capacitor between the pixel electrode the data line D.sub.m, and the capacitor C.sub.pd′ is a coupling capacitor between the pixel electrode and the data line D.sub.m+1. Therefore, equivalently, in addition to that the storage capacitor C.sub.S and the liquid crystal capacitor C.sub.LC are respectively coupled to the first common voltage V.sub.COM1 and the second common voltage V.sub.COM2, potentials stored in the storage capacitor C.sub.S and the liquid crystal capacitor C.sub.LC are easily affected by data voltages of the data lines D.sub.m and D.sub.m+1. In other words, voltage levels of the data lines D.sub.m and D.sub.m+1 affect, through the coupling capacitors C.sub.pd and C.sub.pd′, electric energy stored in the storage capacitor C.sub.S and the liquid crystal capacitor C.sub.LC, so as to affect cross voltages of the storage capacitor C.sub.S and the liquid crystal capacitor C.sub.LC, and further affect a display image provided by the display panel 1000. In an embodiment, polarities of the voltages of the data lines D.sub.m and D.sub.m+1 are opposite, and the opposite polarities herein are defined relative to the second common voltage V.sub.COM2. The definition and the meaning thereof are known to a person of ordinary skill in the art, and details are not described herein. The subsequent embodiments are described by using like embodiments, and the feature is not further explained.

[0031] Referring to FIG. 1 to FIG. 3, how the data lines D.sub.m and D.sub.m+1 affect the electric energy stored in the storage capacitor C.sub.S and the liquid crystal capacitor C.sub.LC is described, and FIG. 3 is a schematic timing diagram of control signals of a display panel according to a comparative embodiment of the present disclosure. In order to achieve conciseness of description, it is defined that a node N.sub.p in FIG. 2 has a voltage level V.sub.p. As shown in FIG. 3, every frame f.sub.1, f.sub.2 interval includes an active interval A.sub.1, A.sub.2 (vertical active interval) and a vertical blanking interval B.sub.1, B.sub.2 (vertical blanking interval). In an active interval, the input signal S.sub.in bears relevant data to be displayed, and the voltage level of the input signal S.sub.in changes, so as to instruct the display panel 1000 to update the display image. Moreover, in a vertical blanking interval, the input signal S.sub.in does not need to instruct the display panel 1000 to update the display image, and therefore, the input signal S.sub.in is of a low voltage level.

[0032] In the frame f.sub.1, the polarity signal POL is of a high voltage level, and therefore, the source driver 1200 provides a positive data voltage to the data line D.sub.m and provides a negative data voltage to the data line D.sub.m+1. However, in the frame f.sub.2, the polarity signal POL is of a low voltage level, and therefore, the source driver 1200 provides a negative data voltage to the data line D.sub.m and provides a positive data voltage to the data line D.sub.m+1. When a voltage level of the gate line G.sub.n is of a high voltage level, the data voltage of the data line D.sub.m is written into the pixel unit P.sub.nm, and therefore, the voltage level V.sub.p of the node N.sub.p is pulled up to the high voltage level. Ideally, the voltage level V.sub.p of the node N.sub.p maintains the high voltage level in the frame f.sub.1. However, when the voltage level of the gate line G.sub.n changes from the high voltage level to a low voltage level, the voltage level V.sub.p is reduced by a feed through voltage difference ΔV.sub.FT due to an impact of instantaneous close of the TFT T. The feed through voltage difference ΔV.sub.FT is related to a feed through effect. The feed through effect is known to a person of ordinary skill in the art, and details are not described herein.

[0033] Besides, in the vertical blanking interval B.sub.1, the voltage level V.sub.p changes due to impacts of the coupling capacitors C.sub.pd, C.sub.pd′. Description is made by referring to FIG. 4A and FIG. 4B, FIG. 4A is a schematic diagram of a direction of charge transfer caused by capacitive coupling between pixel units and data lines under control timing of FIG. 3, and FIG. 4B is a schematic diagram of another direction of charge transfer caused by the capacitive coupling between the pixel units and the data lines under the control timing of FIG. 3. As shown in the figures, in the vertical blanking interval B.sub.1, the data line D.sub.m pulls up the voltage level of the node N.sub.p through the capacitor C.sub.pd, and the data line D.sub.m+1 pulls down the voltage level of the node N.sub.p through the capacitor C.sub.pd′, as shown in FIG. 4A. However, in the frame f.sub.2, polarities of the voltage levels of the data lines D.sub.m and Dm+1 are reversed, and therefore, in the vertical blanking interval B.sub.2, the data line D.sub.m pulls up the voltage level of the node N.sub.p through the capacitor C.sub.pd, and the data line D.sub.m+1 pulls up the voltage level of the node N.sub.p through the capacitor C.sub.pd′, as shown in FIG. 4B. In other words, with a conventional control manner, in the vertical blanking intervals of adjacent frames, coupling effects between the pixel unit P.sub.nm and the capacitors C.sub.pd and C.sub.pd′ are not the same, so that changes of the voltage level V.sub.p are not fixed, and consequently, the display image is subject to an unexpected change of brightness, which is hardly compensated and corrected.

[0034] In view of that, the present disclosure provides a display panel control method. Description is made by referring to FIG. 5, and FIG. 5 is a flowchart of a display panel control method according to an embodiment of the present disclosure. The display panel control method provided in the present disclosure is adapted to control a display panel. The display panel has a plurality of data lines and one common electrode line, where polarities of two adjacent data lines in the data lines are reverse. Step S501 provides a timing control signal, including an active interval and a vertical blanking interval, and configured to make the display panel enter the active interval or the vertical blanking interval to execute corresponding operation procedures. Step S503 provides that when the display panel is in the active interval, a corresponding data voltage to every data line according to image data. Step S505 provides that when the display panel is in the vertical blanking interval, a blanking data voltage to every data line. Every blanking data voltage is determined according to a polarity of the data voltage of the corresponding data line and a common voltage of the common electrode line. Further description is made by referring to FIG. 6, and FIG. 6 is a schematic timing diagram of control signals of a display panel according to an embodiment of a display panel control method of the present disclosure. Different from the foregoing comparative embodiment, in the embodiments corresponding to FIG. 5 and FIG. 6, at a frame f.sub.3 interval, a voltage level of a data line D.sub.m is adjusted to a positive blanking data voltage V.sub.1′ in a vertical blanking interval B.sub.3, and a voltage level of a data line D.sub.m+1 is adjusted to a negative blanking data voltage V.sub.2′ in the vertical blanking interval B.sub.3. The positive blanking data voltage V.sub.1′ and the negative blanking data voltage V.sub.2′ are determined according to a second common voltage V.sub.COM2 of a second common electrode line COM2. However, in a vertical blanking interval B.sub.4 of a frame f.sub.4 interval, due to polarity reversal, the voltage level of the data line D.sub.m is adjusted to the negative blanking data voltage V.sub.2′, and the voltage level of the data line D.sub.m+1 is adjusted to the positive blanking data voltage V.sub.1′.

[0035] In an embodiment, the positive blanking data voltage V.sub.1′ and the negative blanking data voltage V.sub.2′ are symmetrical relative to the second common voltage V.sub.COM2. More specifically, an absolute value of a difference between the positive blanking data voltage V.sub.1′ and the second common voltage V.sub.COM2 is the same as an absolute value of a difference between the negative blanking data voltage V.sub.2′ and the second common voltage V.sub.COM2. From another perspective, the second common voltage V.sub.COM2 is approximately equal to an average value of the positive blanking data voltage V.sub.1′ and the negative blanking data voltage V.sub.2′. In another embodiment, a positive blanking data voltage V.sub.1′ and a negative blanking data voltage V.sub.2′ are further slightly adjusted according to a second common voltage V.sub.COM2 and capacitors C.sub.pd and C.sub.pd′.

[0036] Referring to FIG. 7A and FIG. 7B together, FIG. 7A is a schematic diagram of a direction of charge transfer caused by capacitive coupling between pixel units and data lines under control timing of FIG. 6, and FIG. 7B is a schematic diagram of another direction of charge transfer caused by the capacitive coupling between the pixel units and the data lines under the control timing of FIG. 6. As shown in FIG. 6 and FIG. 7A, in a frame f.sub.3 interval, when the pixel unit P.sub.nm is driven by a positive driving signal, in the corresponding vertical blanking interval, the voltage level of the node N.sub.p is pulled down by the data lines D.sub.m, D.sub.m+1, and the voltage level V.sub.p gets close to the second common voltage V.sub.COM2. As shown in FIG. 6 and FIG. 7B, at a frame f.sub.4 interval, when the pixel unit P.sub.nm is driven by a negative driving signal, in the corresponding vertical blanking interval, the voltage level of the node N.sub.p is pulled up by the data lines D.sub.m, D.sub.m+1, and the voltage level V.sub.p also gets close to the second common voltage V.sub.COM2. Therefore, even the pixel unit P.sub.nm is driven by signals of different polarities in the vertical blanking intervals of different frames, the voltage level V.sub.p gets close to the second common voltage V.sub.COM2, so that light emitted by the pixel unit P.sub.nm in the vertical blanking intervals of different frames becomes dimmer or brighter. For example, when twisted nematic liquid crystal (TN) is used, a decreased voltage enables an image to become brighter, and when vertical alignment liquid crystal (VA) is used, a decreased voltage enables an image to become dimmer. However, no matter which type of liquid crystal is used, light emission of the pixel unit Pnm in the vertical blanking intervals becomes expectable, which alleviates a flicker problem of the image, and facilitates correction and compensation.

[0037] Further referring to FIG. 6, FIG. 7A, and FIG. 7B, in a variant embodiment of this embodiment, in a frame f.sub.3 interval, a voltage level of a data line D.sub.m is adjusted to a negative blanking data voltage V.sub.2 in a vertical blanking interval B.sub.3, and a voltage level of a data line D.sub.m+1 is adjusted to a positive blanking data voltage V.sub.1′ in the vertical blanking interval B.sub.3. However, in a vertical blanking interval B.sub.4 of a frame f.sub.4 interval, due to polarity reversal, the voltage level of the data line D.sub.m is adjusted to the positive blanking data voltage V.sub.1′, and the voltage level of the data line D.sub.m+1 is adjusted to the negative blanking data voltage V.sub.2′. With regard to directions of charge transfer, as shown in FIG. 7A and FIG. 7B, in the vertical blanking interval of the frame f.sub.3 interval, a voltage level of a node N.sub.p is pulled down by the data lines D.sub.m, D.sub.m+1, and the voltage level V.sub.p gets close to a second common voltage V.sub.COM2; and in the vertical blanking interval of the frame f.sub.4 interval, the data lines D.sub.m, D.sub.m+1 pulls up the voltage level of the node N.sub.p, the voltage level V.sub.p also gets close to the second common voltage V.sub.COM2. This variant embodiment differs from the foregoing embodiment in that a time point for polarity reversal of a data signal is in a vertical blanking interval, for example, a time point for polarity reversal of a POL signal may be before the vertical blanking interval B.sub.3. Further referring to FIG. 8, FIG. 8 is a schematic timing diagram of control signals of a display panel according to another embodiment of a display panel control method of the present disclosure. As shown in FIG. 8, in an active interval A.sub.5, a voltage level V.sub.p is first pulled up to a desired voltage value, and then is decreased by a feed through voltage difference ΔV.sub.FT due to a feed through effect caused by instantaneous close of a TFT T. However, in a subsequent vertical blanking interval B.sub.5, a voltage level of a data line D.sub.m is pulled down to a positive blanking data voltage V.sub.1″, and a voltage level of a data line D.sub.m+1 is pulled down to a negative blanking data voltage V.sub.2″. In this embodiment, the positive blanking data voltage V.sub.1″ is set as the voltage level V.sub.p in the active interval A.sub.5 that is obtained after being affected by the feed through effect, and a voltage level of the negative blanking data voltage V.sub.2″ and a voltage level of the positive blanking data voltage V.sub.1″ are symmetrical relative to a second common voltage V.sub.COM2. Therefore, in the vertical blanking interval B.sub.5, the voltage level V.sub.p gets close to the second common voltage V.sub.COM2.

[0038] Similarly, in an active interval A.sub.6, a voltage level V.sub.p is first pulled down to a desired voltage value, and then is further decreased by a feed through voltage difference ΔV.sub.FT due to a feed through effect caused by instantaneous close of the TFT T. However, in a subsequent vertical blanking interval B.sub.6, the voltage level of the data line D.sub.m is pulled down to the negative blanking data voltage V.sub.2″, and the voltage level of the data line D.sub.m+1 is pulled down to the positive blanking data voltage V.sub.1″. In this embodiment, the negative blanking data voltage V.sub.2″ is set as the voltage level V.sub.p at the active interval A.sub.6 that is obtained after being affected by the feed through effect, and the voltage level of the positive blanking data voltage V.sub.1″ and the voltage level of the negative blanking data voltage V.sub.2″ are symmetrical relative to the second common voltage V.sub.COM2. Therefore, similar to the vertical blanking interval B.sub.5, in the vertical blanking interval B.sub.6, the voltage level V.sub.p also gets close to the second common voltage V.sub.COM2. Therefore, in the embodiment shown in FIG. 8, light emission of the pixel unit P.sub.nm in the vertical blanking intervals also becomes expectable, which alleviates a flicker problem of an image, and facilitates correction and compensation.

[0039] In continuation to the foregoing concepts, the present disclosure further provides a driving circuit. Description is made by referring to FIG. 9, and FIG. 9 is a schematic functional block diagram of a driving circuit according to an embodiment of the present disclosure. The driving circuit 1500 is adapted to drive a display panel 1000. The display panel 1000 has a plurality of data lines D.sub.1-D.sub.M and at least one common electrode line. The driving circuit 1500 includes a source driver 1200 and a timing control module 1400, and the timing control module 1400 is electrically connected to the source driver 1200. The timing control module 1400 includes a blanking drive control module 1600, a blanking interval detector 1440, a data mapping module 1460, and a timing control unit 1480. The blanking drive control module 1600 includes a first multiplexer 1640, a second multiplexer 1660, a positive blanking signal module 1670, and a negative blanking signal module 1680. The first multiplexer 1640 has a first input terminal N.sub.1, a second input terminal N.sub.2, a selection terminal N.sub.3, and an output terminal N.sub.4. The second multiplexer 1660 has a first input terminal N.sub.5, a second input terminal N.sub.6, a selection terminal N.sub.7, and an output terminal N.sub.8.

[0040] More specifically, the blanking interval detector 1440, the data mapping module 1460, and the timing control unit 1480 receive an input signal S.sub.in. The blanking interval detector 1440 is electrically connected to the selection terminal N.sub.3 of the first multiplexer 1640 of the blanking drive control module 1600. The data mapping module 1460 is electrically connected to the first input terminal N.sub.1 of the first multiplexer 1640. The second input terminal N.sub.2 of the first multiplexer 1640 is electrically connected to the output terminal N.sub.8 of the second multiplexer 1660. The first input terminal N.sub.5 of the second multiplexer 1660 is coupled to the positive blanking drive signal module 1670, and the second input terminal N.sub.6 is coupled to the negative blanking drive signal module 1680. The selection terminal N.sub.7 of the second multiplexer 1660 is electrically connected to the timing control unit 1480, so as to receive a polarity signal POL.

[0041] The blanking interval detector 1440 is configured to detect, according to the input signal S.sub.in, whether a current time point is in the vertical blanking interval, and generate, on the basis of the foregoing detection, a selection signal V.sub.B for the first multiplexer 1640. The data mapping module 1460 is configured to generate, according to the input signal S.sub.in, a data signal for the first multiplexer 1640. The timing control unit 1480 is configured to generate a polarity signal POL, a timing control signal GTC, and a start signal XSTB according to the input signal S.sub.in. The relevant details are known to a person of ordinary skill in the art, and are not described herein. When the selection signal V.sub.B indicates an active interval, the first multiplexer 1640 is controlled by the selection signal V.sub.B to output a data signal generated by the data mapping module 1460 to the source driver 1200. However, when the selection signal V.sub.B indicates a vertical blanking interval, the first multiplexer 1640 is controlled by the selection signal V.sub.B to output a positive blanking drive signal or a negative blanking drive signal to the source driver 1200.

[0042] The first input terminal N.sub.5 of the second multiplexer 1660 is configured to receive a positive blanking signal of the positive blanking signal module 1670. The second input terminal N.sub.6 is configured to receive a negative blanking signal of the negative blanking signal module 1680. The selection terminal N.sub.7 is configured to receive the polarity signal POL. The output terminal N.sub.8 is electrically connected to the second input terminal N.sub.2 of the first multiplexer 1640. When the polarity signal POL indicates positive, the second multiplexer 1660 outputs the positive blanking drive signal to the first multiplexer 1640, and when the polarity signal POL indicates negative, the second multiplexer 1660 outputs the negative blanking drive signal to the first multiplexer 1640.

[0043] The source driver 1200 is electrically connected to the first multiplexer 1640, and is electrically connected to the data lines D.sub.1-D.sub.M so as to respectively output a plurality of data signals to the data lines D.sub.1-D.sub.M. When the selection signal V.sub.B received by the first multiplexer 1640 indicates an active interval, the first multiplexer 1640 controls the source driver 1200 to provide a corresponding data voltage to every data line D.sub.1-D.sub.M. When the selection signal V.sub.B received by the first multiplexer 1640 indicates a vertical blanking interval, the first multiplexer 1640 controls, according to the blanking drive signal, the source driver 1200 to provide a corresponding blanking data voltage to every data line D.sub.1-D.sub.M, for example, separately provide the foregoing positive blanking data voltages V.sub.1′, V.sub.1″ or the foregoing negative blanking data voltages V.sub.2′, V.sub.2″ to the data line Dm and the data line D.sub.m+1 according to the corresponding polarities.

[0044] Further referring to FIG. 10, FIG. 10 is a schematic functional block diagram of a driving circuit according to another embodiment of the present disclosure. In the embodiment shown in FIG. 10, data reference voltage sources 16441-1644N may be a same voltage source or different voltage sources. Similarly, blanking reference voltage sources N10_1-N10_N may be a same voltage source or different voltage sources, and sub-multiplexers 16421-1642N may be replaced by a 2N−1 multiplexer. In order to achieve conciseness of description, the data reference voltage sources 16441-1644N, the blanking reference voltage sources N10_1-N10_N, and the sub-multiplexers 16421-1642N are used as examples for description, but in practice, the present disclosure is not limited to the figure.

[0045] In the embodiment of FIG. 10, a driving circuit 1600′ is separated from a timing controller 1400. A source driver 1200 converts data signals DAT into corresponding drive voltages according to polarity signals POL, and reference voltages V.sub.G1-V.sub.GM received from a first multiplexer 1640, and provides the drive voltages to pixel units P.sub.11-P.sub.NM through data lines D.sub.1-D.sub.M. The first multiplexer 1640 includes sub-multiplexers 16421-1642M, and each of the sub-multiplexers 16421-1642M includes a first input terminal N.sub.9.sub._.sub.1-N.sub.9.sub._.sub.M, a second input terminal N.sub.10.sub._.sub.1-N.sub.10.sub._.sub.M, a selection terminal N.sub.11.sub._.sub.1-N.sub.11.sub._.sub.M, and an output terminal N.sub.12.sub._.sub.1-N.sub.12.sub._.sub.M. Using the sub-multiplexer 16421 as an example, the first input terminal N.sub.9.sub._.sub.1 is electrically connected to the data reference voltage source 16441. The second input terminal N.sub.10.sub._.sub.1 is electrically connected to the blanking reference voltage source 16461. The selection terminal N.sub.11.sub._.sub.1 is configured to receive the selection signal V.sub.B. The output terminal N.sub.12.sub._.sub.1 is electrically connected to the source driver 1200. When the selection signal V.sub.B indicates an active interval, the first input terminal N.sub.9.sub._.sub.1 is electrically connected to the source driver 1200, that is, at this time, a data voltage generated by the data reference voltage source 16441 is provided to the source driver 1200 through the sub-multiplexer 16421. When the selection signal V.sub.B indicates a vertical blanking interval, the second input terminal N.sub.10.sub._.sub.1 is electrically connected to the source driver 1200, that is, at this time, a positive blanking voltage or a negative blanking voltage generated by the blanking reference voltage source 16461 is provided to the source driver 1200 through the multiplexer 16421.

[0046] Referring to FIG. 11 for description of differences between the data reference voltage sources 16441-1644M and the blanking reference voltage sources 16461-1646M in FIG. 10, FIG. 11 is a schematic diagram of voltage levels illustrated according to data reference voltage sources and blanking reference voltage sources of FIG. 10. Using the data reference voltage source 16441 and the blanking reference voltage source 16461 as examples, output voltage values of the data reference voltage source 16441 may be classified into a positive group P and a negative group N as shown at a left side of FIG. 11, and each of the positive group P and the negative group N has 256 possible voltage values V.sub.0-V.sub.255. In the positive group P, the voltage value V.sub.0 is less than the voltage value V.sub.1, the voltage value V.sub.1 is less than the voltage value V.sub.2. In the negative group N, the voltage value V.sub.255 is less than the voltage value V.sub.254, the voltage value V.sub.254 is less than the voltage level V.sub.253. Output voltage values of the blanking reference voltage source 16461 may be classified into a positive group P′ and a negative group N′ at a right side of FIG. 11, and each of the positive group P′ and the negative group N′ also has 256 possible voltage values V.sub.0′-V.sub.255′. The value relationships between the voltage values V.sub.0′-V.sub.255′ in different groups are similar to those of the voltage values V.sub.0-V.sub.255.

[0047] The difference between the voltage values V.sub.0′-V.sub.255′ and the voltage values V.sub.0-V.sub.255 is that the voltage values V.sub.0′-V.sub.255′ in the positive group P′ and the voltage values V.sub.0′-V.sub.255′ in the negative group N′ are symmetrical relative to a second common voltage V.sub.COM2, and the voltage values V.sub.0-V.sub.255 in the positive group P and the voltage values V.sub.0-V.sub.255 of the negative group N are not necessarily symmetrical relative to the second common voltage V.sub.COM2. More specifically, an absolute difference value between the voltage value V.sub.0′ in the positive group P′ and the second common voltage V.sub.COM2 is equal to an absolute difference value between the voltage value V.sub.0′ in the negative group N′ and the second common voltage V.sub.COM2. An absolute difference value between the voltage value V.sub.1′ in the positive group P′ and the second common voltage V.sub.COM2 is equal to an absolute difference value between the voltage value V.sub.1′ in the negative group N′ and the second common voltage V.sub.COM2. Besides, in this embodiment, upon comparison, the voltage value V.sub.0 in the positive group P is greater than the voltage value V.sub.0′ in the positive group P′ by one feed through voltage difference ΔV.sub.FT, the voltage value V.sub.0 in the negative group N is greater than the voltage value V.sub.0′ in the negative group N′ by one feed through voltage difference ΔV.sub.FT. Relationships between other voltage values V.sub.2′-V.sub.255′ in different groups can be derived in accordance thereto, and details are not described herein again.

[0048] To sum up, the present disclosure provides a display panel control method and a driving circuit thereof, in which a corresponding data voltage is provided to every data line in an active interval according to image data. In a vertical blanking interval, a positive blanking data voltage is provided to one of two adjacent data lines, or a negative blanking data voltage is provided to the other data line of the two adjacent data lines. In this way, directions of charge transfer caused by capacitive coupling between pixel units and adjacent data lines are the same, so as to alleviate flicker of a display panel, and enable a display image in a vertical blanking interval to become predictable. A voltage provided to a data line in a vertical blanking interval is determined according to a common voltage of a common electrode line.

[0049] The foregoing description of the exemplary embodiments of the invention has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.

[0050] The embodiments were chosen and described in order to explain the principles of the invention and their practical application so as to activate others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope. Accordingly, the scope of the present disclosure is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.