Methods and Apparatus for Sharing Nodes in a Network with Connections Based on 1 to K+1 Adjacency Used in an Execution Array Memory Array (XarMa) Processor

Abstract

An Execution Array Memory Array (XarMa) processor is described for signal processing and internet of things (IoT) applications, (pronounced sharma, that means happiness in Sanskrit). The XarMa processor uses a 1 to K+1 adjacency network in an array of execution units. The 1 to K+1 adjacency refers to connections separately made in rows and in columns of execution unit and local file nodes, where the number of R.sub.owsK>1 and of C.sub.olumnsK>1 and K is an odd integer. Instead of a large central multi-ported register file, a distributed set of storage files local to each execution unit is used. The instruction set architecture uses instructions that specify forwarding of execution results to execution units associated with destination instructions. This execution array is scalable to support cost effective and low power high-performance application specific processing focused on target product requirements.

Claims

1. A method of executing a sequence of instructions in an execution unit (EU) node in an array of EUnits, the method comprising: receiving a first instruction and a destination instruction having a dependency on the first instruction, wherein the first instruction identifies the destination instruction in a sequence of instructions from a program and specifies that a result generated by execution of the first instruction by a first EU node is to be forwarded to a destination EU node that is to execute the destination instruction; executing the first instruction on the first EU.sub.r,c node to generate the result for delivery through an EU network to the destination EU node associated with the identified destination instruction, wherein according to a Row by Column (RC) matrix, an RC array of EU row(r),column(c) nodes are interconnected by the EU network, the EU network comprising (K+1) by (K+1) array of EU.sub.r,c nodes, a first stage (K+1)(K+1) array of R.sub.r,c nodes for a first direction of communication, a second stage (K+1)(K+1) array of S.sub.r,c nodes for a second direction of communication, and in each stage having wiring configured according to a 1 to K+1 adjacency of connections between nodes which includes wrapping around data paths at the edges of the (K+1)(K+1) arrays, K is an odd integer, K>1, R(K+1), C(K+1), re {0, 1, . . . , K}, and c{0, 1, . . . , K}, and wherein connections exist between each EU.sub.r,c node and R.sub.r,c nodes with the same row number in the first direction of communication, the first EU.sub.r,c node generates the result for a selectable first data path that connects to an R.sub.r,c+1 node and for a selectable second data path that connects to an R.sub.r,c1 node for single step adjacency and for a selectable third data path that connects to an R.sub.r,c+2 node for two step adjacency, and for a selectable fourth data path that connects to an R.sub.r,c node in the same r,c position in the RC matrix as the connecting EU.sub.r,c node, and wherein connections exist between each R.sub.r,c node and S.sub.r,c nodes with the same column number in the second direction of communication, wherein an R.sub.r,c node, associated with a selected path in the first direction of communication, produces the result for a selectable first data path that connects to an S.sub.r+1,c node and for a second data path that connects to an S.sub.r1,c node for single step adjacency and for a third data path that connects to an S.sub.r+2,c node for two step adjacency, and for a fourth data path that connects to an S.sub.r,c node in the same r,c position in the RC matrix as the connecting R.sub.r,c node, wherein an S.sub.r,c node, associated with the selected data path in the second direction of communication, produces the result on a destination data path that connects to the destination EU node to be received at the destination EU node; and executing the destination instruction in the destination EU node based on the received result to produce a destination result for use by the program.

2. The method of claim 1, wherein the R.sub.r,c nodes are 44 crossbars having four inputs and four outputs and the Sr,c nodes are 41 multiplexers having four inputs and one output.

3. The method of claim 1 further comprising: wrapping around when R.sub.r,c+1=R.sub.r,K+1 in the first direction of communication to R.sub.r,0 for single step adjacency; wrapping around when R.sub.r,c1=R.sub.r,1 in the first direction of communication to R.sub.r,K for single step adjacency; and wrapping around when R.sub.r,c+2=R.sub.r,K+2 in the first direction of communication to R.sub.r,1 for two step adjacency.

4. The method of claim 1 further comprising: wrapping around when S.sub.r+1,c=S.sub.K+1,c in the second direction of communication to S.sub.0,c for single step adjacency; wrapping around when S.sub.r1,c=S.sub.1,c in the second direction of communication to S.sub.K,c for single step adjacency; and wrapping around when S.sub.r+2,c=S.sub.K+2,c in the second direction of communication to R.sub.1,c for two step adjacency.

5. The method of claim 1 further comprising: executing a second instruction on a second EU.sub.r,c node to generate a second result for a selectable fifth data path that connects to the R.sub.r,c node, associated with the selected path in the first direction of communication; producing the second result on the R.sub.r,c node, associated with the selected path in the first direction of communication, for a selectable fifth data path that connects to the S.sub.r,c node, in the same r,c position in the RC matrix as the connecting R.sub.r,c node; and producing the second result, by the S.sub.r,c node associated with the selected data path in the second direction of communication, on a second destination data path that connects to the destination EU node to be received at the destination EU node.

6. The method of claim 5, wherein the R.sub.r,c nodes are 45 crossbars having four inputs and five outputs and the S.sub.r,c nodes are 52 multiplexers having five inputs and two outputs.

7. The method of claim 1 further comprising: setting a program counter mode control to master mode: and controlling the instruction sequence from the program for operation of the K+1 rows of the RC array of EU.sub.row(r),column(c) nodes by using the program counter for row 0 and making program counters for rows 1 to row K to be in a not used state.

8. The method of claim 1 further comprising: setting a program counter mode control to not master mode; and controlling the instruction sequence from the program for each row of the RC array of EU.sub.row(r),column(c) nodes using K+1 program counters for separate control of rows 0 to row K to be in an active state.

9. A network organized according to a 1 by Column (1C) matrix, the network comprising: a 1C array of EU.sub.1,column(c) nodes interconnected by an EU network, the EU network comprising 1 by (K+1) array of EU.sub.1,c nodes connected to a 1(K+1) array of R.sub.1,c nodes for a first direction of communication, and having wiring configured according to a 1 to K+1 adjacency of connections between the EU.sub.1,c nodes and the R.sub.1,c nodes which includes wrapping around data paths at the edges of the 1(K+1) arrays, K is an odd integer, K>1, C(K+1), and c{0, 1, . . . , K} and wherein connections exist between each EU.sub.1,c node and R.sub.1,c nodes in the first direction of communication, a first EU.sub.1,c node is connected by a first data path to an R.sub.1,c+1 node and by a second data path to an R.sub.1,c1 node for single step adjacency and by a third data path to an R.sub.1,c+2 node for two step adjacency, and by a fourth data path to an R.sub.1,c node in the same 1,c position in the 1C matrix as the first EU.sub.1,c node, wherein the R.sub.1,c1 node is connected by a first outputA path to its associated EU.sub.1,c1 node, the R.sub.1,c node is connected by a second outputA path to its associated EU.sub.1,c node, the R.sub.1,c+1 node is connected by a third outputA path to its associated EU.sub.1,c+1 node, and the R.sub.1,c+2 node is connected by a fourth outputA path to its associated EU.sub.1,c+2 node.

10. The network of claim 9, wherein the R.sub.r,c nodes comprise: 41 multiplexers, in the R.sub.r,c nodes, having four inputs and one output.

11. The network of claim 9, wherein the R.sub.1,c1 node is connected by a first outputB path to its associated EU.sub.1,c1 node, the R.sub.1,c node is connected by a second outputB path to its associated EU.sub.1,c node, the R.sub.1,c+1 node is connected by a third outputB path to its associated EU.sub.1,c+1 node, and the R.sub.1,c+2 node is connected by a fourth outputB path to its associated EU.sub.1,c+2 node.

12. The network of claim 11, wherein the R.sub.r,c nodes comprise: 42 crossbars, in the R.sub.r,c nodes, having four inputs and two outputs.

13. The network of claim 9 further comprising: the first data path is wrapped around when R.sub.1,c+1=R.sub.1,K+1 in the first direction of communication to R.sub.r,0 for single step adjacency; the second data path is wrapped around when R.sub.1,c1=R.sub.1,1 in the first direction of communication to R.sub.r,K for single step adjacency; and the third data path is wrapped around when R.sub.1,c+2=R.sub.1,K+2 in the first direction of communication to R.sub.r,1 for two step adjacency.

14. The network of claim 9 further comprising: connecting two 1C arrays of EU.sub.1,column(c) nodes by a second stage (K+1)(K+1) array of S.sub.r,c nodes for a second direction of communication, wherein each R.sub.r,c node is connected by a selectable first data path to an S.sub.r+1,c node and by a second data path to an S.sub.r1,c node for single step adjacency and by a third data path to an S.sub.r+2,c node for two step adjacency, and by a fourth data path to an S.sub.r,c node in the same r,c position in the RC matrix as the connecting R.sub.r,c node, wherein each S.sub.r,c node is connected by a destination data path to a corresponding destination EU.sub.r,c node.

15. The network of claim 14, wherein the R.sub.r,c nodes and S.sub.r,c nodes comprise: 42 multiplexers in the Rr,c nodes having four inputs and one output; and 21 multiplexers in the Sr,c nodes having two inputs and one output.

16. A system apparatus comprising: a load unit having a source of data values external to an array of execution unit (EU) nodes that are interconnected by an EU network; a first multiplexing element in the load unit to connect externally received data values to an EU located in the EU network for processing by one or more program instructions; a store unit having a source of data values internal to the array of EU nodes; a second multiplexing element in the store unit to connect to the EU network to receive data values from an EU source and connect the internally received data values to a destination node located external to the EU network for processing by the destination node, wherein the load unit is combined with the store unit as a single node of the array of EU nodes.

17. The system apparatus of claim 16, wherein the source of data values comprises: a memory unit having a read port providing the source of data values.

18. The system apparatus of claim 16 wherein the destination node comprises: a memory unit having a write port to receive the data values from the EU source and store the received data values in the memory.

19. The system apparatus of claim 16 wherein the EU network comprises: an RowColumn (RC) array of EU.sub.row(r),column(c) nodes interconnected by the EU network, the EU network comprising (K+1) by (K+1) array of EU.sub.r,c nodes, a first stage of (K+1)(K+1) array of R.sub.r,c nodes for a first direction of communication, a second stage of (K+1)(K+1) array of S.sub.r,c nodes for a second direction of communication, and in each stage having wiring configured according to a 1 to K+1 adjacency of connections between nodes which includes wrapping around data paths at the edges of the (K+1)(K+1) arrays, K is an odd integer, K>1, R(K+1), C(K+1), r{0, 1, . . . , K}, and c{0, 1, . . . , K}, and wherein connections exist between each EU.sub.r,c node and R.sub.r,c nodes with the same row number in the first direction of communication, and wherein connections exist between each R.sub.r,c node and S.sub.r,c nodes with the same column number in the second direction of communication, and wherein each S.sub.r,c node is connected to corresponding EU.sub.r,c nodes.

20. The apparatus of claim 19, wherein the load unit connects to the EU network as an EU.sub.r,c node connects in the first direction of communication to an R.sub.r,c node to send a load supplied value to the EU network and the store unit connects to the EU network as an EU.sub.r,c node to receive an EU network provided value from an S.sub.r,c node output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 illustrates exemplary specifiable paths in an array beginning from a source node to nodes in a K+1.sub.row by K+1.sub.column array of nodes interconnected by a K+1 adjacency network, wherein K is an odd integer >1, in accordance with an embodiment of the present invention;

[0014] FIG. 2 illustrates an execution array organized in an exemplary 4 row by 4 column arrangement of execution units and local files in a physical layout form with a one to K+1 level adjacency, where K is a positive odd integer, in accordance with an embodiment of the present invention;

[0015] FIG. 3 illustrates exemplary specifiable paths in a 44 array of nodes beginning from a source node to nodes in a K+1.sub.row by K+1.sub.column array of nodes interconnected by a K+1 adjacency network with an increased number of internode data paths, wherein K is an odd integer >1, in accordance with an embodiment of the present invention;

[0016] FIG. 4 illustrates a control system for a R=4C=4 XarMa processor comprising row 0-3 control units with corresponding prolog instruction code (PIC) memories in accordance with an embodiment of the present invention; and

[0017] FIG. 5 illustrates three RC XarMa processors that are based on the 44 Execution unit (EU) array of FIGS. 1-4 in accordance with embodiments of the invention.

DETAILED DESCRIPTION

[0018] While the present invention is disclosed in a presently preferred context, it will be recognized that the teachings of the present invention may be variously embodied consistent with the disclosure and claims. It will be recognized that the present teachings may be adapted to other present and future architectures to which they may be beneficial.

[0019] In order to amortize development costs for such devices across multiple products targeted for different applications, a scalable architecture with multiple design points using the same instruction set architecture is proposed. To address low power, high performance, and scalability, a new architecture is presented that reduces storage of temporary variables lowering power usage, provide efficient processor and shared memory transfers, and is scalable.

[0020] FIG. 1 illustrates exemplary specifiable paths in an array 100 from a single node (Nb11) 102 to nodes in a K+1.sub.row by K+1.sub.column array of nodes Na00 110 to Na33 125 interconnected by a K+1 adjacency network, wherein K is an odd integer >1, in accordance with an embodiment of the present invention. Array notation is used with nodes, such as Na00=Na.sub.row=0.sub.column=0. The Na00-Na33 nodes 110-125, such as Na11 115, also shown in exemplary node illustration 157, may be processor nodes (Pa), or memory nodes (Ma), or execution unit nodes (Xa), or local file nodes (LFa). The single Nb11 node 102 is one of a 44 array of nodes Nb00 to Nb33, not shown for reason of clarity in the drawing. The Nb00 -Nb33 nodes may also be processor nodes (Pb), or memory nodes (Mb), or execution unit nodes (Xb), or local file nodes (LFb). There is also a 44 array of R.sub.r,c 44 crossbar nodes of which nodes R10 130, R11 131, R12 132, and R13 133 are shown. There is further shown a 44 array of S.sub.r,c 41 multiplexer nodes including S00 41 140 to S33 41 155 nodes. FIG. 2 shows all the nodes together. An exemplary R.sub.r,c node 176 is configured with four 4 to 1 multiplexers (41) 177. An exemplary S.sub.r,c node 178 is configured with one 4 to 1 multiplexer (41) 179. The horizontal row data buses 135-138 and vertical column data buses 160-175 are Bb-bits, for example Bb=16-bits or 32-bits or 64-bits, and the like. Generally, the bus paths for Nb.sub.r,c.fwdarw.R.sub.r,c, R.sub.r,c.fwdarw.S.sub.r,c, and S.sub.r,c.fwdarw.(Pa/Ma/Xa/LFa).sub.r,c, having the same r and the same c, are prioritized for short layouts, such as the case where Nb.sub.r,c is a processor and the S.sub.r,c node connects to a memory node Ma.sub.r,c.

[0021] To illustrate an exemplary data path, the node Nb11 102 is designed to be an execution unit, so is referenced here in this description as Xb11. The execution unit Xb11 102 generates a result upon executing an instruction which is programmatically directed to use one or more selectable data buses 135-138, such as the data bus 135. The data buses 135-138 comprise data buses 135 and 137 having connections between the Xb11 node 102 and the R.sub.1,0 node 130 and the R.sub.1,2 node 132 with the same row number in the first direction of communication of single step adjacency between next door adjacent neighbors. The first direction of communication of single step adjacency for the Xb11 node is communication in the east and west horizontal direction. The single step adjacency for Xb11 is to R nodes having an integer column number of the starting node, in this case column 1 for the Xb11 node 102, increased by a value of 1 for single step adjacency in the east direction to R.sub.1,2 node 132 and decreased by the value 1 for single step adjacency in the west direction to R.sub.1,0 node 130. Wraparound is also in effect, in this case, after the increase of a starting column number 3 by 1 for a value of K+1=4, the starting column number 3 wraps around to column 0 and after the decrease of a starting column number 0 by 1 for a value of 1, the starting column number 0 wraps around to column 3.

[0022] The data bus 136 has a connection between Xb11 node and R.sub.1,1 node 131 having the same position in the RC matrix. The data bus 138 has a connection between Xb11 node 102 and the R.sub.1,3 node 133 representing one additional connection in the first direction of communication of two step adjacency. The one additional connection in the first direction of communication of two step adjacency for the Xb11 node 102 may be communication in either the east direction or communication in the west horizontal direction. The east direction of communication of two step adjacency for the Xb11 node 102 is to an R node having an integer column number of the starting node, in this case column 1 for the Xb11 node 102, increased by a value of 2 in the east direction to R.sub.1,3 node 133. With wrap around, an increased column number of 4 wraps around to column 0 and an increased column number of 5 wraps around to column 1. The west direction of communication of two step adjacency for the Xb11 node 102 is to an R node having an integer column number of 1 for the starting node Xb11 node 102, is decreased by a value of 2 in the west direction to a 1 value and is directed to R.sub.1,3 node 133 due to wraparound. With wrap around, a decreased column number of 2 wraps around to column 2.

[0023] The data travels across the data bus 135 and reaches node R10 130 which is configured with four 4to1 multiplexers, such as shown R.sub.r,c 44 crossbar node 177. Each of the four 4to1 multiplexers receives control signals that cause each multiplexer to select none or one of that multiplexer's four input signals to pass to its associated output of the R10 130 44 crossbar. There are three types of R.sub.r,c node to S.sub.r,c node connection paths. The first type of connection path is for data buses 160 and 168 having connections between the R.sub.1,0 node 130 and the S.sub.0,0 node 140 and the S.sub.2,0 node 148 with the same column number in a vertical second direction of communication of single step adjacency between next door adjacent neighbors. The second type of connection path is for data bus 164 which has a connection between R.sub.1,0 node 130 and S.sub.1,0 node 144 having the same position in the RC matrix. The third type of connection path is for data bus 172 which has a connection between the R.sub.1,0 node 130 and the S.sub.3,0 node 152 representing one additional connection in the second direction of communication of two step adjacency. The first direction of communication and the second direction of communication can be reversed, with the first direction of communication being in a vertical North/South direction and the second direction of communication being is a horizontal East/West direction.

[0024] FIG. 2 illustrates an execution array 200 organized in an exemplary 4 row by 4 column arrangement of execution units and local files in a physical layout form with a one to K+1 level adjacency, where K is a positive odd integer, in accordance with an embodiment of the present invention. In FIG. 2, functional units and local storage units are separately coupled across each row with the same row number in a first direction of communication of single step adjacency between next door adjacent neighbors by horizontal row networks 202-205 to R.sub.r,c nodes. The R.sub.r,c nodes are separately coupled across each column with the same column number in a second direction of communication of single step adjacency between next door adjacent neighbors by vertical column networks 207-210 to S.sub.r,c nodes and from there to the functional units and local storage units. For example, in row 0 202 there are a plurality of functional units comprising a load0 (L0)/store0 (S0) unit 220, a multiplication M01 unit 221, an ALU Complex (C) unit 222, and a ALU Bit operation (B) unit 223. Also in row 0 202 and associated with the plurality of functional units are local file (LF) storage units comprising LF00 225, LF01 226, LF02 227, and LF03 228. The other three rows 1-3 203-205 contain a similar organization of functional units and local file units labeled according to their position in the RC array, such as multiplication Mq11 unit 231 and LF11 236. The local files in each row provide a distributed register file for storage of variables as required by a program. Each local file is placed local to its associated functional unit by nature of the timing path to read from and write to the local file as required by a particular implementation. Each local file may also be considered a sub-file portion of a distributed register file supporting computations in row. The 44 execution unit/LF network connecting the functional units and local LFs according to a 1toK+1 adjacency as defined herein contains paths such as shown in FIG. 1.

[0025] In FIG. 2, the four buses 260-263 are provided to transport four 32-bit results generated in each multiplier (Mqxx) unit 221, 231, 241, and 251 over to an associated add and subtract function in the ALU Complex (C) unit 222, 232, 242, and 252 as part of a complex multiplication operation. The four buses 260-263 are able to operate in parallel with the horizontal row networks 202-205 to R.sub.r,c nodes and the vertical column networks 207-210 to S.sub.r,c nodes and from there to the functional units and local storage units of EU network operations. Results of the complex multiplication generated in C02 222, C12 232, C22 242, and C32 252 may be stored locally in associated LF02 227, LF12 237, LF22 247, and LF32 257, respectively.

[0026] FIG. 3 illustrates exemplary specifiable paths in a 44 array of nodes 300 beginning from a source node, Mq11 306 or LF11 323, to nodes in a K+1.sub.row by K+1.sub.column array of nodes (L0/S0)/LF00 301/318 to B33/LF33 316/333 interconnected by a K+1 adjacency network with an increased number of internode data paths, wherein K is an odd integer >1, in accordance with an embodiment of the present invention. Array notation is used with nodes, such as (L0/S0)/LF00=LF.sub.row=0.sub.column=0 301/318. The (L0/S0)/LF00 301/318-B33/LF33 316/333 nodes may be different types of execution unit nodes, such as a load and store unit loadx(Lx)/storex(Sx) or a multiply complex unit (Mqxx) or an ALU Complex (Cxx) unit or an ALU Bit operation (Bxx) unit located with their corresponding local file nodes (LFxx). A row 1 of nodes L1/S1/LF10 305/322, Mq11/LF11 306/323, C12/LF12 307/324, and B13/LF13 308/325 is an exemplary row of nodes in the 44 array of nodes 300. Wiring according to the 1 to K+1 adjacency where K=3 is only shown for the Mq11 306 and LF11 323 nodes for reason of clarity in the drawing. In order to support two operand data paths, cells are defined, wherein each cell comprises an execution node, a local file node, an R node, and an S node for the same row column position, such as exemplary cell 389 comprising Mq11/LF11 306/323, R11 336, S11 345. The cells are configured with expanded capabilities in the R and S nodes. The R nodes, such as R11 336 and shown in Rrc 45 390 and in more detail in Rrc 45 391 comprises an additional 4to1 multiplexer 392. There is also a 44 array of R.sub.r,c 45 crossbar nodes of which nodes R10 335, R11 336, R12 337, and R13 338 are shown. There is further shown a 44 array of S.sub.r,c 52 multiplexer nodes including S00 340 to S33 355 nodes. Each R.sub.r,c node, such as R.sub.r,c 390, is configured with five 4 to 1 multiplexers as shown in R.sub.r,c 391. Each S.sub.r,c node, such as S.sub.r,c 393 is configured with two 5 to 1 multiplexers as shown in S.sub.r,c 52 394. The horizontal row data buses 356-359 and vertical column data buses 360-379 are Bb-bits, for example Bb=16-bits or 32-bits or 64-bits, and the like. Generally, the data bus paths within cells, such as exemplary cell 389, include paths, such as from Mq11/LF11 306/323 over bus 357 to R11 336, R11 336 over a first data bus path 365 and a second data bus path 377 to S11 345, and S11 345 over two data bus paths 381 to Mq11/LF11 306/323, are prioritized for short layouts.

[0027] To illustrate an exemplary data path, the execution unit Mq11 306 generates a result upon executing an instruction which is programmatically directed to use one or more data buses 356-359, such as the data bus 356. The data buses 356-359 comprise data buses 356 and 358 having connections between the Mq11 306 and the R.sub.1,0 node 335 and the R.sub.1,2 node 337 with the same row number in the first direction of communication of single step adjacency between next door adjacent neighbors. The first direction of communication of single step adjacency for the Mq11 306 node is communication in the east and west horizontal direction. The single step adjacency for Mq11 306 is to R nodes having an integer column number of the starting node, in this case column 1 for the Mq11 306, increased by a value of 1 for single step adjacency in the east direction to R.sub.1,2 node 337 and decreased by the value 1 for single step adjacency in the west direction to R.sub.1,0 node 335. Wraparound is also in effect, in this case, after the increase of a starting column number 3 by 1 for a value of K+1=4, the starting column number 3 wraps around to column 0 and after the decrease of a starting column number 0 by 1 for a value of 1, the starting column number 0 wraps around to column 3.

[0028] The data bus 357 has a connection between Mq11 306 and R.sub.1,1 node 336 having the same position in the RC matrix. The data bus 359 has a connection between Mq11 306 and the R.sub.1,3 node 338 representing one additional connection in the first direction of communication of two step adjacency. The one additional connection in the first direction of communication of two step adjacency for the Mq11 306 node is communication in either the east direction or communication in the west horizontal direction. The east direction of communication of two step adjacency for Mq11 306 is to an R node having an integer column number of the starting node, in this case column 1 for the Mq11 306, increased by a value of 2 in the east direction to R.sub.1,3 node 338. With wrap around, an increased column number of 4 wraps around to column 0 and an increased column number of 5 wraps around to column 1. The west direction of communication of two step adjacency for Mq11 306 is to an R node having an integer column number of 1 for the starting node Mq11 306, is decreased by a value of 2 in the west direction to a 1 value and is directed to R.sub.1,3 node 338 due to wraparound. With wrap around, a decreased column number of 2 wraps around to column 2.

[0029] The data travels across the data bus 356 and reaches node R10 335 which is configured with five 4to1 multiplexers, such as shown R.sub.r,c 45 crossbar node 391. Each of the five 4to1 multiplexers receives control signals that cause each multiplexer to select none or one of that multiplexer's four input signals to pass to its associated output of the R10 335 45 crossbar. There are three types of R.sub.r,c node to S.sub.r,c node connection paths. The first type of connection path is for data buses 360 and 368 having connections between the R.sub.1,0 node 335 and the S.sub.0,0 node 340 and the S.sub.2,0 node 348 with the same column number in a second vertical direction of communication of single step adjacency between next door adjacent neighbors. The second type of connection path is for data buses 364 and 376 which have a connection between R.sub.1,0 node 335 and S.sub.1,0 node 344 having the same position in the RC matrix. The third type of connection path is for data bus 372 which has a connection between the R.sub.1,0 node 335 and the S.sub.3,0 node 352 representing one additional connection in the second direction of communication of two step adjacency. The first direction of communication and the second direction of communication can be reversed, with the first direction of communication being in a vertical North/South direction and the second direction of communication being is a horizontal East/West direction.

[0030] FIG. 4 illustrates control system 400 for an R=4C=4 XarMa processor comprising row 0-3 control units 405, 407, 408 with corresponding prolog instruction code (PIC) memories 410, 412, 414 in accordance with an embodiment of the present invention. FIG. 4 illustrates three of the four row pipeline control units that control pipeline stage operations in each row to execute chained execution packets (CEPs), for reasons of clarity of presentation. A CEP is a chain of instructions that generally contain sequential dependencies between one or more instructions in the chain. The CEPs may be fetched in packets or streamed 420, 422, 423 over to row packet registers, such as row 0 packet register 425. Upon receiving a chained execution packet (CEP) which contains control parameters in a header 427, shown as 12345, for a selected execution row, such as row 3, the control parameters are loaded into the control unit 408 for row 3 to coordinate operations on the processor. Instructions are selected from each row packet register for execution and as specified by the control unit and loaded into the associated prolog instruction control (PIC) memory. As shown, the PIC memories 410, 412, 414 load up the instructions during execution of a prolog code sequence and are accessible from the PIC memories for execution in combinations of instructions of up to five instructions at a time, in this example, for independent parallel decode and execution. The 44 execution unit (EU) array 402 can operate all 16 execution units and 16 LFs under a single program counter control 416 in a master mode of operations or the rows of execution units can operate separately under control of four program counters, three of which 416, 418, and 419 are shown in FIG. 4. The program counters (PCs) operate under a program mode control that if in Master Mode (InMM), the Row 0 program counter (R0PC) is the PC for Rows0-3, else, the R0PC is used for R0 only and for rows 1-3 if InMM, the rows 1-3 PCs are not used (NU), else, the R1PC not shown for reasons of clarity of presentation, the R2PC 418 is used for R2 only and the R3PC 419 is used for R3 only.

[0031] FIG. 5 illustrates three RC XarMa processors 500 that are based on the 44 Execution unit (EU) array of FIGS. 1-4 in accordance with embodiments of the invention. The XarMa processor can be scaled both smaller and larger as shown in FIGS. 5A-5C. FIG. 5A illustrates a 14 XarMa processor 502 having a single row of five types of execution units, one load unit (L), a multiply (M), such as the Mq units shown in FIGS. 2-4, an ALU complex (C) unit, an ALU bitop (B) unit, and a store unit (S). By developing an instruction set architecture that allows operands to be specified for delivery to a function unit's operand input instead of specifying a register in a register file, local files with a reduced capacity and reduced number of ports can be used instead of a large capacity multi-ported register file. A load unit (L1) and a store unit (S1) may be combined (LS) with a single two read port 2 write port (2R2W) LF allowing L1 to load directly to an S1 input register or the associated LF or by means of the execution unit network to one or more OIPRs in function execution units. Such a store unit and load unit combination may facilitate directly communicating between processor and memory nodes to reach further network attached elements. For example, the load unit that provides a data value to a function unit or to a local file write port may be located with the store unit that receives the data value from the load unit, a function unit, or from a local file read port. The load unit may access a source data value from a memory and load the fetched data to one or more function units or LFs. The store unit may receive a data value from a function unit or from a LF for storage to memory. FIG. 5B illustrates a 24 XarMa processor 503 having two rows of four types of execution units, LS, M, C, B per row. FIG. 5C illustrates a 44 XarMa processor 504 having four rows of four types of execution units, LS, M, C, B, per row. The data (D) memory banks and instruction memory are configured on a silicon plane separate from the processing logic and execution array plane. While this is a preferred approach, it does not preclude placing the data memory banks and instruction memory on the same silicon with the processing logic and execution array.

[0032] To minimize the storage of temporary variables, an instruction is formatted to specify that a result is to be forwarded to one or more destination instructions in a chain of execution instructions instead of a destination register in a central register file. The forwarding of the result to the destination instruction is decoded by internal logic to be an operand input port register (OIPR) of an associated execution unit thereby eliminating the storage of the temporary result variable in a central register file. For the 14 XarMa processor 502 of FIG. 5A no row specifier is required, but for the 24XarMa processor 503 of FIG. 5B and for the 44 XarMa processor 504 of FIG. 5C or for other configurations such as a 54 or 55 XarMa processor, a row specifier is used in identifying the appropriate execution unit associated with destination instructions. If there are variables in a program that need to be maintained longer than a specified lifetime they may be stored in one or more of the LFs having available storage.