METHOD FOR GENERATING AN OUTPUT SIGNAL HAVING PREDETERMINED JITTER CHARACTERISTICS

Abstract

A method for generating an output signal having predetermined jitter characteristics is disclosed. A first signal is generated via a first signal generator module. A second signal is generated via a second signal generator module. The first signal is pulse position modulated by the second signal, thereby generating a modulated signal having predetermined jitter characteristics. An output signal having predetermined jitter characteristics is generated based on the modulated signal. Moreover, a signal generator for generating an output signal having predetermined jitter characteristics is disclosed.

Claims

1. A method for generating an output signal having predetermined jitter characteristics, comprising the following steps: generating a first signal via a first signal generator; generating a second signal via a second signal generator; pulse-position modulating the first signal by the second signal, thereby generating a modulated signal having predetermined jitter characteristics; and generating an output signal having predetermined jitter characteristics based on the modulated signal.

2. The method of claim 1, wherein the first signal is PAM-n coded.

3. The method of claim 2, wherein the first signal is generated with rising edges having predefined rising slopes between pairs of different signal levels and with falling edges having predefined falling slopes between pairs of different signal levels in order to obtain a predefined duty cycle distortion in the modulated signal.

4. The method of claim 2, wherein the first signal comprises at least one of a predefined symbol sequence and a pseudo-random symbol sequence.

5. The method of claim 2, wherein the pulse position of each signal edge of the first signal is modulated, wherein the modulation is kept constant within each symbol.

6. The method of claim 1, wherein the modulated signal is filtered via a filter in order to generate the output signal, thereby generating predefined inter-symbol interferences in the output signal.

7. The method of claim 6, wherein the filter is a finite impulse response filter.

8. The method of claim 6, wherein the modulated signal is filtered with a filter sampling rate being equal to or larger than a data rate of the first signal.

9. The method of claim 1, wherein the second signal comprises at least one of an periodic signal and white Gaussian noise in order to generate periodic jitter and random jitter in the modulated signal, respectively.

10. The method of claim 8, wherein the periodic signal is generated as a superposition of several sine-shaped signals.

11. The method of claim 1, wherein a perturbation signal being uncorrelated with the first signal, the second signal and the modulated signal is at least one of generated and received, wherein the perturbation signal is added to at least one of the first signal, the second signal and the modulated signal in order to generate other bounded uncorrelated jitter in the output signal.

12. Method according to claim 11, wherein the perturbation signal is multiplied with a predetermined weighting factor before being added to the at least one of the first signal, the second signal and the modulated signal.

13. The method of claim 1, wherein at least the modulated signal is established as a digital signal, and wherein the modulated signal is converted to an analog signal in order to generate the output signal.

14. A signal generator for generating an output signal having predetermined jitter characteristics, comprising a first signal generator circuit, a second signal generator circuit, and a modulation circuit, the first signal generator circuit being configured to generate a first signal and to forward said first signal to the modulation circuit; the second signal generator circuit being configured to generate a second signal and to forward said second signal to the modulation circuit; and the modulation circuit being configured to pulse-position modulate the first signal by the second signal, thereby generating a modulated signal having predetermined jitter characteristics.

15. The signal generator of claim 14, wherein the first signal generator circuit is configured to generate the first signal as a PAM-n coded signal with rising edges having predefined rising slopes between pairs of different signal levels and with falling edges having predefined falling slopes between pairs of different signal levels in order to obtain a predefined duty cycle distortion in the modulated signal.

16. The signal generator of claim 14, wherein the second signal generator circuit is configured to generate the second signal with at least one of a periodic signal and white Gaussian noise.

17. The signal generator of claim 14, comprising a finite impulse response filter module downstream of the modulation circuit.

18. The signal generator of claim 14, comprising a perturbation circuit being configured to at least one of generate and receive a perturbation signal that is uncorrelated with the first signal, the second signal and the modulated signal, wherein the perturbation module is configured to add the weighted perturbation signal to at least one of the first signal, the second signal and the modulated signal.

19. The signal generator of claim 14, wherein at least one of the first signal generator circuit and the second signal generator circuit is established as a digital signal generator.

20. The signal generator of claim 19, comprising a digital-to-analog converter downstream of the modulation circuit.

Description

DESCRIPTION OF THE DRAWINGS

[0044] The foregoing aspects and many of the attendant advantages of the claimed subject matter will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0045] FIG. 1 shows a block diagram of a representative signal generator according to a first embodiment of the disclosure;

[0046] FIG. 2 shows a block diagram of a representative signal generator according to a second embodiment of the disclosure;

[0047] FIG. 3 shows a schematic flow chart of a representative method according to an embodiment of the disclosure;

[0048] FIG. 4 shows a block diagram of a representative modulation module of a signal generator according to FIG. 1 and/or FIG. 2;

[0049] FIG. 5 shows a schematic flow chart of a representative method according to an embodiment of the disclosure, and

[0050] FIG. 6 shows a detailed illustration of Step S3 of the method according to FIG. 5.

DETAILED DESCRIPTION

[0051] The detailed description set forth below in connection with the appended drawings, where like numerals reference like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed.

[0052] FIG. 1 shows a block diagram of a signal generator 10 for generating an output signal x.sub.out(t) having predetermined jitter characteristics. Such output signals having predetermined jitter characteristics are usually employed for testing certain properties of a device under test, for example for jitter tolerance testing of the device under test. Thereby and in the following, the term predetermined jitter characteristics is understood to include both the total jitter contained in the respective signal and the individual jitter components contained in the respective signal. The modulated signal and the output signal each contain periodic jitter (PJ), random jitter (RJ), data dependent jitter (DDJ) and/or other bounded uncorrelated jitter (OBUJ). In some embodiments, the modulated signal and the output signal may each contain inter-symbol interferences (ISI) and/or duty cycle distortion (DCD).

[0053] The signal generator 10 comprises a first signal generator circuit or module 12, a second signal generator circuit or module 14, a modulation circuit or module 16, a filter 18, a perturbation circuit or module 20 and a memory 21.

[0054] The first signal generator module 12 and the second signal generator module 14 are both connected to the modulation module 16 upstream of the modulation module 16. Accordingly, signals can be sent from both the first signal generator module 12 and the second signal generator module 14 to the modulation module 16.

[0055] The filter 18 is connected to the modulation module 16 downstream of the modulation module 16 such that signals sent by the modulation module 16 are received by the filter 18.

[0056] The perturbation module 20 is connected to the filter 18 downstream of the filter 18 and comprises a perturbation signal generator 22, a weighting circuit or unit 24 and an adding circuit or unit 26.

[0057] However, the perturbation module 20 may also be connected to the both the modulation module 16 and the filter 18 downstream of the modulation module 16 and upstream of the filter 18.

[0058] Alternatively, the perturbation module 20 may be connected to the modulation module 16, the first signal generator module 12 or the second signal generator module 14 upstream of the modulation module 16. Further, the perturbation module 20 may be connected downstream of the first signal generator module 12 or the second signal generator module 14, respectively.

[0059] FIG. 2 shows another embodiment of the signal generator 10. This embodiment differs from the embodiment of FIG. 1 in that the modulation module 16 is part of the first signal generator module 12 rather than being established separately from the first signal generator module 12. The remaining parts of the signal generator 10, however, remain unchanged compared to the embodiment of FIG. 1.

[0060] The signal generator 10 according to the embodiments of FIGS. 1 and 2 is configured to perform a method for generating an output signal having predetermined jitter characteristics, which method is described in the following with reference to FIG. 3.

[0061] A first signal x.sub.1(t) is generated via the first signal generator (step S1). The shape of the first signal x.sub.1(t) is schematically depicted in FIG. 4.

[0062] The first signal x.sub.1(t) is a digital PAM-n coded signal, wherein n is an integer bigger than one. Thus, the first signal x.sub.1(t) comprises a sequence of symbols (bits in the PAM-2 coded case) that are generated via the first signal generator module 12.

[0063] The sequence comprised in the first signal x.sub.1(t) is at least one of predefined and pseudo-random, and is either generated by the first signal generator module 12 itself or loaded into the first signal generator module 12 from the memory 21.

[0064] Each symbol takes one of n possible values, wherein signal edges are located between adjoining symbols having different values. The signal edges connect the individual symbols in a continuous and approximately linear manner, i.e. the signal edges each have a certain slope.

[0065] The first signal x.sub.1(t) is generated with rising edges having predefined rising slopes between pairs of different signal levels and with falling edges having predefined falling slopes between pairs of different signal levels such that the first signal x.sub.1(t) has a predefined duty cycle distortion.

[0066] In total, there are n*(n1) possible transitions between the different signal levels and, in general, the slopes or more precisely the absolute values of the slopes corresponding to each of the transitions may are different from each other. However, at least some of the slopes may be pairwise equal to each other.

[0067] In some embodiments, all slopes may be equal to each other, such that the first signal x.sub.1(t) has no duty cycle distortion in this case.

[0068] Thereby and in the following, it is to be understood that the slope of a rising edge between two signal levels and the corresponding slope of the falling edge between the same two signal levels are considered to be equal if their absolute values are equal and are considered different from each other if their absolute values are different from each other.

[0069] In the case of a PAM-2 coded signal, there are two different levels low and high and thus two possible transitions, namely low to high and high to low. Therefore, in order to introduce a duty cycle distortion in this case, the slope of the signal edge corresponding to the transition low to high is chosen to be different from the slope of the signal edge corresponding to the transition high to low. Thus, in the case of a PAM-2 coded signal, the first signal has a trapezoidal shape. Accordingly, the first signal generator module 12 is established as a trapezoid generator.

[0070] Moreover, a digital second signal x.sub.2(t) is generated via the second signal generator (step S2). The second signal x.sub.2(t) comprises at least one of a periodic signal and white Gaussian noise.

[0071] In general, the periodic signal has an arbitrary periodic shape, which shape may be set by a user of the signal generator 10 or may be loaded from the memory 21.

[0072] In the simplest case, the periodic signal portion of the second signal x.sub.2(t) is established as a sine-shaped signal with a certain amplitude and phase.

[0073] In general, the periodic signal portion of the second signal x.sub.2(t) is generated as a superposition of several sine-shaped signals. Thus, the second signal x.sub.2(t) has the following general form:

[00001]$x_2\left(t\right)=\underset{k=0}{\overset{N}{.Math.}}.Math.A_k.Math.\sin \left({}_k.Math.t+{}_k\right)+x_{G.Math.N}.$

[0074] Therein, A.sub.k are the amplitudes of the individual sine-shaped periodic signal portions, .sub.k are their frequencies and .sub.k their phases, thus the sum in the equation above essentially represents a Fourier series of a periodic signal to be obtained. x.sub.GN represents the white Gaussian noise portion of the second signal x.sub.2(t), and is usually normal-distributed with a certain expected value and a certain variance.

[0075] Now, the first signal x.sub.1(t) and the second signal x.sub.2(t) are forwarded to the modulation module 16 and the first signal x.sub.1(t) is phase position modulated by the second signal x.sub.2(t), thereby generating a modulated signal x.sub.mod(t) (step S3). More precisely, the first signal x.sub.1(t) is the carrier signal of the modulation and the second signal x.sub.2(t) is the modulating signal of the modulation.

[0076] As is illustrated in FIG. 5 for the case of a PAM-2 coded signal, the position of each signal edge of the first signal x.sub.1(t) is shifted based on the value of the second signal x.sub.2(t) at a certain time, which certain time is equal to the temporal position of the preceding signal edge of the first signal x.sub.1(t), as indicated by the arrows in FIG. 5. Thus, the temporal position t.sub.i of the i-th signal edge is shifted by a time span .sub.t, as a result of the pulse position modulation.

[0077] The modulation is kept constant within each symbol. In other words, only the temporal position of each of the signal edges is adjusted while no changes are made within the symbol itself. In some embodiments, no changes are made to the slopes of the signal edges. Put differently, the temporal length of a symbol is only modified by parallel shifting of the signal edges defining the respective symbol and not by contracting or stretching areas within the symbol itself.

[0078] Step S3 is illustrated in more detail in FIG. 6. The modulation module 16 samples the first signal x.sub.1(t) having a data rate f.sub.d with a sampling frequency f.sub.s. Moreover, the modulation module 16 also samples the modulation signal via a first sample and hold circuit or member S&H1.

[0079] The modulation module 16 now detects signal edges in the first signal x.sub.1(t) and controls the first sample and hold member S&H1 based on whether a signal edge is detected or not (edge detect).

[0080] If no signal edge is detected, only the first signal x.sub.1(t) is forwarded to a second sample and hold circuit or member S&H2. Thus, if no signal edge is detected, the corresponding portion of the first signal x.sub.1(t) remains unchanged.

[0081] If a signal edge is detected, the first signal x.sub.1(t) is forwarded to the second sample and hold member S&H2. Moreover, the current value of the second signal x.sub.2(t) is scaled based on at least one jitter factor J and forwarded to the second sample and hold member S&H2. The at least one jitter factor J may be preset by a user and/or may be loaded from the memory 21.

[0082] More precisely, phases .sub.PJ.sub.k(i) and .sub.RJ(i) are determined for the periodic signal components and the white Gaussian noise component of the second signal x.sub.2(t) and scaled by respective jitter factors, such that an overall phase shift .sub.tot is determined to be

[00002]${}_{t.Math.o.Math.t}\left(i\right)=\underset{k=0}{\overset{N}{.Math.}}.Math..Math.J_{{\mathrm{PJ}}_k}.Math.{}_{{\mathrm{PJ}}_k}\left(i\right)+.Math.J_{\mathrm{RJ}}.Math.{}_{\mathrm{RJ}}\left(i\right).$

[0083] This overall phase shift .sub.tot is then added to the phase of the corresponding signal edge number i, such that the temporal position of the signal edge number i is shifted when output by the second sample and hold member S&H2.

[0084] As a result of the steps Si to S3, the modulated signal x.sub.mod(t) contains the duty cycle distortion inherited from the first signal x.sub.1(t), periodic jitter due to the periodic signal portions of the second signal x.sub.2(t) and random jitter due to the white Gaussian noise portion of the second signal x.sub.2(t).

[0085] The modulated signal x.sub.mod(t) is then forwarded to the filter 18 and filtered via the filter 18, thereby generating a filtered modulated signal x.sub.mod,filt(t) having predefined inter-symbol interferences.

[0086] In general, defining parameters of the filter 18 are chosen such that the filter 18 reflects the characteristics of a transmission channel that is to be modelled.

[0087] The filter 18 may be established as a finite impulse response filter. For example, the filter 18 is established as a low pass filter. Such a low-pass filter reflects the transmission characteristics of a finite-bandwidth medium such as a cable and therefore reproduces the inter-symbol interferences caused by the finite-bandwidth medium.

[0088] In some embodiments, a filter sampling rate may be chosen to be equal to or larger than a data rate of the first signal x.sub.1(t).

[0089] Moreover, a perturbation signal x.sub.per(t) is generated and/or received by the perturbation signal generator 22, weighted with a weighting factor g by the weighting unit 24 and added to the filtered modulated signal X.sub.mod,filt(t) by the adding unit 26, thereby generating the output signal x.sub.out(t) (step S5).

[0090] Thereby, the perturbation signal x.sub.per(t) and the weighting factor are chosen such that a predetermined other bounded uncorrelated jitter is added to the filtered modulated signal X.sub.mod,filt(t) and thus comprised in the output signal x.sub.out(t).

[0091] Accordingly, the form of the perturbation signal x.sub.per(t) and/or the weighting factor may be adjustable by a user and/or loaded from the memory 21.

[0092] Finally, the output signal x.sub.out(t) the output signal x.sub.out(t) may be converted to an analog signal via a digital-to-analog converter if an analog signal is required for testing the particular device under test (step S6).

[0093] As a result of the method described above, the output signal x.sub.out(t) comprises predetermined jitter characteristics. More precisely, the output signal x.sub.out(t) comprises a predetermined duty cycle distortion, a predetermined periodic jitter, a predetermined random jitter, a predetermined other bounded uncorrelated jitter and predetermined inter-symbol interferences.

[0094] Certain embodiments disclosed herein utilize circuitry (e.g., one or more circuits) in order to implement protocols, methodologies or technologies disclosed herein, operably couple two or more components, generate information, process information, analyze information, generate signals, encode/decode signals, convert signals, transmit and/or receive signals, control other devices, etc. Circuitry of any type can be used.

[0095] In an embodiment, circuitry includes, among other things, one or more computing devices such as a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system on a chip (SoC), or the like, or any combinations thereof, and can include discrete digital or analog circuit elements or electronics, or combinations thereof. In an embodiment, circuitry includes hardware circuit implementations (e.g., implementations in analog circuitry, implementations in digital circuitry, and the like, and combinations thereof).

[0096] In an embodiment, circuitry includes combinations of circuits and computer program products having software or firmware instructions stored on one or more computer readable memories that work together to cause a device to perform one or more protocols, methodologies or technologies described herein. In an embodiment, circuitry includes circuits, such as, for example, microprocessors or portions of microprocessor, that require software, firmware, and the like for operation. In an embodiment, circuitry includes an implementation comprising one or more processors or portions thereof and accompanying software, firmware, hardware, and the like.

[0097] The present application may reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the present application. Also in this regard, the present application may use the term plurality to reference a quantity or number. In this regard, the term plurality is meant to be any number that is more than one, for example, two, three, four, five, etc. The terms about, approximately, near, etc., mean plus or minus 5% of the stated value. For the purposes of the present disclosure, the phrase at least one of A and B is equivalent to A and/or B or vice versa, namely A alone, B alone or A and B.. Similarly, the phrase at least one of A, B, and C, for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when greater than three elements are listed.

[0098] The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, aspects of the present disclosure which are intended to be protected are not to be construed as limited to the particular embodiments disclosed. Further, the embodiments described herein are to be regarded as illustrative rather than restrictive. It will be appreciated that variations and changes may be made by others, and equivalents employed, without departing from the spirit of the present disclosure. Accordingly, it is expressly intended that all such variations, changes, and equivalents fall within the spirit and scope of the present disclosure, as claimed.