Correction of mismatch errors in a multi-bit delta-sigma modulator

Abstract

A method for calibrating a multi-bit Delta-Sigma modulator is disclosed herein. The method includes at least one main multi-bit digital-analogue converter in a return loop for generating a return signal subtracted from an input of the modulator. The main converter includes a plurality of elementary source cells at least some of which, referred to as active cells, are associated with the various input bits of the converter for generating the return signal. The output level of these active source cells is adjustable under the action of a matching signal that comes from a calibration circuit receiving an output signal from the modulator at its input. The calibration circuit includes a generator of a calibration sequence.

Claims

1. A method for calibrating a multi-bit Delta-Sigma modulator comprising at least one main multi-bit digital-analogue converter (11) in a return loop for generating a modulator return signal (I.sub.dac) to be subtracted from an input of the modulator, the main converter (11) comprising a plurality of elementary source cells, at least some of which, referred to as active cells (12.sub.1, . . . , 12.sub.n), are associated with a plurality of input bits (D.sub.0, . . . , D.sub.n1) of the converter coupled to an output signal (M.sub.out) of the modulator for generating the modulator return signal, the output level of the active source cells being adjustable under the action of a matching signal (m), the matching signal coming from a calibration circuit (2) that receives the output signal (M.sub.out) from the modulator at its input, the calibration circuit (2) comprising a generator of a calibration sequence (pr), method in which, given a reference cell, a cell to be calibrated (12.sub.j) is selected from amongst the active source cells, the selected source cell and the reference cell being controlled by complementary signals based on the calibration sequence (pr) in such a manner as to inject into the modulator return signal a calibration signal whose amplitude decreases with the matching between the selected source cell and the reference cell thus controlled, and in which the matching signal (m) sent to the selected source cell to be calibrated is generated by processing of the output signal (M.sub.out) of the modulator and of the calibration sequence (pr) in such a manner as to make the amplitude of the injected calibration signal converge towards a predefined limit value.

2. The method according to claim 1, the predefined value being non-zero.

3. The method according to claim 1, the reference cell being dedicated to the calibration of all the active source cells and not being used for generating the modulator return signal from one of the input bits (D.sub.0, . . . , D.sub.n1) coupled to the output (M.sub.out) of the modulator.

4. The method according to claim 1, the converter comprising an assembly of source cells formed of an additional source cell and of as many active source cells as input bits of the converter coupled to the output (M.sub.out) of the modulator, the additional source cell receiving either the calibration sequence (pr) or the complementary calibration sequence (pr) and the reference cell receiving the complementary sequence from the one received by the additional source.

5. The method according to claim 1, wherein a spectral power distribution of the calibration sequence (pr) is centred on a frequency outside of a band of the modulator's input.

6. The method according to claim 1, the calibration sequence (pr) being one of periodic, random or pseudo-random.

7. The method according to claim 1, the active elementary source cells being current generators.

8. The method according to claim 1, the active source cells each comprising an addressable memory element (15) for storing a value of the matching signal (m).

9. A multi-bit Delta-Sigma modulator comprising: a main return loop multi-bit digital-analogue converter (11) for generating a modulator return signal to be subtracted from an input of the modulator, the main converter comprising a plurality of elementary source cells at least some of which, referred to as active cells (12.sub.1, . . . , 12.sub.n), are associated with a plurality of input bits (D.sub.0, . . . , D.sub.n1) of the converter coupled to an output signal (M.sub.out) of the modulator, for generating the modulator return signal, the output level of each active source cell being adjustable under the action of a matching signal (m); a control circuit (13) for selecting a cell to be calibrated (12.sub.j) from amongst the active source cells, the selected source cell and a reference cell (12.sub.n+2) each being controllable by complementary signals based on a calibration sequence (pr) in such a manner as to inject into the modulator return signal a calibration signal whose amplitude decreases with the matching between the selected source cell (12.sub.j) and the reference cell (12.sub.n+2); and a calibration circuit (2) for generating the matching signal (m) to be sent to the selected source cell to be calibrated, the calibration circuit operable to receive the output signal (M.sub.out) from the modulator at its input, the calibration circuit (2) comprising a generator for generating the calibration sequence (pr), wherein the calibration circuit is operable to generate the calibration sequence (pr) and to generate the matching signal (m) by processing of the output signal (M.sub.out) of the modulator in such a manner as to make the amplitude of the calibration signal converge towards a predefined limit value.

10. The modulator (1) according to claim 9, the reference cell dedicated to the calibration and other than the active source cells.

11. The modulator (1) according to claim 9, the converter (11) comprising an assembly of source cells comprising an additional source cell and as many source cells (12.sub.1, . . . , 12.sub.n) as there are input bits of the converter coupled to the output (M.sub.out) of the modulator, wherein the additional source cell is operable to receive either the calibration sequence (pr) or the complementary calibration sequence (pr) and wherein the reference cell is operable to receive the complementary sequence from the one received by the additional source cell.

12. The modulator (1) according to claim 9, the calibration sequence (pr) being chosen so that a spectral distribution of its power is centred on a frequency outside of the band of the modulator's input.

13. The modulator (1) according to claim 9, the active source cells each comprising an addressable memory (15) for storing a value of the matching signal (m), the matching signal (m) being transmitted in digital form to the source cells.

14. The modulator (1) according to claim 9, the active source cells comprising a local digital-analogue converter (16).

15. An adjustable source cell (12.sub.k) of a main multi-bit digital-analogue converter (11) of a main return loop of a Delta-Sigma modulator (1) according to claim 9, the cell comprising a local digital-analogue converter (16) comprising: an inverter (24, 25) having as input one of the input bits (D.sub.0, . . . , D.sub.3) of the main converter (11), and being powerable by high (V+) and low (V) voltages; a high adjustment set (21) comprising transistors, installed between a high reference voltage (V.sub.reft) and the high voltage power supply (V+) of the inverter, the transistors being controllably by a matching signal (m); a low adjustment set (22), comprising transistors, installed between a low reference voltage (V.sub.reft) and the low power supply voltage (V) of the inverter, the transistors being controllable by the matching signal (m); the high and low adjustment sets being implemented in such a manner that, depending on the transistor that is activated, the output high and low level of the inverter is different.

Description

(1) The invention will be better understood upon reading the description that follows of non-limiting exemplary embodiments of the latter, and upon examining the appended drawings, in which:

(2) FIG. 1 shows schematically one example of a Delta-Sigma modulator according to the invention;

(3) FIG. 2 illustrates an example of selection of the active source cell to be calibrated;

(4) FIG. 3 shows schematically an exemplary structure of an active current source cell;

(5) FIG. 4 shows one example of an implementation in CMOS of a local digital-analogue converter of an active current source cell;

(6) FIG. 5 illustrates schematically one example of an adjustment set comprising several parallel branches;

(7) FIG. 6 is a diagram illustrating the generation of the calibration sequence in the case where the latter is pseudo-random; and

(8) FIG. 7 shows the timing diagrams of the signals in FIG. 6.

(9) FIG. 1 shows, in a schematic and partial manner, a multi-bit Delta-Sigma modulator 1 according to the invention. In this example, for the sake of simplicity of the diagram, the modulator has a resolution of 4 thermometric bits. However, in practice, the modulator may have a higher resolution.

(10) The modulator 1 comprises a sub-modulator 3, a calibration circuit 2 and a control circuit 13 for selecting the cell to be calibrated. The sub-modulator 3 has as inputs the input voltage V.sub.in to be digitized, a calibration sequence pr and a matching signal m, the calibration sequence pr, the matching signal m coming from the calibration circuit 2 and a cell selection signal C.sub.select from the control circuit 13. The sub-modulator 3 has as output a digital signal M.sub.out in the form of a digital code composed of n bits (D.sub.0, . . . , D.sub.n1, i.e. D.sub.0 to D.sub.3 for n=4) resulting from the digitization. This signal M.sub.out is injected into the input of the calibration circuit 2 and fed back to the sub-modulator 3.

(11) The sub-modulator 3 comprises, in this example, a transconductance 8 transforming the input voltage V.sub.in into a current I.sub.in. The sub-modulator 3 comprises, in this example, a low-pass filter 9 followed by an analogue-digital converter 10, for example of the Flash type, and a main return loop digital-analogue converter 11 supplying a current I.sub.dac. The filter 9 integrates the difference (I.sub.inI.sub.dac) which is subsequently converted into a digital code (D.sub.0, . . . , D.sub.n1). This code is thermometric.

(12) The main return loop digital-analogue converter 11 comprises n+2 elementary source cells 12.sub.k, 1<=k<=n+2, n and k being positive integer numbers. In the example illustrated, these source cells correspond to current sources, but voltage sources may be used.

(13) Each active cell 12.sub.k, for 1<=k<=n+1, comprises an adjustable current source that may be adjusted by the matching signal m. Electronic switches 18.sub.k are associated with the cells and controlled by respective bits D.sub.0, . . . , D.sub.n1 of the signal M.sub.out. In this example, there are four active sources (12.sub.1, . . . , 12.sub.4) corresponding to the four bits of the code at the output (D.sub.0, . . . , D.sub.3), and two additional sources. These additional sources are a reference source 12.sub.n+2 (noting that n=4 in this embodiment, hence reference source 12.sub.n+2 may also be referred to as reference source 12.sub.6) and an additional source, allowing four sources to be used for generating the useful signal, chosen from amongst the (4+1) sources, while the unused source 12.sub.j from amongst these (4+1) sources for generating the useful signal is calibrated. This source 12.sub.j is referred to as the source under calibration.

(14) The current at the output I.sub.cali of the cell under calibration 12.sub.j is equal to I.sub.ref.Math.(1+), I.sub.ref being the current of the reference source 12.sub.n+2 and being the relative value of deviation with respect to the reference source. The switch 18.sub.j of the cell under calibration 12.sub.j is controlled by the calibration sequence pr, which is, for example, pseudo-random.

(15) The reference source 12.sub.n+2 comprises a fixed current source and the corresponding switch is controlled by the complementary signal of pr (i.e. pr).

(16) The correction of the mismatch errors is carried out by injecting into the return signal I.sub.dac a calibration signal equal to pr.Math.(I.sub.caliI.sub.ref). The amplitude of this signal decreases with the matching between the cell under calibration 12.sub.j and the reference cell 12.sub.n+2.

(17) For the processing of the useful signal, n sources are active and controlled by the signal D.sub.0, . . . , D.sub.n1.

(18) It can be seen in FIG. 1 that the cell under calibration 12.sub.j receives the signal pr, whereas the cell 12.sub.n+1 receives the signal corresponding to the bit D.sub.n1 (i.e. D.sub.3 with N=4 in the exemplary embodiment).

(19) FIG. 2 is a table where l corresponds to the position of the cell and c corresponds to a phase of operation of the digital-analogue converter. It is assumed that the reference cell controlled by the complementary signal of pr (pr) is fixed and remains at the sixth position (l=6). In the first phase (c=1), the third cell (l=3) is that under calibration, which corresponds to FIG. 1. The cell occupying the fourth position (l=4), controlled by D.sub.2 at c=1, is subsequently selected for calibration. Therefore, in the following phase, the signal pr is directed towards this cell, whereas the bit D.sub.2 replaces pr which was at the third position at c=1. In the following, the fifth cell (l=5) is selected for calibration at c=3, pr is then directed towards this cell, and the bit D.sub.3 is directed towards the cell that was under calibration in the preceding cycle.

(20) The modulator thus comprises a control circuit 13, shown schematically in FIG. 1, for selecting the cell to be calibrated from amongst the active source cells.

(21) The choice of the cell under calibration may be random or sequential.

(22) The calibration circuit 2 comprises a generator 4 of the calibration sequence pr. This signal pr and the output digital code M.sub.out undergo a bandpass filtering, then a decimation, by means of a decimator bandpass filter 5, prior to being correlated by a multiplier 6. The result K of the multiplication is equal to:
M.sub.out.Math.pr=I.sub.in.Math.pr+I.sub.ref.Math.,
given that M.sub.out=I.sub.inI.sub.dac=I.sub.inpr.Math.I.sub.ref+I.sub.cali.Math.pr=I.sub.in+I.sub.ref.Math..Math.pr and that pr=+/1 for a pseudo-random signal. Therefore, K.fwdarw.I.sub.ref.Math. when t.fwdarw..

(23) K is subsequently integrated by an integrator 7 in order to yield the matching signal m.

(24) The pseudo-random signal pr may be obtained from a pseudo-random binary sequence PRBS generator and from the clock signal clk of the modulator.

(25) In order for the spectral power density of the pseudo-random signal pr to be centred on a frequency outside of the band of the useful signal of the modulator, the pseudo-random signal may be obtained by dividing the clock signal clk of the modulator either by N1 or by N2 depending on the value of the pseudo-random binary sequence PRBS, N1 and N2 being, in the current example, different positive integer numbers. Thus, the noise density on the signal pr is centred on f.sub.clk*(N1+N2)/(2*N1*N2), f.sub.clk being the clock frequency of the modulator.

(26) For example, in FIG. 6, N1=3 and N2=5. The diagram in FIG. 6 is based on a fractional divider, such as those used in fractional phase-locked loop circuits for example. The corresponding timing diagrams are given in FIG. 7, where it can be seen that, when PRBS=0, the signal pr is obtained from the signal clk divided by 3, and when PRBS=1, the signal pr is obtained from the signal clk divided by 5.

(27) An active elementary source cell 12.sub.k is shown in FIG. 3. It comprises an addressable memory 15 for storing a value of the matching signal m. The signal s at the output of the memory 15 acts on a variable current source 19. This variable current source comprises a local digital-analogue converter.

(28) FIG. 4 shows schematically one exemplary embodiment of this digital-analogue converter local 16. The latter comprises an CMOS inverter composed of a PMOS transistor 24 and of a NMOS transistor 25. Their gates are controlled by an input signal D.sub.i and their drains are connected to a terminal Q of a resistor R.sub.dac of the local converter. It is also envisaged that the converter may be controlled by the calibration sequence pr or the complimentary calibration sequence (pr).

(29) A high adjustment set 21, composed for example of PMOS transistors in parallel with one another, is connected in series with the PMOS transistor 24. This transistor set 21 is connected to the source of the transistor 24, defining the high power supply voltage V+ of the inverter, and is furthermore connected to the high reference voltage such as a positive power supply voltage V.sub.DD. The gates of the transistors of the transistor set 21 receive a first control signal ctrlp [0:m1] which is for example a thermometric word of length m, m being the number of transistors in the transistor set 21. Each of the bits of ctrlp controls a gate of a transistor of the transistor set 21. The signal ctrlp is a code obtained at the output of a decoder 27 receiving at its input the matching signal m.

(30) In a symmetrical manner, a low adjustment set 22 of NMOS transistors in parallel with one another is connected in series with the NMOS transistor 25. This transistor set 22 is connected to the source of the transistor 25, defining the low power supply voltage V of the inverter, and are also connected to a low reference voltage such as the negative power supply voltage V.sub.ss. The gates of the transistors of the transistor set 22 receive a second control signal ctrln [0:m1] which is for example a thermometric word of length m, m being the number of transistors in the transistor set 22. Each of the bits of ctrln controls a gate of a transistor 22. The signal ctrln is the complement of the signal ctrlp.

(31) The resistances R.sub.ds_ON of the transistors of these two sets of transistors 21 and 22 are adjusted by the matching signal m in order to compensate the mismatch errors between the resistors R.sub.dac of the local digital-analogue converters 16.

(32) When the transistors, which may be identical, of an adjustment set are in parallel with one another, the equivalent resistance is the resistance R.sub.ds_ON of a transistor divided by the number of transistors activated by the control signal.

(33) The high adjustment set 21 or low set 22 may comprise several parallel branches of transistors connected together as illustrated in FIG. 5.

(34) The topology of the set is for example of the segmented DAC type, with most significant bits t1-t3 being thermometric bits and with least significant bits b0-b1 being binary bits, in a R-2R structure, as illustrated.

(35) Accordingly, there has been described a method for calibrating a multi-bit Delta-Sigma modulator comprising at least one main multi-bit digital-analogue converter in the return loop for generating a return signal subtracted from the input of the modulator, the main converter comprising a plurality of elementary source cells at least some of which, referred to as active cells, are associated with the various input bits of the converter for generating the return signal, the output level of these active source cells being adjustable under the action of a matching signal, the matching signal coming from a calibration circuit receiving an output signal from the modulator at its input, this calibration circuit comprising a generator of a calibration sequence.

(36) Aspects of the invention are set out in the following series of numbered clauses.

(37) 1. Method for calibrating a multi-bit Delta-Sigma modulator comprising at least one main multi-bit digital-analogue converter in the return loop (11) for generating a return signal (I.sub.dac) subtracted from the input of the modulator, the main converter (11) comprising a plurality of elementary source cells at least some of which, referred to as active cells (12.sub.1, . . . , 12.sub.n), are associated with the various input bits (D.sub.0, . . . , D.sub.n1) of the converter for generating the return signal, the output level of these active source cells being adjustable under the action of a matching signal (m), the matching signal coming from a calibration circuit (2) receiving an output signal from the modulator at its input (M.sub.out), this calibration circuit (2) comprising a generator of a calibration sequence (pr), method in which, given a reference cell, a cell to be calibrated (12.sub.j) is selected from amongst the active source cells, the selected source cell and the reference cell being controlled from the calibration sequence (pr) in such a manner as to inject into the return signal a calibration signal whose amplitude decreases with the matching between the selected source cell and the reference cell thus controlled, and in which the matching signal (m) sent to the active cell in the process of being calibrated is generated by processing of the output signal of the modulator (M.sub.out) and of the calibration sequence (pr) in such a manner as to make the amplitude of the injected calibration signal converge towards a predefined value.

(38) 2. Method according to the preceding clause, the predefined value being zero.

(39) 3. Method according to Clause 1, the predefined value being non-zero.

(40) 4. Method according to any one of the preceding clauses, being applied sequentially to each active elementary cell.

(41) 5. Method according to any one of Clauses 1 to 3, being applied randomly to each active elementary cell.

(42) 6. Method according to any one of the preceding clauses, the reference cell (12.sub.n+2) being chosen from amongst one of the active source cells.

(43) 7. Method according to any one of Clauses 1 to 5, the reference cell (12.sub.n+2) being dedicated to the calibration of all the active source cells and not being used for generating the return signal from one of the input bits (D.sub.0, . . . , D.sub.n1).

(44) 8. Method according to any one of the preceding clauses, the converter comprising an assembly of source cells formed of an additional source cell (12.sub.n+1) and of as many active source cells as input bits of the converter, the input bit of the active source cell selected for the calibration being directed towards this additional cell, during the calibration of the selected active source cell.

(45) 9. Method according to the preceding clause, the additional source cell being chosen randomly or sequentially from amongst the said assembly of source cells.

(46) 10. Method according to any one of the preceding clauses, the calibration sequence (pr) being chosen so that the spectral power distribution is mainly situated outside of the bandwidth of the modulator, being preferably centred around at least one predefined frequency.

(47) 11. Method according to any one of the preceding clauses, the calibration sequence (pr) being periodic.

(48) 12. Method according to any one of Clauses 1 to 10, the calibration sequence (pr) being pseudo-random.

(49) 13. Method according to Clause 12, the calibration sequence (pr) being generated from a pseudo-random binary sequence (PRBS).

(50) 14. Method according to Clause 13, the modulator comprising a clock generating a clock signal (clk), the pseudo-random signal (pr) being obtained by dividing the clock signal (clk) of the modulator either by N1 or by N2 depending on the value of the pseudo-random binary sequence (PRBS), N1 and N2 being two different integer numbers.

(51) 15. Method according to any one of the preceding clauses, the matching signal being generated from a correlation between the calibration sequence (pr) and the output signal of the modulator (M.sub.out).

(52) 16. Method according to the preceding clause, the quantity coming from the correlation being integrated in order to generate the matching signal (m).

(53) 17. Method according to either of Clauses 15 and 16, at least one of the calibration sequence (pr) and of the output signal of the modulator (M.sub.out) undergoing a filtering, preferably bandpass, then a decimation, prior to the correlation.

(54) 18. Method according to Clause 17, the filtering being carried out by a bandpass filter centred on f.sub.clk*(N1+N2)/(2*N1*N2), f.sub.clk being the clock frequency of the modulator.

(55) 19. Method according to any one of the preceding clauses, the active elementary source cells being current sources.

(56) 20. Method according to any one of the preceding clauses, the active elementary source cells each comprising an addressable memory element (15) for storing a value of the matching signal (m).

(57) 21. Method according to any one of the preceding clauses, the calibration being carried out as a background task during the processing of the useful signal at the input of the modulator.

(58) 22. Method according to any one of the preceding clauses, the matching signal (m) being transmitted in digital form to the active elementary source cells.

(59) 23. Method according to any one of the preceding clauses, the number (n) of active elementary source cells used to generate the return signal (I.sub.dac) from the input bits (D.sub.0, . . . , D.sub.n1) of the main converter being greater than or equal to 2, preferably in the range between 2 and 64, notably equal to 32.

(60) 24. Multi-bit Delta-Sigma modulator (1) comprising: a main return loop multi-bit digital-analogue converter (11) for generating a return signal subtracted from the input of the modulator, the main converter comprising a plurality of elementary source cells at least some of which, referred to as active cells (12.sub.1, . . . , 12.sub.n), are associated with the various input bits (D.sub.0, . . . , D.sub.n1) of the converter for generating the return signal, the output level of each active source cell being adjustable under the action of a matching signal (m), a control circuit (13) for selecting a cell to be calibrated (12.sub.j) from amongst the active source cells, the selected source cell and a reference source (12.sub.n+2) being controlled from the calibration sequence (pr) in such a manner as to inject into the return signal a calibration signal whose amplitude decreases with the matching between the selected active cell (12.sub.j) and the reference source cell (12.sub.n+2), a calibration circuit (2) for generating the matching signal (m) sent to the active cell in the process of being calibrated, receiving an output signal from the modulator at its input (M.sub.out), this calibration circuit (2) comprising a generator of a calibration sequence (pr), the matching signal (m) sent to the active cell in the process of being calibrated being generated by processing of the output signal (M.sub.out) of the modulator and of the calibration sequence (pr) in such a manner as to make the amplitude of the calibration signal converge towards a predefined value, preferably zero.

(61) 25. Modulator (1) according to Clause 24, the control circuit (13) being configured for applying the calibration sequence sequentially or randomly to each active source cell.

(62) 26. Modulator (1) according to either of Clauses 24 and 25, the converter (11) comprising a reference cell (12.sub.n+2) dedicated to the calibration and other than the active source cells.

(63) 27. Modulator (1) according to any one of Clauses 24 to 26, the converter (11) comprising an assembly of source cells comprising an additional source cell (12.sub.n+1) and as many source cells (12.sub.1, . . . , 12.sub.n) as there are input bits of the converter, in such a manner that this additional source cell (12.sub.n+1) can receive the input bit of the active source cell selected for calibration, during the calibration of the latter.

(64) 28. Modulator (1) according to any one of Clauses 24 to 27, the calibration sequence (pr) being chosen so that the spectral distribution of its power is mainly situated outside of the bandwidth of the modulator, being preferably centred around at least one predefined frequency.

(65) 29. Modulator (1) according to any one of Clauses 24 to 28, the calibration sequence (pr) being pseudo-random, generated from a pseudo-random binary sequence (PRBS), the modulator comprising a clock generating a clock signal (clk), the pseudo-random signal (pr) being preferably obtained by dividing the clock signal (clk) of the modulator either by N1 or by N2 depending on the value of the pseudo-random binary sequence (PRBS), N1 and N2 being two different numbers, the matching signal being preferably generated from a correlation between the calibration sequence (pr) and the output signal of the modulator (M.sub.out), the quantity coming from the correlation being integrated in order to generate the matching signal (m), at least one of the calibration sequence (pr) and of the output signal of the modulator (M.sub.out) undergoing a filtering, preferably bandpass, then a decimation, prior to the correlation, the filtering preferably being carried out by a bandpass filter centred on f.sub.clk*(N1+N2)/(2*N1*N2), f.sub.clk being the clock frequency of the modulator.

(66) 30. Modulator (1) according to any one of Clauses 24 to 29, the active source cells each comprising an addressable memory (15) for storing a value of the matching signal (m), the matching signal (m) being transmitted in digital form to the source cells.

(67) 31. Modulator (1) according to any one of Clauses 24 to 30, the control circuit being configured for carrying out the calibration as a background task during the processing of the useful signal at the input of the modulator.

(68) 32. Modulator (1) according to any one of Clauses 24 to 31, the active source cells comprising a local digital-analogue converter (16).

(69) 33. Adjustable source cell (12.sub.k) of a main multi-bit digital-analogue converter (11) of a main return loop of a Delta-Sigma modulator (1), notably a modulator according to any one of Clauses 24 to 32, the cell comprising a local digital-analogue converter (16) comprising: an inverter (24, 25) having as input one of the input bits (D.sub.0, . . . , D.sub.3) of the main converter (11), and being powered by high (V+) and low (V) voltages; a high adjustment set (21) comprising transistors, installed between a high reference voltage (V.sub.reft) and the high voltage power supply (V+) of the inverter, the transistors being controlled by a matching signal (m); a low adjustment set (22), comprising transistors, installed between a low reference voltage (V.sub.refb) and the low power supply voltage (V) of the inverter, the transistors being controlled by the matching signal (m);
the high and low adjustment sets being implemented in such a manner that, depending on the transistor that is controlled, the output high and low level of the inverter is different.

(70) 34. Cell according to the preceding clause, the high adjustment set (21) comprising an assembly of PMOS transistors, notably configured in parallel with one another, their gates receiving a first control signal (ctrlp) depending on the matching signal (m), these transistors being installed between the high reference voltage (V.sub.reft) and the high voltage power supply (V+) of the inverter.

(71) 35. Cell according to either of the two preceding clauses, the low adjustment set (22) comprising an assembly of NMOS transistors, notably configured in parallel with one another, their gates receiving a second control signal (ctrln) depending on the matching signal (m), these transistors being installed between the low reference voltage (V.sub.refb) and the low power supply voltage (V) of the inverter.

(72) The invention is not limited to the examples described hereinabove. In the figures, for the sake of simplicity, only a structure with a single output of the modulator (known as a single-ended structure) has been shown, but a differential (or double-ended) structure of the modulator is also perfectly possible.