Cost-efficient high power PECVD deposition for solar cells

Abstract

A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.

Claims

1. A plasma enhanced chemical vapor deposition (PECVD) system, comprising: a vacuum chamber having a platform configured to receive a substrate; and a common electrode disposed in the vacuum chamber and positioned over the platform, the common electrode having a first end connected to a first power generator configured to perform a high power PECVD flash deposition for depositing a first portion of a layer on the substrate, and a second end connected to a second power generator configured to perform a low power PECVD deposition for depositing a second portion of the layer on the substrate, the first power generator and the second power generator sharing usage of the common electrode in the vacuum chamber, and being controllable to form a p-type layer using high power PECVD and using low power PECVD for other layers within the vacuum chamber.

2. The system as recited in claim 1, wherein the buffer layer is a single material layer of silicon germanium that is in direct contact with both the transparent electrode and the p-type layer of the photovoltaic stack.

3. The system as recited in claim 1, wherein the high power PECVD flash deposition forms a first portion of the germanium containing material layers having an increasing crystallinity with increasing depth; and the low power PECVD deposition forms a second portion of the germanium containing material layers that is amorphous to provide the single material layer for the buffer layer having a varying crystal structure having said first portion with said increasing crystallinity with said increasing depth and said second portion being said amorphous.

4. The system as recited in claim 3, wherein the increasing crystallinity is in a direction towards the p-type layer of hydrogenated silicon carbide to provide for alignment of a conduction band of the buffer layer and the p-type layer of hydrogenated silicon carbide to reduce a Schottky barrier between the buffer layer and the p-type layer of hydrogenated silicon carbide.

5. The system as recited in claim 1, wherein the high power PECVD flash deposition forms a thickness of less than about 5 nm in less than about 5 seconds.

6. The system as recited in claim 1, wherein the first power generator provides a plasma at a power of between about 100 mW/cm.sup.2 and about 100 W/cm.sup.2.

7. The system as recited in claim 1, wherein first power generator is configured to pulse to provide a plurality of the high power PECVD flash deposition cycles to form multiple layers of high power flash deposited material.

8. The system as recited in claim 7, wherein the high power PECVD flash deposition cycles include different pulse durations.

9. The system as recited in claim 1, wherein the vacuum chamber includes a support structure for holding or conveying the substrate.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:

(2) FIG. 1 is a cross-sectional view of a photovoltaic device with a buffer layer formed in accordance with the present principles;

(3) FIG. 2 depicts a graph showing current density (mA/cm.sup.2) versus voltage (V) for three different deposition powers for forming a buffer layer to demonstrate an effect of deposition power on the buffer layer;

(4) FIG. 3 depicts a graph showing open circuit voltage (V.sub.OC) versus p-layer deposition power (W) to demonstrate an effect of deposition power on the p-layer;

(5) FIG. 4 depicts a graph showing band gap energy (eV) versus deposition power (W) to demonstrate an effect of p-type layer deposition power on the intrinsic layer;

(6) FIG. 5 is a block diagram showing a plasma enhanced chemical vapor deposition (PECVD) system for providing a dual power deposition process in accordance with the present principles; and

(7) FIG. 6 is a block/flow diagram showing methods for fabricating a photovoltaic device using a dual power deposition in accordance with illustrative embodiments.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(8) In accordance with the present principles, methods and devices are presented that provide improved efficiency based upon deposition parameters of layers formed for semiconductor devices and in particular for photovoltaic cells. Layers for semiconductor devices are often deposited using low deposition energies. Low deposition energies are favored by manufacturing since the low energy permits high quality a-Si:H layer deposition and less energy results in lower process costs. Designers also prefer low deposition energies since the low energies create plasma with less energy bombardment on a surface resulting in less damage to existing structures on semiconductor devices. In thin film Si solar cell applications, high deposition energies are desired for depositing a p+ layer since the higher energies increase the likelihood that a microcrystalline phase will form. The microcrystalline phase can reduce barrier heights between the p+ layer and an electrode (e.g., formed from a transparent conductive oxide (TCO)).

(9) For example, photovoltaic stacks and, in particular, p-i-n structures (a p-type layer, an intrinsic layer, an n-type layer) or n-i-p structures (an n-type layer, an intrinsic layer, a p-type layer) include layers where a band offset at an interface can be improved based upon the crystallinity of the layersthe higher power, the higher the crystallinity. Higher crystallinity permits for tunneling current through the barrier. In useful examples, such improvements can be gained at an interface between a transparent conductive oxide (TCO) to the p+ layer. A band offset at the TCO/p+ layer is unavoidable since all developed TCO films are n-type. In particularly useful embodiments, photovoltaic devices are constructed using materials and processes that adjust deposition power for the formation of layers, e.g., a buffer layer at the TCO/p+ interface. To provide improved efficiency, the manner in which the buffer layer and other layers are formed may be addressed in accordance with the present principles. In one example, a buffer layer is deposited between the TCO and the p.sup.+ layer of the device using a deposition process designed to improve device efficiency. In particularly useful embodiments, low power deposition may be employed to deposit a bulk portion of the layer followed by a high power flash deposition to finish the layer.

(10) Methods and devices provide a deposition process and power settings that improve device efficiency. In one embodiment, a buffer layer may include Ge or Ge.sub.xSi.sub.1-x, which is disposed between the TCO layer and the p+ layer of the solar cell. The Ge is deposited using power deposition settings that are adjusted to reduce band offsets between materials and to increase crystallinity of the Ge or GeSi buffer layer. The Ge is preferably deposited using a high power deposition process to affect the properties of the buffer layer to increase efficiency of the device. The high power deposition process will be implemented as a flash process lasting less than about 5 seconds. In another embodiment, the p+ layer or p-type layer is deposited or processed to reduce band offsets by a flash high deposition power process. This may be performed in addition to or instead of the buffer layer processing. Other layers in the structures may also be processed using the high deposition power flash.

(11) In accordance with the present principles, layers are deposited by high power plasma deposition, and, in particular, a high power plasma enhanced chemical vapor deposition (PECVD) process. In one embodiment, plasma is provided by a dual power system. A low power system supplies plasma for a regular deposition while a second power supply provides a high power short duration flash deposition. In another embodiment, a high power supply system is locally installed to deposit layers, e.g., provide a scanning deposition of p-i-n (n-i-p) layers on a photovoltaic device.

(12) It is to be understood that the present invention will be described in terms of a given illustrative architecture having substrates and photovoltaic stacks; however, other architectures, structures, substrates, materials and process features and steps may be varied within the scope of the present invention.

(13) It will also be understood that when an element such as a layer, region or substrate is referred to as being on or over another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

(14) A design for a photovoltaic device may be created for integrated circuit integration or may be combined with components on a printed circuit board. The circuit or board may be embodied in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or photovoltaic devices, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet), directly or indirectly.

(15) Methods as described herein may be used in the fabrication of photovoltaic devices and/or integrated circuit chips with photovoltaic devices. The resulting devices/chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged devices/chips), as a bare die, or in a packaged form. In the latter case the device/chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the devices/chips are then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys, energy collectors, solar devices and other applications including computer products or devices having a display, a keyboard or other input device, and a central processor.

(16) It should be further understood that material compounds will be described in terms of listed elements, e.g., SiC, SiGe, etc. These compounds include different proportions of the elements within the compound, e.g., Si.sub.xC.sub.y where x/y1, etc. In addition, other elements may be included in the compound and still function in accordance with the present principles.

(17) Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, an illustrative photovoltaic structure 100 is illustratively depicted in accordance with one embodiment. The photovoltaic structure 100 may be employed in solar cells, light sensors or other photovoltaic applications. Structure 100 includes a substrate 102 that permits a high transmittance of light. The substrate 102 may include a transparent material, such as glass, a polymer, etc. or combinations thereof.

(18) A first electrode 104 includes a transparent conductive material. Electrode 104 may include a transparent conductive oxide (TCO), such as, e.g., a fluorine-doped tin oxide (SnO.sub.2:F, or FTO), doped zinc oxide (e.g., ZnO:Al), indium tin oxide (ITO) or other suitable materials. For the present example, a doped zinc oxide is illustratively employed for electrode 104. The TCO 104 permits light to pass through to an active light-absorbing material beneath and allows conduction to transport photo-generated charge carriers away from that light-absorbing material. The TCO 104 may be deposited by a chemical vapor deposition (CVD) process, a low pressure CVD (LPCVD) process or a plasma-enhanced (PE-CVD) process.

(19) A buffer layer 105 may be employed. Buffer layer 105 may include germanium or silicon germanium and may include a p-type dopant such as B, Ga, In or combinations thereof. In one embodiment, the buffer layer 105 includes a silicon-germanium alloy layer including germanium, silicon, optionally a p-type dopant, and hydrogen. In this embodiment, the atomic concentration of germanium may be greater than 50%. Depending on the work-function of TCO 104, Si content in Ge can be varied. The buffer layer 105 has a greater atomic concentration of germanium than a p-doped layer 106 formed on the buffer layer 105.

(20) The buffer layer 105 can be amorphous, microcrystalline, or single crystalline. The buffer layer 105 may include a hydrogenated material. For example, if the buffer layer 105 includes a hydrogenated amorphous silicon germanium alloy, a hydrogenated microcrystalline silicon-germanium alloy, a hydrogenated amorphous germanium, or a hydrogenated microcrystalline germanium, the hydrogenation of the material of the buffer layer 105 decreases localized electronic states and increases the conductivity of the buffer layer 105. A hydrogenated amorphous germanium may be formed using GeH.sub.4 plasma.

(21) The buffer layer 105 can be formed, for example, by plasma enhanced chemical vapor deposition (PECVD). In accordance with the present principles, the buffer layer 105 is formed with a dual process including a low power deposition and a high power flash deposition. In one embodiment, the low power deposition may include a power of between about 1.0 mW/cm.sup.2 and about 100 mW/cm.sup.2, and the high power flash deposition may include a power of between about 100 mW/cm.sup.2 and about 100 W/cm.sup.2. The deposition temperature for either process may be maintained at between about 200 degrees C. to about 300 degrees C., although other temperatures may be employed. Either process may be performed first depending on the desired crystallinity of the completed layer. The high power deposition includes a power higher than the low power deposition to provide thicknesses of the same layer that have different levels or crystallinity. This better transitions band gap energies between layers.

(22) The thickness of the buffer layer 105 can be from about 1 nm to about 30 nm, although lesser and greater thicknesses can also be employed. All the barriers, e.g., between TCO 102 and the buffer layer 105 and between the buffer layer 105 and the p+ layer 106, exist at valence band locations. One purpose of having the buffer layer 105 is to make a mid-gap bridge between TCO 102 and p+ layer 106.

(23) In the case of FIG. 1, the low power deposition is performed first followed by the high power flash to increase crystallinity towards the p+ layer 106. In this case, the buffer layer 105 includes an interfacial layer 116 with higher crystallinity (microcrystalline) than the remaining portions of the buffer layer 105. The buffer layer 105, with the interface layer 116, better aligns the Fermi level between the TCO layer 104 (e.g., ZnO) and the p-type layer 106 (e.g., a-SiC:H). The Fermi level of the TCO layer 104 in the case of ZnO is about 4.5 eV. Without the buffer layer 105, a larger Schottky barrier exists between the TCO 104 and the p-type layer 106. With the buffer layer 105, the Fermi levels of TCO 104 and the buffer layer 105 are well-aligned reducing the barrier offset. A conduction band between the buffer layer 105 and the p-type layer 106 is also well-aligned. In this way, the Schottky barrier is reduced or eliminated resulting in better conduction and more efficient device operation by permitting higher open circuit voltage (V.sub.OC) without sacrificing fill factor (FF). In particularly useful embodiments, it is believed that increased crystallinity of the buffer layer 105 and in particular the interface layer 116 correlates with increased open circuit voltage (V.sub.OC) while at least maintaining fill factor (FF).

(24) The p-doped layer 106 may include an amorphous, microcrystalline, or single-crystalline p-doped silicon-containing material. The p-doped layer 106 can be a p-doped silicon layer including: silicon and at least one p-type dopant and optionally hydrogen; a p-doped silicon-carbon alloy layer including: silicon, carbon, at least one p-type dopant and optionally hydrogen. Other materials may also be employed.

(25) In some cases, the p-doped layer 106 may include a hydrogenated amorphous, microcrystalline, or single-crystalline p-doped silicon-containing material. A hydrogenated p-doped silicon-containing material can be deposited in a process chamber having a silicon-containing reactant gas as a carrier gas. To facilitate incorporation of hydrogen in the hydrogenated p-doped silicon-containing material, a carrier gas including hydrogen can be employed. Hydrogen atoms in the hydrogen gas within the carrier gas are incorporated into the deposited material to form an amorphous or microcrystalline hydrogenated p-doped silicon-containing material of the p-doped layer 106.

(26) In one embodiment, p-doped or p-type layer 106 includes boron as a dopant, although other p-type dopants may be employed. Layer 106 may be deposited using diborane gas, trimethylborane or other gases. The p-type layer 106 may have a thickness of between about 5-30 nm. In particularly useful embodiments, layer 106 includes amorphous SiC or Si. The processing of the p-type layer 106 also can affect the efficiency of the device. For example, the deposition parameters for depositing the p-type layer 106 may be selected to increase the effects of the buffer layer 105.

(27) The p-type layer 106 can be formed, for example, by plasma enhanced chemical vapor deposition (PECVD). As with the buffer layer 105 or any other layer in the device 100, the two-part deposition process may be employed that includes a low power deposition and a high power flash deposition. As before, the low power deposition may include a power of between about 1.0 and about 100 mW/cm.sup.2, and the high power flash deposition may include a power of between about 100 mW/cm.sup.2 and about 100 W/cm.sup.2. The deposition temperature for either process may be maintained at between about 200 degrees C. to about 300 degrees C., although other temperatures may be employed. Either process may be performed first depending on the desired crystallinity of the completed layer.

(28) The thickness of the p-type layer 106 can be from about 5 nm to about 30 nm, although lesser and greater thicknesses can also be employed. For the smaller thicknesses, the high power flash deposition may be employed alone. For example, layer thicknesses of about 5 nm may be formed by the high power flash deposition.

(29) In one embodiment, the high power flash is performed first followed by the low power deposition. In this case, the p-type layer 106 includes an interfacial layer 118 with higher crystallinity than the remaining portions of the p-type layer 106. The p-type layer 106 (e.g., a-SiC:H) is better aligned in terms of the Fermi level with the TCO layer 104 (e.g., ZnO) or the buffer layer 105 (e.g., Ge) (if employed). More efficient device operation is provided by permitting higher open circuit voltage (V.sub.OC) without sacrificing fill factor (FF). In particularly useful embodiments, it is believed that increased crystallinity of the p-type layer 106 results in enhanced doping efficiency and in particular the interface layer 118 correlates with increased V.sub.OC while at least maintaining FF.

(30) Processing continues with the formation of an intrinsic layer 110 formed on layer 106 from compatible materials. Intrinsic layer 110 may be undoped and may include an amorphous silicon material, e.g., hydrogenated amorphous Si (a-Si:H). The intrinsic layer 110 may include a thickness of between about 100-300 nm, although other thicknesses are contemplated. The intrinsic layer 110 may be formed using a chemical vapor deposition (CVD) process, or a plasma-enhanced (PE-CVD), e.g., from silane gas and hydrogen gas.

(31) A doped layer 112 (e.g., an n-type layer) is formed on the intrinsic layer 110. Layer 112 may include an n-type Si containing layer, e.g., hydrogenated microcrystalline (c-Si:H), single crystalline (Si) or an amorphous (a-Si) layer. Layer 112 may be deposited by a chemical vapor deposition (CVD) process, or a plasma-enhanced (PE-CVD). The n-type layer 112 may have a thickness of between about 5-20 nm. A back reflector and/or bottom electrode 114 may be formed using a reflective metal, such as Ag, Al, etc. and may be combined with ZnO back reflectors. A suitable metal deposition process may be employed, e.g., physical or chemical vapor deposition, sputtering, evaporation, electro or electroless plating, etc. It should be understood that other material selections, layers, structures, etc. may be employed in device 100 including additional back reflectors, etc. or instead of back reflectors: tandem cells, etc.

(32) It should be understood that the structures depicted in FIG. 1 are illustrative and that other structures may be employed, e.g., the p-i-n stack can be reversed (n-i-p). In addition, one or more layers of the device 100 may be formed with the two-part deposition process. In addition, the high power deposition process may be employed alone to form small thickness layers.

(33) In accordance with another embodiment, the high power flash deposition may be employed in multiple pulses to form layers. For example, if the high power flash deposition provides a 3 nm thickness for the buffer layer 105, the high power flash deposition may be repeated four times (four pulses) to achieve a 12 nm buffer layer 105. The high power flash deposited buffer layer 105 would include a higher crystallinity, which results in improved efficiency of operation. The high power flash deposited buffer layer 105 would be more cost effective since the flash pulses would take only a few seconds, and low temperature is maintained therefore maintaining thermal budget and reducing damage to existing layers/structures.

(34) Referring to FIG. 2, a graph shows general effects of different deposition powers for a buffer layer (e.g., buffer layer 105) in a p-i-n stack photovoltaic device. The graph shows three plots corresponding to different deposition powers for a buffer layer formed from a-GeSi:H. The graph plots current density (J) in mA/cm.sup.2 versus voltage (V) in volts for three devices. The deposition powers include the following: 0.15 W/cm.sup.2 for plot 202, 0.6 W/cm.sup.2 for plot 204 and 1.6 W/cm.sup.2 for plot 206. A systematic degradation of FF occurs as the deposition power is reduced. For a power of 0.15 W/cm.sup.2 (plot 202), FF was 53%. For a power of 0.6 W/cm.sup.2 (plot 204), FF was 66%. For a power of 1.6 W/cm.sup.2 (plot 206), FF was 69%. Advantageously, V.sub.OC remains high with higher FF.

(35) The plots 202, 204 and 206 correspond to devices that were processed in the same way but for the deposition power of the buffer layer. The devices included p-i-n (p-type, intrinsic, n-type) layers deposited at 250 degrees C. and the p type layer (106) was deposited with a power of 0.6 W/cm.sup.2 for these devices. In accordance with these findings, a high power deposition seems to result in improved device efficiency. This may be as a result of increased crystallinity and therefore conductivity of the deposited material and/or other factors. However, high power is expensive, costs thermal budget and may have a destructive effect on adjacent structures. In addition for large area deposition in manufacturing environments, high deposition power is not favored. Large area refers to large scale devices having an illustrative size on the order of feet or meters, e.g., 1.5 meters by 0.6 meters. Such devices may include solar panels. Low power is favored in such environments.

(36) In accordance with the present principles, a high power flash deposition with a low power bulk deposition provides improved device efficiency while permitting a reduction in overall deposition power. In some embodiments, the high power flash deposition may be employed alone to form a layer depending on a thickness needed and a deposition rate provided by the process. In other embodiments, the high power flash deposition may be repeatedly performed in a pulsing fashion to accumulate the needed thickness. The pulses may include a same pulse rate or the pulse rate may be altered for subsequent pulses. The high power flash deposition is preferably a plasma enhanced CVD process and may include a duration (pulse duration) of between 1 millisec to about 5 seconds. Other times are also contemplated and may depend on the application, materials, etc.

(37) Referring to FIG. 3, experimental results for devices fabricated using different deposition powers are depicted to show a correlation between deposition power and open circuit voltage (V.sub.OC) (in millivolts). V.sub.OC is graphed versus deposition power (W) for a p-type layer in p-i-n photovoltaic devices. The p-type layer included a p-doped a-Si layer. In accordance with the graph, V.sub.OC increased with deposition power.

(38) It should be understood that the deposition power may be increased to levels higher than those depicted herein (e.g., deposition powers of 900 W or greater may be provided) and that comparable improvements may be obtained but may have some limitations. In addition, other parameters may be adjusted as well including duration of a treatment, temperature, etc. It should be understood that the high power deposition may improve other adjacent layers as well including but not limited to the intrinsic layer, which will be illustratively described with respect to FIG. 4, and even the n-type layer.

(39) Referring to FIG. 4, experimental results for devices fabricated using different deposition powers are depicted to show a correlation between deposition power of the p-type layer and band gap energy (eV) of the intrinsic layer (e.g., 110, FIG. 1). Band gap is graphed versus deposition power (W) for a-Si p-i-n photovoltaic devices. In accordance with the graph, band gap increased with deposition power until it reached 2.00-2-01 eV.

(40) From FIGS. 2, 3 and 4, higher power deposition provides improvements in efficiency. However, this needs to be balanced against some drawbacks including lifetime efficiency, cost, ease of manufacturing, etc. In accordance with the present principles, a high power flash process is performed in a PECVD chamber to form one or more of a buffer layer and a p-type layer. In particularly useful embodiments, a largest efficiency gain comes from high power flash processing of the p+ type layer and the use of high power flash processing of a buffer layer. In one particularly useful embodiment, a high power flash process includes a power greater than about 100 mW/cm.sup.2 for less than about 5 seconds, and more preferably less than one second. The temperature may be about 200-300 degrees C.

(41) Referring to FIG. 5, a dual power system 300 is shown in accordance with one illustrative embodiment. The system 300 includes a low power generator 302, which is employed most of time, and a high power generator 304, which is used for a few seconds or less to provide a high power flash process, as described. The generators 302 and 304 include power supplies capable of generating sufficient potential between an electrode 320 and a ground 322. The system 300 may include a vacuum chamber 324 for carrying out a PECVD processes. As is known, plasma includes charged particles/ions accelerated in an electric field (being set by the power settings) to bombard and therefore be deposited on a surface of a device, wafer or panel 310. The system 300 may include a support platform or carrier 306 for supporting the device, wafer or panel 310 on which deposition and other processes are carried out. Platform 306 may include a conveyor or other mechanical device for a manufacturing line. This may be particularly useful for scanning deposition processes, e.g., for fabricating solar panels. The platform 306 also includes the ground 322 to provide a ground potential to the electric field accelerating the plasma particles. Two different electrical feedthroughs 326 and 328, respectively, connect the high power generator 304 and the low power generator 302 to the electrode 320.

(42) In one embodiment, the high power generator 304 is retrofit into an existing chamber to provide the dual power system 300. In other embodiments, a same generator may be employed to perform both the high and low power deposition processes. In still other embodiments, only the high power generator 304 is provided.

(43) The high power generator 304 is configured to provide a higher conductivity to a layer by providing increased crystallinity to an otherwise amorphous or microcrystalline deposition. In one embodiment, the flash deposition may form a thickness of less than about 5 nm in less than about 5 seconds. Other thicknesses and times are also contemplated. The high power generator 304 provides a plasma at a power of between about 100 mW/cm.sup.2 and about 100 W/cm.sup.2. Higher powers are also contemplated.

(44) In other embodiments, the power generator 304 is configured to pulse to provide a plurality of the high power flash deposition cycles to form multiple layers of high power flash deposited material. For example, 5 cycles may produce a 10 nm layer where each cycle provides 2 nm. In other embodiments, the high power flash deposition cycles may include different pulse durations. For example, a 10 nm layer may be deposited in 3 cycles: a 5 nm deposition cycle, a 3 nm deposition cycle and a 1 nm deposition cycle. Other combinations of thickness and flash durations are also contemplated.

(45) Referring to FIG. 6, methods for forming a photovoltaic device are illustratively shown. It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in FIG. 6. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagram and/or flowchart illustration, and combinations of blocks in the block diagram and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

(46) In block 402, a substrate is provided. A transparent electrode may be formed on a transparent substrate. The transparent electrode may include a transparent conductive oxide or the like. The transparent substrate may include glass, a polymer, monocrystalline silicon, etc. In block 404, one or more layers of a photovoltaic stack are deposited on the substrate. The depositing step of the one or more layers includes performing a high power flash deposition for depositing a first portion of the layer in block 410. It should be understood that the one or more layers may include deposited amorphous or microcrystalline layers with increased crystallinity and conductivity as a result of the high power flash deposition.

(47) In block 420, a low power deposition is performed for depositing a second portion of the layer. The low power deposition may be eliminated if the high power deposition provides sufficient thickness for the layer. The one or more layers processed using the dual power process may include a p-type layer and a buffer layer, although the process may be employed for other layers as well. In a particularly useful embodiment, the buffer layer and the p-type layer are formed by the dual power process.

(48) In block 412, the high power flash deposition may include depositing a thickness of less than about 5 nm in less than about 5 seconds. Other parameters are also contemplated in accordance with the present principles. In block 416, the high power flash deposition may include a plasma enhanced chemical vapor deposition at a power of between about 100 mW/cm.sup.2 and about 100 W/cm.sup.2. In block 418, the high power flash deposition may include pulsing the high power flash deposition process to form multiple thicknesses of high power flash deposited material in a same layer. Pulses may include different pulse durations. The deposited thickness may increase in crystallinity with depth. This may be performed by increasing the power with each subsequent pulse or gradually increasing the power over time.

(49) The high power flash deposition may be performed before or after the low power deposition. The p-type layer, the intrinsic layer and the n-type layer may be formed at a temperature of about 250 degrees Celsius. Other temperatures may also be employed.

(50) In block 422, processing continues to complete the photovoltaic device. For example, a back reflector or back reflectors may be formed. Other structures and layers are also envisioned. In one embodiment, the p-type layer includes a form of silicon (e.g., a-Si, a-Si:H, a-SiC, a-SiC:H, crystalline forms of Si or SiC, etc.). The intrinsic layer may include a-Si, a-Si:H, or crystalline forms of Si, etc.). The n-type layer may include an n-doped form of a-Si, a-Si:H, or crystalline forms of Si, etc.).

(51) Having described preferred embodiments for cost-efficient high power PECVD deposition for solar cells (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.