Chip testing method and an apparatus for testing of a plurality of field emission light sources

Abstract

The present invention generally relates to a method for operating a plurality of field emission light sources, specifically for performing a testing procedure in relation to a plurality of field emission light sources manufactured in a chip based fashion. The invention also relates to a corresponding testing system.

Claims

1. A method of controlling a plurality of field emission light sources, each field emission light source comprising a cathode side including an electrical cathode connection and an oppositely arranged anode side including an electrical anode connection, wherein the method comprises: arranging the plurality of field emission light sources in vicinity of each other in a matrix formation having m rows and n columns, where the electrical cathode connections for the field emission light sources are electrically connected to each other in line with the columns, and the electrical anode connections for the field emission light sources are electrically connected to each other in line with the rows, providing an electrical interface point for each of the m rows and the n columns, applying a control signal to at least one of the electrical interface points at each of the m rows and to at least one of the electrical interface points at each of the n columns, thereby energizing at least one of the field emission light sources for emitting light, acquiring, using a light sensor, an indication of a photonic output from the at least one energized field emission light source, determining an operational status for the at least one energized field emission light source based on the indication of the photonic output from the at least one energized field emission light source, and separating the field emission light sources from each other, wherein the separation is based on the operational status for the at least one energized field emission light source.

2. The method according to claim 1, wherein the separation is controlled further based on the photonic output of field emission light sources.

3. The method according to claim 1, further comprising: subsequently applying the control signal to at least another one of the electrical interface points at the m rows or the n columns, thereby energizing at least another one of the field emission light sources for emitting light.

4. The method according to claim 1, further comprising: storing the indication of the photonic output emitted by the at least one energized field emission light source.

5. The method according to claim 1, wherein the anode side is shared between at least two of the plurality of field emission light sources.

6. The method according to claim 1, wherein determining of the operational status for the at least one energized field emission light source comprises determining at least one of an operating voltage, an operating current, and operating power or an operational point for the at least one energized field emission light source.

7. The method according to claim 6, wherein the determined operational status is used for sorting of the plurality of field emission light sources into different functionality bins.

8. The method according to claim 1, wherein a predetermined number of field emission light sources are energized at the same time.

9. The method according to claim 8, wherein a single field emission light sources is energized at a time.

10. The method according to claim 8, wherein a group of field emission light sources are energized at a time.

11. The method according to claim 1, wherein the control signal is a high voltage control signal having a voltage level above 1 kV.

12. The method according to claim 1, wherein the electrical interface point is arranged at an end portion of each of the m rows and the n columns.

13. The method according to claim 12, further comprising arranging a first electrical contact to the electrical interface points of the rows and a second electrical contact to the electrical interface points of the columns.

14. The method according to claim 1, wherein the anode side is individual for each of the plurality of field emission light sources.

15. A system adapted for controlling a plurality of field emission light sources, wherein: each field emission light source comprising a cathode side including an electrical cathode connection and an oppositely arranged anode side including an electrical anode connection, the plurality of field emission light sources being arranged in vicinity of each other in a matrix formation having m rows and n columns, where the electrical cathode connections for the field emission light sources are electrically connected to each other in line with the columns, and the electrical anode connections for the field emission light sources are electrically connected to each other in line with the rows, and at least one electrical interface point being arranged at each of the m rows and at least one interface point being arranged at each of the n columns, wherein the system comprises: a first electrical contact adapted to be connected the at least one interface point of the m rows and a second electrical contact to be connected to the at least one test point of the n columns, and means for applying a control signal to the first and the second electrical contacts, thereby energizing at least one of the field emission light sources for emitting light, wherein the system is further adapted to: acquire, using a light sensor comprised with the system, an indication of a photonic output from the at least one energized field emission light source, determine an operational status for the at least one energized field emission light source, and separate the field emission light sources from each other, wherein the separation is based on the operational status for the at least one energized field emission light source.

16. The system according to claim 15, wherein when the plurality of field emission light sources are arranged in the matrix formation, to select a separation between the plurality of field emission light sources is below 0.3 mm, preferably around 0.2 mm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The various aspects of the invention, including its particular features and advantages, will be readily understood from the following detailed description and the accompanying drawings, in which:

(2) FIG. 1 illustrates a typical process flow for wafer test, sawing /dicing, encapsulation and final test;

(3) FIGS. 2A and 2B provide exemplary descriptions of an arrangement for wafer test according to prior-art;

(4) FIGS. 3A and 3B illustrates exemplary descriptions of an arrangement for wafer test according to the invention, and

(5) FIG. 4 shows a flow chart of a method according to an embodiment of the invention.

DETAILED DESCRIPTION

(6) The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which currently preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided for thoroughness and completeness, and fully convey the scope of the invention to the skilled addressee. Like reference characters refer to like elements throughout.

(7) Referring now to the drawings and to FIG. 1 in particular, there is illustrated a typical process flow 100 for wafer test, sawing/dicing, encapsulation and final test in order to put the invention into context. Once the manufacturing of a wafer containing multiple field emission light sources (FELs) has been completed, the wafer is to be tested, for example by a test system 102, and the parametric data such as for example operating voltage, current, power and optical output is measured, recorded and stored, as e.g. text data 104. Faulty and devices non-compliant to the desired specification are identified. After this the wafer is subdivided in a subdivision process 106, so that the devices are now single parts, or in case that a larger array shall be used, the subdivision takes this into account by the aid of the test data 104. The good FELs identified by the testing system 102 are picked out for further processing and the faulty parts are scrapped or sent to analysis. The good parts are then encapsulated, usually in a plastic package and electrical leads are attached so that the end user may contact the device electrically. Finally, the parts are tested again in a finalization process 108; the parametric data are again recorded, stored and possibly compared with the original test data 104, where-after the FELs are ready for packaging and shipment.

(8) In FIG. 2A there is illustrated a typical testing system 200 according to the prior-art. A plurality of FELs 202 is manufactured on a wafer 204. For simplicity and clarity, a small wafer containing only 16 individual FELs are shown. Much larger substrates, containing several hundreds of devices are entirely possible, as well as preferred. Wafer testing is done by contacting probes 206 and 208 to the electrical connection points, or pads 210 and 212, respectively. The pad 210 is in the illustration in electrical connection with a single cathode of the FEL 200 (as will be further elaborated in relation to FIG. 2B). In a corresponding manner, the pad 212 is in electrical connection with a single anode of the FEL 202. Accordingly, a pair of pads 210, 212, must be contacted with the pair of probes 206, 208 for testing a single FEL 202. Thus, the pads must be moved between testing a first to testing a second FEL 202, such as out of the 16 FEL 202 shown in FIG. 2A. As can be seen in FIG. 2A, it may be preferable to shift of at least one of the pads by 45 degrees in order to allow more space and easier probing. The probes 206, 208 are connected to an electrical control unit 214, typically energizing the FEL 202, measuring the parametric data and subsequently storing the data.

(9) In FIG. 2B a typical partial view of a FEL device wafer is shown according to the prior-art. The individual FELs 202 are built on the substrate wafer 204 by attaching or forming a cathode 216, a spacer 218 and a top glass disk 220 also being the carrier of a field emission anode 222. A detailed view of the cathode 216 is provided, typically comprising a plurality of nanostructures, for example formed from ZnO or carbon nanotubes.

(10) The glass disc 220 must overlap the spacer 218, typically by 1 mm in order to allow for accumulated alignment uncertainties as well as making it possible to achieve an electrical contact. As mentioned above, conducting paths are provided from the anode 222 to the pad 210 and from the cathode 216 to the pad 212. In this specific example, an electrical via connection 228 is used to make the connection to the top pad 210 at the top glass disk 220 so that it may easily be probed. The electrical via connection 228 is preferably made outside the cavity area (i.e. outside of the spacer 218) as well as the seal area to minimize unwanted leakage of gaseous species. The distance between the individual FELs 202 must be large enough to allow for final separation. In a typical prior-art embodiment, 0.2 mm has been used. It is possible that this distance must be larger since, in this arrangement in inaccuracy of placement of the top glass discs must be accounted for. Such an uncertainty will only elevate the benefits of the proposed invention.

(11) FIG. 3A illustrates exemplary descriptions of an arrangement for wafer test according to the present invention. In FIG. 3A, two glass substrates 302 and 304 are joined together forming multiple individual FELs 306. The spacers 218 and the anodes 222 may also be seen. At the edges of the substrates 302, 306, pads 308 and 310 may in accordance to the present invention now connecting to the anode rows and cathode columns respectively. In comparison to the illustration provided in FIGS. 2A and 2B, where the pads are shifted 45 degrees, in FIG. 3A the shift is 90 degrees. It should be understood that it of course may be possible to select any angular degree of shift, for example dependent on the intended type of electrical contact interface to be used in the testing process.

(12) It should be specifically noted that it in accordance to an alternative aspect may be possible to arrange the electrical cathode connections for the field emission light sources to be electrically connected to each other in line with the columns, but to still keep the anodes as separate elements. This will make it possible to provide a single interface to all of the cathodes at the end of the wafer, while still having to individually probing/connecting to the anodes as those are provided as separate unconnected islands.

(13) FIG. 3B shows a partial cross section along the axis A-A in FIG. 3A. The individual FELs 306 are built on the substrate 302 by attaching cathodes 216 (possibly similar to what is shown in FIG. 2B), spacers 218 and the top glass substrate glass 304 also being the carrier of the anodes 222. Electrical connections are arranged in a continuous line to the edge of the substrates 302 where the pads 308 are formed, for a column of cathodes 216. Similarly, electrical connections are arranged in a continuous line to the edge of the substrates 304 where the pads 310 are formed, for a row of anodes 222. Again a distance must be used in order to accommodate the subdividing (e.g. sawing) of the substrates 302, 304 to form individual FELs 306. From FIG. 3B it is easy to realize that probes are preferably omitted entirely and replaced by multiple connection contact (as described earlier) inserted into the slots between the substrates 304 and 306 to make contact with all the rows and columns respectively at the same time, using suitable electrical contact interfaces.

(14) An exemplary comparison on device area savings is shown in Table 1 below. It is advantageous to make the devices in a circular fashion as avoiding corners and sharp edges often is beneficial when dealing with high electrical fields in order to avoid parasitic currents and arcing phenomena.

(15) The active device area is set by the anode area and the desire power output in combination with the desired anode lifetime (by intensity degradation). In this example 1cm.sup.2 has been used. The anode must have a certain distance to the inner wall of the spacer element, in these examples set to 1 mm. The spacer width is typically 1 mm.

(16) TABLE-US-00001 TABLE 1 Prior art Present implementation disclosure Anode area 1.00 1.00 cm2 Anode radius 5.65 5.65 mm Anode - sidewall distance 1.00 1.00 mm Spacer width 1.00 1.00 mm Glass disc overlap 1.00 0.00 mm Saw street 0.10 0.10 mm Total radius 8.75 7.75 mm Device diameter 17.50 15.50 mm Devices per 300 300 mm wafer 256 324

(17) When using top glass discs, an overlap outside the sealing spacer must be present in order to accommodate the contact structure, also in the case using a via. The sawing blade must have room with margin; 0.2 mm (i.e. 2 x 0.1 mm) should be sufficient using state of the art sawing equipment.

(18) The end result is that on an exemplary substrate wafer size of 300 x 300 mm the total possible devices is increased from 256 to 324 devices, providing an increase of 27% in regards to devices.

(19) In accordance to the present invention and in line with FIG. 4, there is provide a method of performing functionality testing of a plurality of field emission light sources, each field emission light source comprising a cathode side including an electrical cathode connection and an oppositely arranged anode side including an electrical anode connection, wherein the method comprises arranging, S1, the plurality of field emission light sources in vicinity of each other in a matrix formation having m rows and n columns, proving, S2, an electrical test point for each of the m rows and the n columns, and applying, S3, a control signal to at least one of the electrical test points at each of the m rows and to at least one of the electrical test points at each of the n columns, thereby energizing at least one of the field emission light sources for emitting light. Preferably, the method further comprises determining, S4, an operational status for the at least one energized field emission light source.

(20) In comparison to prior-art solutions for performing functionality testing of a plurality of field emission light sources the presently suggested approach will be greatly simplified.

(21) Although the figures may show a specific order of method steps, the order of the steps may differ from what is depicted. In addition, two or more steps may be performed concurrently or with partial concurrence. Such variation will depend on the software and hardware systems chosen and on designer choice. All such variations are within the scope of the disclosure. Likewise, software implementations could be accomplished with standard programming techniques with rule based logic and other logic to accomplish the various connection steps, processing steps, comparison steps and decision steps. Additionally, even though the invention has been described with reference to specific exemplifying embodiments thereof, many different alterations, modifications and the like will become apparent for those skilled in the art.

(22) Variations to the disclosed embodiments can be understood and effected by the skilled addressee in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. Furthermore, in the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality.