Digital control of switched boundary mode interleaved power converter with reduced crossover distortion

Abstract

A circuit arrangement, signal processor, and method for interleaved switched boundary mode power conversion are disclosed. The circuit arrangement comprises at least an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising: a first energy storage device; and a first controllable switching device; and one or more secondary interleaved circuits, each comprising: a secondary energy storage device; and a secondary controllable switching device; and a signal processor. The signal processor is connected to the controllable switching devices and comprises at least a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices The signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage to reduce the zero-crossing time.

Claims

1. A circuit arrangement for interleaved switched boundary mode power conversion, comprising at least: an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising: a first energy storage device; and a first controllable switching device; and one or more secondary interleaved circuits, each comprising: a secondary energy storage device; and a secondary controllable switching device; said circuit arrangement further comprising a signal processor, connected to the controllable switching devices; the signal processor comprising at least a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices, wherein the signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage to reduce a zero-crossing time, and wherein the signal processor is further configured to control a gain multiplier for at least one of an on-time period of the controllable switching devices and a switching cycle time, wherein in case one or more of the interleaved circuits are disabled, the gain multiplier is increased.

2. The circuit arrangement of claim 1, wherein the signal processor is further configured to re-enable one or more of the interleaved circuits when the alternating input voltage is higher than the first threshold voltage.

3. The circuit arrangement of claim 1, wherein the increase of the gain multiplier depends on the number of disabled interleaved circuits.

4. The circuit arrangement of claim 1, wherein the increase of the gain multiplier corresponds to the quotient of the total number of interleaved circuits in the circuit arrangement by the number of non-disabled interleaved circuits.

5. The circuit arrangement of claim 1, wherein the signal processor is further configured to control the gain multiplier so that the open loop system bandwidth is constant.

6. The circuit arrangement of claim 1, wherein the signal processor is further configured to control, in a given switching cycle, an on-time period of each non-disabled controllable switching device to correspond to each other.

7. The circuit arrangement of claim 1, wherein the signal processor is further configured to control phases between the on-time periods of the non-disabled switching devices, so that the on-time periods are distributed over the given switching cycle to reduce an overall current ripple at the input.

8. The circuit arrangement of claim 1, wherein the signal processor is configured to disable an increasing number of the controllable switching devices with a decrease of the alternating input voltage.

9. The circuit arrangement of claim 1, wherein the signal processor is configured to vary which interleaved circuits are disabled within a half-cycle of the alternating input voltage to equalize stress of the interleaved circuits.

10. The circuit arrangement of claim 1, wherein the signal processor is configured to vary which interleaved circuits are disabled in two subsequent half-cycles of the alternating input voltage to equalize stress of the interleaved circuits.

11. The circuit arrangement of claim 1, wherein the signal processor is configured with multiple different threshold voltages, wherein the first threshold voltage is the highest of the threshold voltages and each other threshold voltage of the multiple threshold voltages is half of a another threshold voltage of the multiple threshold voltages; and wherein the signal processor is configured to disable a number of interleaved circuits when the alternating input voltage falls below one of the multiple threshold voltages.

12. The circuit arrangement of claim 11, wherein the number of threshold voltages depends on the number of interleaved circuits of the circuit arrangement.

13. The circuit arrangement of claim 11, wherein the number of threshold voltages corresponds to the binary logarithm of the number of interleaved circuits of the circuit arrangement.

14. The circuit arrangement of claim 1, wherein the number of interleaved circuits of the circuit arrangement is a power of 2.

15. The circuit arrangement of claim 11, wherein one or more of the threshold voltages are predefined.

16. The circuit arrangement of claim 11, wherein the number of threshold voltages is dynamically determined, based on a peak level of the input voltage.

17. The circuit arrangement of claim 1, wherein the signal processor during zero-current switching is configured to control the switching devices at least at one zero-current point of the associated energy storage device.

18. The circuit arrangement of claim 1, wherein the signal processor is configured to control the switching devices from an off-state to an on-state at the at least one zero-current point.

19. The circuit arrangement of claim 1, wherein the signal processor is configured to control the on-time periods to correspond to each other in every switching cycle.

20. The circuit arrangement of claim 1, wherein the signal processor is configured to control the phases between the on-time periods of the first and the one or more secondary switching controllers in every switching cycle.

21. The circuit arrangement of claim 1, wherein each switching cycle controller is configured for PWM operation of the associated controllable switching device.

22. The circuit arrangement of claim 1, wherein the signal processor comprises a delay module, configured so that the at least one switching point is delayed for a predetermined delay time.

23. The circuit arrangement of claim 1, wherein the signal processor further comprises a limiter, configured to provide maximum on-time information to the PWM module.

24. The circuit arrangement of claim 1, wherein the circuit arrangement is a boost converter.

25. The circuit arrangement of claim 1, further comprising a rectifier circuit to rectify an AC input voltage.

26. A signal processor for use in a circuit arrangement for interleaved switched boundary mode power conversion with at least a first controllable switching device and one or more secondary controllable switching devices; said signal processor being connectable to the controllable switching devices and being configured for zero-current switching of the switching devices; wherein the signal processor comprises at least: a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices, wherein the signal processor is configured to disable one or more of the controllable switching devices when an alternating input voltage of the circuit arrangement is lower than a first threshold voltage, and wherein the signal processor is further configured to control a gain multiplier for at least one of an on-time period and a switching cycle time of at least one of the controllable switching devices, wherein in case one or more of the controllable switching devices are disabled, the gain multiplier is increased.

27. A method of interleaved switched boundary mode power conversion with a circuit comprising an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first controllable switching device; and one or more secondary controllable switching devices; wherein one or more of the controllable switching devices are disabled when the alternating input voltage is lower than a first predefined voltage, and wherein a gain multiplier for at least one of an on-time period and a switching cycle time of at least one of the controllable switching devices is controlled, wherein in case one or more of the controllable switching devices are disabled, the gain multiplier is increased.

28. A non-transitory machine-readable medium including contents that are configured to cause a signal processor to conduct the method of claim 27.

29. A circuit arrangement for interleaved switched boundary mode power conversion, comprising at least: an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising: a first energy storage device; and a first controllable switching device; and one or more secondary interleaved circuits, each comprising: a secondary energy storage device; and a secondary controllable switching device; said circuit arrangement further comprising a signal processor, connected to the controllable switching devices; the signal processor comprising at least a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices, wherein the signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage, and wherein the signal processor is further configured in case one or more of the interleaved circuits are disabled, to increase at least one of an on-time period and a switching cycle time of one or more of the controllable switching devices of one or more of the interleaved circuits that are not disabled.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other objects, features, and advantages of the current invention will become apparent from the following discussion of various embodiments. In the FIGS.,

(2) FIG. 1 shows a schematic block diagram of an embodiment of a circuit arrangement for switched boundary conduction mode (BCM) power conversion;

(3) FIG. 2 shows a diagram of the inductor current I.sub.L in an exemplary schematic PWM switching cycle;

(4) FIG. 3 shows diagrams of the operation of an interleaved circuit ILC.sub.N during a full cycle of an AC input voltage V.sub.IN;

(5) FIG. 4 shows a timing diagram of the interleaved operation of the circuit arrangement of FIG. 1;

(6) FIG. 5 shows exemplary waveforms of the rectified alternating input voltage V.sub.IN as well as the associated input current I.sub.IN in a BCM switching power converter circuit arrangement;

(7) FIG. 6 shows a schematic block diagram of a digital signal processor 9, configured to operate a total of N interleaved circuits ILC.sub.N;

(8) FIG. 7 shows a half-wave of the rectified input voltage V.sub.IN;

(9) FIGS. 8-9 show switching PWM waveforms during operation of the embodiment of FIG. 6;

(10) FIGS. 10-12 show waveform plots during the sections of the half-wave as discussed with reference to FIG. 7;

(11) FIG. 13 shows the waveform of the input current when a DSP operates as discussed with reference to FIGS. 7-12;

(12) FIG. 14 shows a further embodiment of a circuit arrangement for interleaved switched boundary mode power conversion;

(13) FIG. 15 shows a timing diagram related to the embodiment of FIG. 14;

(14) FIG. 16 shows a block diagram of a signal processor as used in the embodiment of FIG. 14;

(15) FIG. 17 shows a timing diagram related to the embodiment of FIG. 14;

(16) FIGS. 18 and 19 shows schematic block diagrams of further embodiments of a signal processor; and

(17) FIG. 20 shows a more detailed schematic block diagram of the embodiment of FIG. 19.

DETAILED DESCRIPTION

(18) Technical features described in this application can be used to construct various embodiments of circuit arrangements, signal processors, and integrated circuit devices. Some embodiments of the invention are discussed so as to enable one skilled in the art to make and use the invention.

(19) As discussed in the preceding, and in one aspect, a circuit arrangement for interleaved switched boundary mode power conversion is provided that comprises at least an input for receiving an input voltage from a power supply, an output to provide an output voltage to a load, a first interleaved circuit, one or more secondary interleaved circuits, and a signal processor.

(20) According to this aspect, the first interleaved circuit comprises at least a first energy storage device and a first controllable switching device. The one or more secondary interleaved circuits each comprise at least a secondary energy storage device and a secondary controllable switching device. The signal processor is connected to the controllable switching devices and comprises at least a first switching cycle controller, configured for cycled/recurrent zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled/recurrent zero-current switching operation of the secondary controllable switching devices.

(21) The signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage to reduce the zero-crossing time.

(22) In the context of the present discussion, the term switched boundary mode power conversion is understood as switched-mode electric power conversion in boundary conduction mode (BCM). A corresponding converter circuit comprises at least an energy storage device and a switching device for storing input energy temporarily and then releasing that energy to the output at a different voltage.

(23) In some embodiments, the value of the energy storage device such as an inductor may be selected to be large in comparison to the total resistance in the circuit. The resistance (R) could be present in the form of inductor resistance, switching device resistance, filter resistance, board trace resistance etc. The inductor current in some embodiments follows a path based on the final value of current during ON time as If*e{circumflex over ()}(t/) where If=Vin/R, =L/R. The inductor current appears as a straight line if is large. One way to increase the value of is to reduce the resistance (R) value by using efficient switches and inductors. During the OFF time, the load resistance contributes to R in addition to other resistances. The value of L may be set in some embodiments by the input voltage, load range, and switching frequency limits.

(24) In BCM, a new switching period is initiated when the current through the energy storage device returns to zero, which is at the boundary of continuous conduction (CCM) and discontinuous conduction mode (DCM).

(25) Interleaved power conversion and a corresponding interleaved power converter is understood as using multiple stages, also referred to as interleaved circuits in the following, which are operated out of phase. For example, in an interleaved power converter having two interleaved circuits, the circuits typically operate at 180 degrees out of phase. In the present context, an interleaved circuit comprises at least an energy storage device and a controllable switching device. Typically, the interleaved circuits are connected in parallel with each other.

(26) An energy storage device in the present context is understood as a device for storing electrical energy at least temporarily. For example, an energy storage device may comprise one or more inductors/inductances and/or one or more capacitors/capacitances.

(27) A controllable switching device in the present context may be of any suitable type to control an electrical current. The switching device may comprise for example one or more semiconductor switches, such as bipolar transistors, field-effect transistors, MOSFETs, IGBTs, SiCs, GANs, etc.

(28) According to the present aspect, the circuit arrangement comprises the signal processor. In this context, a signal processor is understood as a device that allows for cycled controlling of the switching device, for example according to a pulse-width-modulation (PWM), with a frequency in the kHz range. In some examples, the signal processor is configured to control the switch in PWM mode with a frequency of approximately 500 kHz. In some embodiments, the signal processor is a digital signal processor (DSP), e.g., a DSP with PWM units, ADCs, etc. A DSP architecture facilitates faster execution of instructions for the zero-current point detection.

(29) The signal processor according to the present aspect comprises at least a first switching cycle controller and one or more secondary switching cycle controllers, which switching cycle controllers are configured for zero-current switching. In this context, zero-current switching is understood as controlling the switching device when no or just a minor current of, e.g., less than 100 A, is flowing. As will be apparent in view that the circuit arrangement is configured for boundary conduction mode operation, zero-current switching in particular relates to the control from an off-state, i.e., non-conductive state of the switching device, to an on-state, i.e., a conductive state of the switching device when no or just a minor current is flowing.

(30) A zero-current point of the energy storage device in the context of the present explanation is understood as the point in time when the energy storage device is completely discharged after a charge/discharge cycle, also referred to as switching cycle herein.

(31) A switching cycle in this context is consequently understood as the combined time of the respective controllable switching device being set conductive, i.e., in the on-state, and the controllable switching device subsequently being set non-conductive, i.e., in the off-state. In case of a PWM control, the switching cycle corresponds to the PWM cycle time T.

(32) A mid-cycle time corresponds to half the switching cycle period and is thus a point in time in each switching cycle that is equally spaced between two subsequent zero-current points of the energy storage device.

(33) According to the present aspect, the signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage to reduce the zero-crossing time. The term zero-crossing time relates to the time, the input current remains close to 0 A when the input voltage is at a zero-crossing, i.e., 0V.

(34) The threshold voltage herein is understood as a threshold, determined by the signal processor. In some embodiments, the level of the threshold voltage is predefined, e.g., by the number of interleaved circuits present. In additional or alternative embodiments, the level of the threshold voltage is changed dynamically by the signal processor, such as, e.g., based on an input voltage level (peak) from a previous half cycle of an alternating input voltage.

(35) The term alternating input voltage herein refers to a true alternating voltage or a full wave rectified positive or negative input voltage. It is noted, that the disabling of a interleaved circuit herein means that the respective controllable switching device is not operated and set to a non-conductive state. Accordingly, the term of a disabled interleaved circuit corresponds to a disabled switching device and these terms are used interchangeably. Similarly, a non-disabled interleaved circuit means that the respective controllable switching device is operated normally according to one of the switching patterns described herein, i.e., a non-disabled switching device or a remaining/operational switching device.

(36) In some embodiments, and in a given switching cycle, an on-time period of each of the controllable switching devices is controlled by the signal processor to correspond to an each other. Accordingly, the time period in the switching cycle, in which each of the switching devices are controlled conductive, at least substantially matches, i.e., is substantially the same. In this context, the term substantially is understood to comprise slight deviations in the on-time periods of some nanoseconds. A deviation in the switching time period of the multiple interleaved circuits may be in the range of some 100 nanoseconds.

(37) In some embodiments, the signal processor is further configured to control a gain multiplier for at least one of an on-time period of the controllable switching devices and a switching cycle time, wherein in case one or more of the interleaved circuits are disabled, the gain multiplier is increased.

(38) In the present context, the term gain multiplier is a multiplication factor used when one or more interleaved circuits are disabled. The signal processor may in some embodiments be configured so that the gain multiplier affects the on-time period of the operable controllable switching devices and/or the switching cycle time of the operable switching devices, i.e., the non-disabled switching devices of corresponding non-disabled interleaved circuits. A main idea of using the gain multiplier is to increase the on-time and thereby to further reduce the switching frequency and to keep the dynamic performance of the circuit unaffected by the disabling of one or more interleaved circuit.

(39) In some embodiments, the signal processor is configured, so that the gain multiplier affects the on-time period and the switching cycle time of the operable switching devices.

(40) In some embodiments, the increase of the gain multiplier depends on the number of disabled interleaved circuits. In alternative or additional embodiments, the increase of the gain multiplier corresponds to the quotient of the total number of interleaved circuits in the circuit arrangement by the number of non-disabled interleaved circuits.

(41) In some embodiments, the gain multiplier is set in such a way that the open loop system bandwidth is the same for all operating conditions. Due to this, the system transient response is same throughout. The time required for the output to settle in the event of a load change may be the same throughout independent of the number of stages operating.

(42) The term open loop system bandwidth herein is understood as the frequency at which the value of the open loop system gain is 3 dB below the DC gain. The term open loop system bandwidth typically is used in conjunction with the Bode stability analysis. The Bode analysis may predict the closed loop system stability based on the open loop gain. Bandwidth determines the transient response of the system to changes in external load conditions.

(43) According to some embodiments, the signal processor is further configured to control phases between the on-time periods of the first and the one or more secondary switching controllers, so that the on-time periods are distributed over the given switching cycle.

(44) As will be apparent, this may equalize the current input and thus reduce an overall current ripple at the input and consequently reduce electromagnetic interference effects.

(45) In some embodiments, the on-time periods are distributed evenly over the given switching cycle, which provides a particularly beneficial reduction of overall current ripple. However, it is noted that any distribution of the on-time periods, i.e., avoidance of having the on-time periods of all controllable switching devices simultaneously, will reduce the overall current ripple.

(46) In some embodiments, the signal processor is further configured to control, in a given switching cycle, an on-time period of the controllable switching devices, wherein in case one or more of the interleaved circuits are disabled, the on-time period of controllable switching devices of non-disabled, i.e., the remaining operational interleaved circuits, is increased. In some embodiments, the increase of the on-time period depends on the number of disabled interleaved circuits. In further embodiments, the increase in on-ime does not alter the dynamic performance of the system at any point in the alternating input voltage cycle.

(47) In some embodiments, the phases between the on-time periods of the non-disabled interleaved circuits is set to correspond to ((n1))/N*360, where N is the total number of interleaved non-disabled circuits and n is an index number of the respective secondary interleaved circuit. Accordingly, for a given secondary interleaved circuit n, the respective phase can be determined as

(48) $\frac{\left(n-1\right)}{N}*360.$

(49) For example, given a total of N=3 operational interleaved circuits, the phase of a first secondary interleaved circuit, i.e., circuit n=2, is 120 degrees, while the phase of a second secondary interleaved circuit, i.e., circuit n=3, is 240 degrees. It is noted, that the term phase herein relates to the delay, the controllable switching device of the respective secondary interleaved circuit is set to an on-state, compared with the time, the controllable switching device of the first interleaved circuit is set to an on-state. The angular phase is defined over the switching cycle, e.g., in a PWM, the PWM cycle with time T.

(50) In some embodiments, the signal processor is configured to disable an increasing number of the controllable switching devices with a decrease of the alternating input voltage.

(51) In some embodiments, the signal processor is configured with multiple different threshold voltages. For example, first threshold voltage may be the highest of the threshold voltages and each other threshold voltage of the multiple threshold voltages is half of a another threshold voltage of the multiple threshold voltages, so that a staggered setup of threshold voltages result. For example, the number of threshold voltages may depend on the number of interleaved circuits of the circuit arrangement.

(52) In some embodiments, the signal processor is configured to disable a number of interleaved circuits when the alternating input voltage falls below one of the multiple threshold voltages. In one example, one interleaved circuit is disabled per threshold voltage. In another example, the number of interleaved circuits that are disabled depends on the number of threshold voltages and secondary interleaved circuits to distribute the disabling of interleaved circuits equally between a peak of the alternating input voltage and a subsequent zero-crossing, where all interleaved circuits are operated upon a peak and only the first interleaved circuit is operated at a zero-crossing. In some embodiments, the number of threshold voltages is selected as a multiple of 2 to allow an efficient implementation.

(53) In some embodiments, the number of threshold voltages corresponds to the binary logarithm of the number of interleaved circuits of the circuit arrangement. In alternative embodiments, number of threshold voltages is dynamically determined, based on a peak level of the input voltage, i.e., a peak from the previous half cycle of the alternating input voltage.

(54) In some embodiments, the one or more of the threshold voltages, i.e., the number and/or voltage levels of each threshold voltage, are predefined, e.g., my the manufacturer of the circuit arrangement.

(55) Reference will now be made to the drawings in which the various elements of embodiments will be given numerical designations and in which further embodiments will be discussed.

(56) Specific references to components, modules, units, devices, sections, parts, process steps, and other elements are not intended to be limiting. Further, it is understood that like parts bear the same or similar reference numerals, when referring to alternate figures. It is further noted that the figures are schematic and provided for guidance to the skilled reader and are not necessarily drawn to scale. Rather, the various drawing scales, aspect ratios, and numbers of components shown in the figures may be purposely distorted to make certain features or relationships easier to understand.

(57) FIG. 1 shows a schematic block diagram of an embodiment of a circuit arrangement for switched boundary conduction mode (BCM) power conversion, namely in the instant embodiment, a switched-mode boost converter circuit 1.

(58) The boost converter circuit 1 comprises an input or input stage 2, configured for connection to a typical mains connection, e.g., at 110V, 60 Hz or 240V, 50 Hz. A bridge rectifier 3 is provided at the input 2 to obtain positive half-waves. The boost converter circuit 1 further comprises a first interleaved circuit ILC.sub.1 and multiple secondary interleaved circuits ILC.sub.2, . . . , to ILC.sub.N, connected with each other in parallel and each comprising an energy storage device in the form of an inductor L.sub.N, MOSFET switching device S.sub.N, and flyback diode D.sub.N, where the index N refers to the respective interleaved circuit ILC.sub.1, ILC.sub.2, . . . , to ILC.sub.N. As will be apparent from FIG. 1, the boost converter circuit 1 may comprise any number of interleaved circuits ILC greater than one, depending on the respective application and in particular, on the overall current that is to be delivered to load 11. Boost converter circuit 1 further comprises output capacitor 7, output 8, and a digital signal processor (DSP 9; not shown in FIG. 1) for operating the gates G.sub.1, G.sub.2, . . . , G.sub.N of MOSFET switching devices S.sub.1, S.sub.2, . . . , S.sub.N as explained in the following.

(59) The general operation of circuit 1 corresponds to that of a typical boost converter. For reasons of clarity, the functionality of one interleaved circuit ILC will be discussed first, followed by a discussion of interleaved operation.

(60) Inductor L.sub.N of circuit ILC.sub.N is charged when the respective MOSFET S.sub.N is in the on state. Once inductor L.sub.N is charged, MOSFET S.sub.N is switched to the off state, so that the only remaining current path is through the flyback diode D.sub.N and load 11, the latter of which is shown in FIG. 1 as a resistance. The voltage increases in view of the increased current from both, the inductance 4 and the the input 2. The energy stored in the inductor L.sub.N during the on state is discharged into the load resistance 11 through diode D.sub.N, when the MOSFET S.sub.N is in the off state.

(61) In typical BCM operation, a new switching period of the PWM is initiated when the current through the inductor 4, i.sub.LN, returns to zero. FIG. 2 shows a diagram of the inductor current i.sub.L in an exemplary schematic PWM switching cycle. The rising current slope typically may correspond to V.sub.IN/L and the falling current slope may typically correspond to

(62) $\frac{\left(V_{\mathrm{IN}}-V_{\mathrm{OUT}}\right)}{L}.$

(63) As can be seen from the bottom part of FIG. 2, a PWM control signal is applied to MOSFET S.sub.N. When the PWM signal is high, MOSFET S.sub.N is conductive and the current I.sub.LN in the inductor L.sub.N increases. This time period is described herein as T.sub.ON time. Once the desired charge of inductor L.sub.N is reached, the PWM signal is controlled to low and MOSFET 5 is set non-conductive. The current I.sub.LN gradually decreases until the inductor L.sub.N is fully discharged. This time period is described herein as T.sub.OFF time. Both, T.sub.ON and T.sub.OFF are a switching cycle T, i.e., in this embodiment, a PWM/switching cycle T.

(64) When the inductor L.sub.N is fully discharged, i.e., at a zero-current point in time in the PWM cycle, the next PWM cycle begins. The PWM signal correspondingly is controlled high and MOSFET S.sub.N is switched conductive.

(65) As discussed in the preceding, BCM avoids switching losses in view that the MOSFET S.sub.N is controlled from an off-state to an on-state when no substantial current flows, which is referred to herein as zero-current switching.

(66) FIG. 3 shows diagrams of the operation of an interleaved circuit ILC.sub.N during a full cycle of AC input voltage V.sub.IN. As will be apparent from the FIG., the inductor L.sub.N is charged and discharged multiple times in each half-cycle of the input voltage in accordance with the PWM signal, shown in FIG. 3 as V.sub.PWM. The converter circuit 1 and more precisely, each interleaved circuit ILC.sub.N operates with a variable switching frequency, which depends primarily on the desired output reference voltage V.sub.O, ref, the instantaneous value of the input voltage V.sub.IN, the inductor value of inductor 4, and the output power delivered to the load R.sub.L 11.

(67) The operating frequency changes as the input current follows the sinusoidal input voltage waveform, as shown in FIG. 3. The lowest frequency occurs at the peak of sinusoidal input, i.e., line voltage. As will be apparent from FIG. 3, and since the current waveform of I.sub.L is roughly triangular, the average value in each PWM period is proportional to the input voltage V.sub.IN. Thus, provided a sinusoidal V.sub.IN, the input current TIN of the circuit 1 follows the waveform of V.sub.IN with high accuracy and draws a sinusoidal input current from the mains. Accordingly, operating the converter 1 in BCM is ideal for power factor correction (PFC).

(68) While FIGS. 2 and 3 show the operation of each of the interleaved circuit ILC.sub.N, FIG. 4 shows a timing diagram of the interleaved operation of a circuit arrangement 1 with an exemplary total number of N=4 interleaved circuits. As will be apparent from FIG. 4, interleaved circuits ILC.sub.N, i.e., the gates G.sub.N of corresponding MOSFETS S.sub.N of circuits ILC.sub.N are operated out of phase to reduce a current ripple i.sub.IN at the input 2, which is significantly smaller than i.sub.L, i.e., the maximum difference/span of current i.sub.L of one of the interleaved circuits ILC.sub.N.

(69) In the present embodiments, the operation of each secondary interleaved circuit ILC.sub.N is shifted versus the first interleaved circuit ILC.sub.1 by

(70) $\frac{\left(n-1\right)}{N}*360,$
where N is the total number of interleaved circuits and n is an index number of the respective secondary interleaved circuit. It follows that in the example of FIG. 4, ILC.sub.2 shows a phase shift of 90, ILC.sub.3 shows a phase shift of 180, and ILC.sub.4 shows a phase shift of 270 to equalize or distribute the current draw from input 2 evenly over a given switching cycle T, reducing electromagnetic interference (EMI) effects and thus allows for smaller and more cost-efficient EMI filters.

(71) As however will also be apparent from FIG. 4, the interleaved operation results in a high frequency current ripple, which is particularly high near the zero-crossings of the alternating input voltage in view of the small voltage levels and the subsequent fast PWM cycles. In view that typical EMI filters attenuate high frequency components, the high frequency current ripple leads to a limited current draw. This results in a zero-current situation being prolonged, leading to a distorted input current waveform and thus, a comparably high THD, as can be seen from FIG. 5, which shows exemplary waveforms of the rectified alternating input voltage V.sub.IN as well as the associated input current I.sub.IN in a BCM switching power converter circuit arrangment. Reference numeral 50 marks the prolonged zero-current times. The distortion of I.sub.IN is readily apparent from FIG. 4.

(72) To counter the above effects, DSP 9 is configured to disable interleaved circuits when the input voltage V.sub.IN is falls below predefined voltage thresholds and to simultaneously increase a gain multiplier that sets the on-time T.sub.ON and the PWM cycle time T of the remaining, i.e., non-disabled interleaved circuits.

(73) FIG. 6 shows a schematic block diagram of a digital signal processor 9, configured to operate a total of N interleaved circuit ILC.sub.N. Certainly, the digital signal processor 9 in this case comprises a corresponding number of PWM drive modules PWM.sub.N. A voltage signal, corresponding to V.sub.OUT is provided to subsequently sampled by the comparators 53. A predefined output voltage reference V.sub.O,REF is obtained from memory 40.

(74) Signal processor 9 calculates the on-time for the PWM, T.sub.ON, from V.sub.OUT, i.e., the current output voltage and the predefined voltage reference V.sub.O,REF. Summing node 46 compares the current output voltage V.sub.OUT with the set point V.sub.O,REF. The resulting error signal is provided to filter/compensator 47, which runs at a relatively low frequency, e.g., 10 Hz, to remove second harmonic components, typically present in the output voltage V.sub.OUT.

(75) The resulting signal corresponds to T.sub.ON and is provided to a switch matrix, comprising switches S.sub.N1 and S.sub.N2. Switches S.sub.N allow to enable and disable the PWM modules and subsequently, the switching device of the respective interleaved circuit. Switches S.sub.N1 allow to let the T.sub.ON signal pass one of N gain multiplier modules 61a-61n. In some implementations, the total time T is processed by the same gain multiplier modules 61a-61n (not shown in FIG. 6).

(76) The resulting operation of DSP 9 is described in the following with reference to FIGS. 7-9, which show various timing diagrams for an exemplary circuit arrangement with four interleaved circuits ILC.

(77) FIG. 7 shows a half-wave of the rectified input voltage V.sub.IN. As can be seen, two threshold voltages are defined V.sub.thresh and V.sub.thresh/2. The threshold voltage V.sub.thresh is based on the power handling capability of individual stage relating to the requirements at the output, so that enough current can be provided at the output at all times. The threshold voltages define switching points, where some of the secondary interleaved circuits are disabled, i.e., when the input voltage V.sub.IN falls below the respective threshold. For clarity, the different timing segments have been marked in FIG. 7. Section II describes the time in the half-wave, where the input voltage V.sub.IN is higher than the highest threshold voltage V.sub.thresh. Sections I and III describe the time in the half-wave, where the input voltage V.sub.IN is lower than the highest threshold voltage V.sub.thresh. As will be apparent, subsections ab and ba relate to the time in the half-wave, where the input voltage V.sub.IN is lower than the lower threshold voltage V.sub.thresh/2.

(78) When the input voltage V.sub.IN is above the threshold voltage V.sub.thresh, all the interleaved circuits are active and enabled. The output load is effectively shared by all the N converters. The switching pattern in this section of the half-wave corresponds to FIG. 4, i.e., normal interleaved operation.

(79) When the input voltage is less than V.sub.thresh, the total time is divided into log 2(N) subsections as shown in FIG. 7. There are two subsections for the input voltage below V.sub.thresh namely ab and ba. When the input voltage V.sub.IN is rising from zero towards the peak (ascending, section I), the first subsection ab is active. During this time, the first interleaved circuit is active, and the gain multiplicator is 4. Thus, the times T and T.sub.ON are four times the nominal times if all interleaved circuits were active. The frequency of the first interleaved circuit is of the nominal frequency in consequence. All other interleaved circuits are switched off/disabled, and only the first interleaved circuit supplies the load current. The switching PWM waveforms are as shown in FIG. 8.

(80) The operation will continue in this subsection until the input voltage V.sub.IN increases beyond V.sub.thresh/2. When the input voltage V.sub.IN is higher than V.sub.thresh/2, the operation enters subsection bc. During this time, the the first and one of the secondary interleaved converters are controlled operative at twice the period time T and on-time T.sub.ON, i.e., at half the nominal frequency, while the two remaining secondary interleaved circuits are switched off. The switching PWM waveforms are as shown in FIG. 9. The gain multiplicator is set to 2. It is noted that the two active interleaved circuits are operated in an interleaved way, as can be seen from FIG. 9, and to distribute the on-time periods over the switching cycle T.

(81) When the input voltage V.sub.IN exceeds V.sub.thresh, all the 4 interleaved circuits operate with a gain multiplicator of 1 (section II). The switching PWM waveforms are as shown in FIG. 4.

(82) In the descending section II, when the input voltage falls below V.sub.thresh, the operation enters subsection cb. During this time, the 3rd and 4.sup.th interleaved circuits are active with a gain multiplicator of 2 and half the nominal switching frequency, i.e., corresponding to FIG. 9, however with the lower two gates G.sub.3 and G.sub.4 driven instead of gates G.sub.1 and G.sub.2. When the input voltage falls below V.sub.thresh/2, the subsection ba becomes active. During this time, the interleaved circuit 4 operates with a frequency of times the nominal frequency and a gain multiplicator of 4, while all other interleaved circuits are disabled.

(83) In the next half-wave of the AC input voltage cycle, and during the subdivision ab, interleaved circuit 2 takes place of interleaved circuit 1, and interleaved circuit 4 takes place of interleaved circuit 4 during subdivision ba. The interleaved circuits are interchanged in order to provide uniform stresses to all the interleaved circuits thereby increasing reliability. The switching sequence for N=4 is provided in Table I below.

(84) TABLE-US-00001 TABLE I Active AC Cycle Section Subsection interleaved circuits Gain Frequency Positive I ab 1 4 Fsw/4 Positive I bc 1, 2 2 Fsw/2 Positive II cc 1, 2, 3, 4 1 Fsw Positive III cb 3, 4 2 Fsw/2 Positive III ba 4 4 Fsw/4 Negative I ab 2 4 Fsw/4 Negative I bc 1, 2 2 Fsw/2 Negative II cc 1, 2, 3, 4 1 Fsw Negative III cb 3, 4 2 Fsw/2 Negative III ba 3 4 Fsw/4

(85) FIGS. 10-12 show waveform plots during the sections of the half-wave as discussed in the preceding. It is noted, that the switching of only two interleaved circuits is shown for clarity, labeled PWM1 and PWM2. FIG. 10 shows the transition from a zero-crossing in section I. FIG. 11 shows the signals at peak of the alternating input voltage, i.e., in section II, while FIG. 11 shows the transition from peak to the next zero-crossing in section III.

(86) FIG. 13 shows the waveform of the input current when the DSP operates as discussed in the preceding, namely with the disabling pattern described. When comparing FIG. 13 with FIG. 5, it will be apparent that the input current ills is much smoother, compared to FIG. 5 and in particular, the waveform does not comprise the prolonged zero-times 50.

(87) As the inventors have ascertained, the THD can thus be reduced substantially. Experiments have shown that when operating the invention, THD corresponds to 10.22% without correction and 6.92% with correction.

(88) FIG. 14 shows a further embodiment of a circuit arrangement 51 for interleaved switched boundary mode power conversion. The circuit arrangement 51 corresponds to the circuit arrangement 1 with the following exceptions. First, circuit arrangement 51 only comprises a first interleaved circuit ILC.sub.1 and a second interleaved circuit ILC.sub.2, i.e., a two-stage setup. It is noted that FIG. 14 only shows two stages for clarity. Certainly, more than two-stages are possible in corresponding alternative embodiments.

(89) Each interleaved circuit, in addition to inductor L.sub.N, MOSFET switching device S.sub.N, and flyback diode D.sub.N, comprises a current sensor ZCD.sub.N, comprising a secondary inductor, inductively coupled to the respective inductor L.sub.N, as well as an associated comparator IZCD.sub.N. Current sensors ZCD.sub.N are connected to digital signal processor 52 to allow zero-current switching operation. Two further comparators I.sub.CH1 and I.sub.CH2 are provided to determine the current through the respective MOSFET S.sub.1 and S.sub.2. Further comparators 54 and 53 are arranged to determine the input voltage V.sub.IN and V.sub.OUT, respectively. DSP 52 in the present embodiment is of dsPIC33EP series type, available from Microchip Technology Inc., Chandler, Ariz., USA.

(90) Digital signal processor 52 may be operated in different operating modes. In the following, an exemplary phase update mode is discussed with reference to the timing diagram of FIG. 20.

(91) In this embodiment, digital signal processor 52 determines the parameters for PWM operation of the two MOSFETs S.sub.1 and S.sub.2. DSP 52 correspondingly comprises at least two internal PWM drive modules, configured in current reset mode.

(92) In particular, current sensors ZCD.sub.N provide the instant time in each PWM cycle, where the current through the respective inductor L.sub.N reaches zero, which is used as a current reset trigger and thus to restart a new PWM cycle in current reset mode operation.

(93) The desired on-time of the two MOSFETs S.sub.1 and S.sub.2 is determined from the current voltage V.sub.OUT at output 8 and comparator 53 and a reference voltage V.sub.O,REF that is predefined in internal memory of the DSP 52 by the manufacturer or the user of DSP 52. V.sub.O,REF corresponds to the desired voltage at output 8, applied to load 11. It is noted that the on-time of MOSFET S.sub.1 is set to correspond to the on-time of MOSFET S.sub.2 in every PWM cycle.

(94) In addition to the above, the total PWM cycle time T is determined from the preceding PWM cycle. While doing so provides a one-cycle delay in the cycle time T, the resulting error is comparably small, even considering the changing frequency of the switching operation, as discussed in the preceding with reference to FIG. 3. To determine the PWM cycle time T, the DSP 52 is programmed to determine the elapsed time between the latest two rising edges of the PWM signal, that is provided to MOSFET S.sub.1, i.e., the PWM signal, applied to the first interleaved circuit. Alternatively, the PWM cycle may be sampled using an input capture pin of the DSP 52, should the latter be present with the respective type of DSP 52 used.

(95) With reference to the timing diagram of FIG. 20 and as shown, both interleaved circuits and more precisely MOSFETs S.sub.1 and S.sub.2 are operated with PWM signals. In FIG. 20, PWM1 refers to the PWM signal, applied to MOSFET S.sub.1 and PWM2 refers to the PWM signal, applied to MOSFET S.sub.2. I.sub.1 and I.sub.2 refer to the currents through inductors L.sub.1 and L.sub.2, respectively.

(96) Both MOSFETs are driven with the same-on time in each PWM switching cycle, which allows zero-current switching and thus operation in BCM mode. PWM2 is phase shifted compared to PWM1 by half a PWM cycle, i.e., T/2, for a fully interleaved operation. The phase of PWM2 is set at the start of each switching cycle of PWM1. An alignment/update of the zero-current instant and the cycle time T is conducted at the end of each cycle, if there is any difference in the instant of the zero-current instant and phase, which can occur during short transient conditions.

(97) FIG. 15 shows the resulting currents I.sub.1 and I.sub.2 for multiple inductances. As the current inventors have determined, differing inductances between the different interleaved circuits only has a negligible effect on the timing, so that slight variations in the inductances have only little effect on the timing when operating as discussed herein. It is noted however, that the power shared by the current in a given stage is inversely proportional to the value of the stage inductance, so that in some embodiments, identical inductances are used in all interleaved circuits.

(98) As discussed in the preceding with reference to timing chart FIG. 15, the discussed interleaved BCM operation requires setting the phase of the secondary interleaved circuit in every PWM cycle, in particular in view of the changing switching frequency in boundary conduction mode. In view that some commercially available digital signal processors do not allow a phase update when operating in current reset mode, a corresponding further embodiment for the operation of the digital signal processor 52 of FIG. 14 is discussed in the following with reference to the block diagram of FIG. 16 and the timing diagram of FIG. 17, also referred to as PWM synchronization mode. Both operating modes of digital signal processor 52, i.e., the operation discussed in the preceding with reference to FIG. 15 and the operation discussed in the following with reference to FIGS. 16 and 17 may be realized in software and/or hardware, wherein the software may be comprised in an internal memory (not shown) of digital signal processor 52. While the DSP 52 may comprise software for both operating modes, so that the desired mode can be set during operation, it is certainly sufficient, when one operating mode is provided, depending on the capabilities of the type of DSP used.

(99) As will be apparent from FIG. 16, the current embodiment uses two intermediate PWM modules, namely PWMa and PWMb to obtain PWM2 for controlling the secondary interleaved circuit and MOSFET S.sub.2. It is noted that all PWM modules according to this embodiment are operated in current reset mode.

(100) PWM1 is generated as discussed in the preceding with reference to FIG. 15, namely based on the zero-current point, determined by ZCD.sub.1. Based on the detected zero-current point, comparator circuit CMP.sub.1 generates a pulse to start or restart (reset) a PWM cycle for signal PWM1. Corresponding to the preceding operating mode, the desired on-time of the two MOSFETs S.sub.1 and S.sub.2 is determined from the current voltage V.sub.OUT at output 8 and comparator 53 and the reference voltage V.sub.REF. The total PWM cycle time T is determined from the preceding PWM cycle, as discussed. It is noted that all comparator circuits CMP.sub.N are peripherals of the DSP.

(101) With respect to the generation of PWM2, intermediate PWMb signal is generated from the determined zero-current point of the secondary interleaved circuit, as determined by the zero-current sensor ZCD.sub.2, and a corresponding start or restart pulse, generated by comparator circuit CMP.sub.2. The PWMb signal thus starts a new cycle upon the determined zero-current point and thus determines the instant of the zero-current point. The PWMb signal is provided to a further PWM module for generating PWMa. This PWM module also receives the CMP.sub.1 signal, as well as the determined PWM cycle time T. PWMa is started or restarted using the CMP.sub.1 pulse, corresponding to a zero-current point of the first interleaved circuit. PWMa is programmed with a duty cycle T/2, i.e., half of the PWM cycle time of the first interleaved circuit. PWMb is used to truncate PWMa at the zero-current point of the secondary interleaved circuit, as shown in the timing diagram of FIG. 17.

(102) The PWMa signal is provided to a fourth PWM module of DSP 52 to provide PWM2 to the MOSFET S.sub.2 of the secondary interleaved circuit, using a falling edge of PWMa to trigger a start or restart of a PWMb cycle. The on-time of PWMb is set to correspond to the on-time of PWMa.

(103) In this embodiment, the comparators CMP.sub.1 and CMP.sub.2 also allow to add a control delay for the switching of MOSFETS S.sub.1 and S.sub.2. Such a delay may be useful in view that considering typical parasitic capacitances, in particular of MOSFETS S.sub.1 and S.sub.2, the actual zero moment of the inductors may not ideal for the switching in view the voltage across the parasitic capacitance of the of MOSFETS S.sub.1 and S.sub.2 in this case would discharge through the of MOSFETS S.sub.1 and S.sub.2. To counter this loss, a delay may be introduced. The delay time is predefined, based on the parasitic capacitance value. Typical delay times range between 100 nanoseconds and 400 nanoseconds. It is noted that in view of the rather small delay introduced in the switching of MOSFETS S.sub.1 and S.sub.2, the delayed switching points are still considered as zero-current points herein.

(104) FIG. 18 shows a schematic block diagram of a digital signal processor 92, operating according to the preceding operating modes for a total of N interleaved circuit ILC.sub.N. Certainly, the digital signal processor 72 in this case comprises a corresponding number of PWM drive modules.

(105) FIG. 19 shows a further embodiment of a digital signal processor 102 in a schematic block diagram. As can be seem from the FIG., the present embodiment uses the voltages V.sub.IN, V.sub.OUT, and V.sub.REF to control the PWM operation, without a current measurement being necessary. Accordingly, current sensors ZCD.sub.N can be omitted herein, thus reducing the cost and size of the overall setup.

(106) Using the two voltage signals, corresponding to V.sub.IN and V.sub.OUT, as well as a predefined voltage reference V.sub.O,REF, provided again by an internal memory (not shown) of digital signal processor 102, the digital signal processor 102 calculates the zero-current points in each PWM cycle, i.e., the points in time, where the inductor currents i.sub.LN respectively reaches zero.

(107) The signal processor 102 in the present embodiment is a digital signal processor of dsPIC33 series type.

(108) FIG. 20 shows a more detailed schematic block diagram of the embodiment of FIG. 19.

(109) The first (corresponding to V.sub.IN) and second (corr. to V.sub.OUT) voltage signals are received at and subsequently sampled by the respective comparators 54 and 53 (see FIG. 19). The predefined voltage reference V.sub.O,REF is obtained from memory 40.

(110) Signal processor 102 is configured to sample the voltage signals at T/2 when the duty cycle of the PWM is lower than 50%, i.e., when V.sub.IN>V.sub.OUT/2 to V.sub.IN,PEAK. This provides that the period corresponds to the average of the input voltage. The bulk of the power transfer occurs during this interval. Since the duty cycle and the frequency are low in this case, there is adequate time for calculating the next zero-current point and the switching period.

(111) For the remainder of the input voltage half-wave, the sampling frequency goes higher towards the zero-current point and there is no adequate time for computation if sampling would be done at T/2. Instead, for a duty cycle of equal to or higher than 50%, the signal processor 9 is configured to sample the voltage signals near the start of the cycle, for example after a small delay of 20 ns for switching transients to die down. Since the input voltage is small compared to its peak, the difference between the values sampled at start and T/2 is not significant

(112) The two voltage signals are provided to operational amplifiers 41a, 41b for signal conditioning and then provided to analog-to-digital (ADC) circuits 42a, 42b. The two ADC circuits 42a, 42b convert the voltage signals to digital information and are of 12 bit type with a Vmin: 0V and a Vmax: 3.3V.

(113) Signal processor 102 further comprises multiple modules to provide the total PWM cycle time T and the on-time T.sub.ON to the PWM modules PWM.sub.N. As shown in the upper part of FIG. 20, subtraction module 43 and division module 44 provide

(114) $\frac{V_{\mathrm{OUT}}}{\left(V_{\mathrm{OUT}}-V_{\mathrm{IN}}\right)}$
to multiplication module 45. The upper path, shown in FIG. 20, is a high frequency execution path to compute the PWM period value, operating at a maximum frequency in this embodiment of 500 kHz.

(115) In the lower part of FIG. 20, the on-time for the PWM, T.sub.ON, is calculated from V.sub.OUT, i.e., the current output voltage and the predefined voltage reference V.sub.O,REF. Summing node 46 compares the current output voltage V.sub.OUT with the set point V.sub.O,REF. The resulting error signal is provided to filter/compensator 47, which runs at a relatively low frequency, e.g., 10 Hz, to remove second harmonic components, typically present in the output voltage V.sub.OUT.

(116) The filtered error signal is provided to limiter 48. The limiter 48 provides safety, in particular in a load side short circuit situation. During a short circuit on the output/load side, the ON time of MOSFETs S.sub.N tend to go higher. Limiter 48 limits the maximum on time T.sub.ON, and thus the maximum power, fed to the output. Accordingly, a short circuit situation is safely handled. If both, the input voltage and the on-time are within limits, an over power condition does not arise.

(117) Multiplier 45 receives the correspondingly processed error signal as on-time T.sub.ON and correspondingly provides

(118) $\frac{V_{\mathrm{OUT}}}{\left(V_{\mathrm{OUT}}-V_{\mathrm{IN}}\right)}{T}_{\mathrm{ON}}$
to delay 49 and subsequently to PWM modules PWM.sub.1 as total PWM period time T. The phase of the remaining PWM modules is calculated based on the PWM period time T through a respective phase shift module 54.

(119) T.sub.ON is also directly provided to the PWM modules PWM.sub.N. Using T and T.sub.ON, each PWM module can apply the appropriate PWM timing settings to the respective gates G.sub.N of MOSFETs S.sub.N. In view that the calculation is based upon V.sub.OUT and V.sub.IN, the zero-current point in each PWM cycle reliably determined.

(120) While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. For example, it is possible to operate the invention in an embodiment in which: instead of or in addition to inductor 4, a capacitor is used as an energy storage device; an EMI (electromagnetic interference) filter is included and designed to pass lower frequency components and attenuate the higher frequency components; filter/compensator 47 is a 2P2Z or a PID controller; and/or instead of current sensor ZCD.sub.N comprising a coupled inductor, current sensor ZCD.sub.N comprises a CT or Hall Effect sensor, or a sensing resistor for inductor current measurement and/or diode current measurement.

(121) Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. A single processor, module, or other unit may fulfill the functions of several items recited in the claims.

(122) The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

APPENDIX

(123) The present disclosure relates to power supplies and, more particularly, to digital control of interleaved boundary mode power factor correction (PFC) for reduced crossover distortion

(124) Embodiments of the present disclosure include microcontrollers, systems, integrated circuit devices, and methods for digital control of interleaved boundary mode PFC for reduced crossover distortion. Such PFC may be implemented by any suitable combination of analog circuitry, digital circuitry, instructions for execution by a processor, or combination thereof. Embodiments of the present disclosure may further be implemented in power supplies or controllers for power supplies.

(125) FIG. 1 is an illustration of an example circuit for implementing control of interleaved boundary mode power factor correction (PFC) for reduced crossover distortion.

(126) Boundary mode PFC may include a variable frequency topology wherein the switching frequency is varying over an alternating current (AC) line cycle. The variable frequency may be due to zero-inductor-current PWM switching. The frequency may be primarily dependent on the input voltage, output load, and inductor value. The frequency may be highest near the input voltage zero and lowest near the input voltage peak. An EMI filter may be included and designed to pass lower frequency components and attenuate the higher frequency components. For a fixed load, the higher frequency components near the zero crossing may get attenuated. This may result in the input current distortion near the zero crossing and will lead to lower total harmonic distortion (THD) numbers.

(127) Boundary mode PFC may also include a boost topology, AC input, direct current (DC) output, a single voltage loop, constant ON time, a switch to be turned off at zero current, and, as mentioned above, variable frequency. Embodiments of the present disclosure may reduce crossover distortion. This may lead to achieving a high power factor and lower THD. The embodiments may be highly efficient and better utilize digital control. Moreover, the embodiments may lead to higher power density, with reduced EMI filter size, smaller packaging, and lower cost.

(128) In FIG. 1, in an interleaved multistage boundary mode PFC, the EMI filter may attenuate high frequency components near the zero crossing of the input voltage waveform. This may result in a prolonged zero current situation near the zero crossing, thereby leading to a distorted current waveform. With high power factor, the input current wave shape may be the same as that of the input voltage. Near zero cross, the input voltage and input current levels may be very low. The input current levels may increase with the input voltage and are highest near the peak of the input voltage. The approach taken to solve this issue may involve reducing the number of stages operating near the zero crossing, thereby operating the converter at an increased frequency. The current ripple may tend to get higher with this approach, but will effectively pass through the EMI filter, thereby reducing the zero crossover time. A sudden change in the number of operating stages can affect the control loop and have stability issues. However by changing the gain based on number of converter stages operating, the control loop may be unaffected.

(129) The PFC may include two or more identical sections of boost converters. The boost converters may include an inductor, switch, and diode. The boost converters may convert AC input voltage to DC output voltage. The boundary mode operation may have advantages of higher efficiency and power factor. One of the drawbacks of this topology is the variation in switching frequency over the line cycle. Towards zero crossing of the AC line cycle, the frequency is highest, while the frequency is lowest at the peak.

(130) In one embodiment, a new PWM switching cycle is synchronized with zero inductor current. The zero inductor current instant can be sensed using, for example, a current sensor or coupled inductor, or determined by calculations. As seen in FIG. 1, the input to the circuit is the AC supply of, for example, 10V at 60 Hz or 230V at 50 Hz. The input voltage may be rectified using a bridge rectifier. Furthermore the input voltage may be subsequently fed to one of the boost circuits. Give, for example, N boost stages or converters, each boost stage may be designed to handle a power of P/N, with adequate margins. The input and output capacitors may be common to all the boost stages, and can be lumped or distributed.

(131) FIG. 3 illustrates example, basic input and output waveforms, according to embodiments of the present disclosure.

(132) The zero switching instant for each stage can be determined by using a coupled inductor or inductor current sensing. In both the cases, a comparator within the dsPIC may receive the sensing signal.

(133) FIG. 6 illustrates an algorithm for the interleaved PFC running inside the dsPIC, according to embodiments of the present disclosure. The dsPIC may compute the ON time using a digital filter and the difference between reference output voltage and the actual output voltage. The bandwidth of the output voltage may be kept low to prevent input current distortion. This may lead to a constant ON time over AC line cycle for a given input voltage and output load. The gating pulse to the switch, which may be implemented as a MOSFET, may be HIGH during the ON time and LOW during the OFF time. The PWM cycle may be restarted when the inductor current goes to zero. The ON time for each PWM module may go through two switches. The first switch may control the gain in the system, while the second switch controls the active power stages. The threshold voltage, Vthresh, may be based on the power handling capability of individual stage. When the input voltage is above the threshold voltage Vthresh, all the power stages may be active. The output load is effectively shared by all the N converters, wherein N may be generally a power of 2. When the input voltage is less than Vthresh, the total time may be divided into log 2(N) subdivisions.

(134) FIG. 7 illustrates example voltage waveforms and subdivisions, according to embodiments of the present disclosure. Waveforms and subdivisions may be shown for N=4. There will be two subdivisions for input voltage below Vthresh, referenced as ab and bc, When the input voltage is rising from zero towards the peak (ascending, I), the first subdivision ab may be active. During this time, converter I is active, and the gain selected is N (4). The frequency of converter I may be I/4th of the nominal frequency if all the converters were active. All other converters may be switched off, and only converter I supplies the load current.

(135) FIG. 8 illustrates gate waveforms for the first subdivision ab, according to embodiments of the present disclosure. The operation will continue in this subdivision until the voltage increases beyond Vthresh/2. When the input goes beyond Vthresh/2, the operation may enter subdivision bc. During this time, the converters 1 and 2 may operate at half the nominal frequency and a gain of 2, while converters 3 and 4 are off.

(136) FIG. 9 illustrates gate waveforms for the second subdivision bc, according to embodiments of the present disclosure. When the input voltage exceeds Vthresh, all of the 4 converters may operate with a gain of 1 (II) (or cc). FIG. 8 illustrates gate waveforms and input current ripple for period II, according to embodiments of the present disclosure. In the descending cycle (III), when the input voltage is below Vthresh, the operation may enter subdivision cb. During this time, the converters 3 and 4 may be active with a gain of and twice the nominal frequency, while converters 1 and 2 are off. When the input voltage falls below Vthresh/2, the subdivision ba may become active. During this time, the converter 4 may operate with a frequency of times the nominal frequency and a gain of 4, while other converters are off. In the next half of the input cycle, during the subdivision ab, converter 2 may take the place of converter 1, and converter 3 can take place of converter 4 during subdivision ba. The converters may be interchanged in order to provide uniform stresses to all the converters thereby increasing reliability. The switching sequence for N=4 is provided in FIG. 9, according to embodiments of the present disclosure.

(137) FIGS. 10-13 illustrate screenshots from oscilloscopes or simulations for the operation and performance of the system, according to embodiments of the present disclosure.

(138) Because boundary PFC has a variable switching frequency within a line cycle, achieving the frequency and phase synchronization is difficult with interleaved converters. Embodiments of the present disclosure include switching after the phase and zero current conditions are met in an interleaved converter. Embodiments of the present disclosure do not depend on any complex compensator changes, and manages the power stage change using gain change.

(139) Although particular embodiments have been illustrated in the present disclosure, additions, modifications, subtractions, and other alterations may be made to the example embodiments of the present disclosure without departing from the spirit and teachings of the present disclosure.