Amplification interface, and corresponding measurement system and method for calibrating an amplification interface

Abstract

An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.

Claims

1. An amplification interface, comprising: first and second differential input terminals, wherein the first differential input terminal is configured to receive a measurement sensor current and the second differential input terminal is configured to receive a reference sensor current; first and second differential output terminals, wherein the first differential output terminal is configured to provide a first output voltage, the second differential output terminal is configured to provide a second output voltage, and the first and second output voltages define a differential output signal; a first analog integrator coupled between the first differential input terminal and the first differential output terminal, the first analog integrator being resettable by a reset signal; a second analog integrator coupled between the second differential input terminal and the second differential output terminal, the second analog integrator being resettable by the reset signal; a control circuit configured to: generate the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval; receive a control signal indicative of offsets in the measurement sensor current and the reference sensor current; and generate a drive signal as a function of the control signal; a first current generator configured to couple a first compensation current to the first differential input terminal as a function of the drive signal; and a second current generator configured to couple a second compensation current to the second differential input terminal as a function of the drive signal.

2. The amplification interface of claim 1: wherein the control circuit is further configured to: determine first and second durations as a function of the control signal, wherein a sum of the first and second durations corresponds to a duration of the measurement interval; and during the measurement interval, set the drive signal to a first logic value for the first duration and set the drive signal to a second logic value for the second duration; and wherein the first current generator is configured: when the drive signal has the first logic value, to generate the first compensation current as being positive and the second compensation current as being negative; and when the drive signal has the second logic value, to generate the first compensation circuit as being negative and the second compensation current as being positive.

3. The amplification interface of claim 2: wherein the first current generator comprises: a first current source selectively coupled to source current the first differential input terminal by a first switch controlled by the drive signal; and a second current source selectively coupled to sink current from the first differential input terminal by a second switch controlled by a complement of the drive signal; and wherein the second current generator comprises: a third current source selectively coupled to source current the second differential input terminal by a third switch controlled by the drive signal; and a fourth current source selectively coupled to sink current from the second differential input terminal by a fourth switch controlled by a complement of the drive signal.

4. The amplification interface of claim 1: wherein the first analog integrator comprises: a first operational amplifier having a non-inverting input coupled to a reference voltage, an inverting input coupled to the first differential input terminal, and an output coupled to the first differential output terminal; a first feedback capacitor coupled between the inverting input and the output of the first operational amplifier; and a first switch coupled between the inverting input and the output of the first operational amplifier, the first switch being controlled by the reset signal; and wherein the second analog integrator comprises: a second operational amplifier having an inverting input coupled to the reference voltage, a non-inverting input coupled to the second differential input terminal, and an output coupled to the second differential output terminal; a second feedback capacitor coupled between the non-inverting input and the output of the second operational amplifier; and a second switch coupled between the non-inverting input and the output of the second operational amplifier, the second switch being controlled by the reset signal.

5. The amplification interface of claim 1, wherein the control circuit comprises a counter circuit configured to generate the reset signal synchronously in response to a clock signal.

6. The amplification interface of claim 5, wherein the measurement interval corresponds to an even number of 2N sub-intervals, with a duration of each sub-interval corresponding to a multiple of a period of the clock signal, with N being an integer corresponding to a number of current generators in the amplification interface.

7. The amplification interface of claim 6, wherein the control circuit is configured to determine said the first duration, T.sub.4, and the second duration, T.sub.5, as: $T_4=\frac{T_2}{2}-\mathrm{COMP}\frac{T_2}{2N}$ $T_5=\frac{T_2}{2}+\mathrm{COMP}\frac{T_2}{2N}$ where T.sub.2 is the duration of the measurement interval, and COMP is an integer between −N and +N and corresponds to the control signal.

8. The amplification interface of claim 1, further comprising a sample-and-hold circuit controlled by a sampling control signal and configured to store the differential output signal.

9. The amplification interface of claim 8, wherein the sample-and-hold circuit is configured to store the differential output signal in response to the sampling control signal having a first logic value and to maintain storage of the differential output signal in response to the sampling control signal having a second logic value.

10. The amplification interface of claim 1, further comprising a calibration circuit comprising: a sensor connected to the first and second differential input terminals of said amplification interface; a first circuit configured to monitor, at an end of said measurement interval, the differential output signal; and a second circuit configured to vary said control signal such that said monitored differential output signal corresponds to a reference voltage.

11. An amplification interface, comprising: first and second differential input terminals, wherein the first differential input terminal is coupled to a current indicative of a quantity measured by a first sensor, and the second differential input terminal is coupled to a reference current indicative of a reference quantity measured by a second sensor; first and second differential output terminals; a first current generator configured to couple a first compensation current to the first differential input terminal; a second current generator configured to couple a second compensation current to the second differential input terminal; a first analog integrator coupled between the first differential input terminal and the first differential output terminal, the first analog integrator comprising a first operational amplifier having a non-inverting input connected to a reference voltage, an inverting input connected to the first differential input terminal, and an output coupled to the first differential output terminal; a second analog integrator coupled between the second differential input terminal and the second differential output terminal, the second analog integrator comprising a second operational amplifier having an inverting input connected to the reference voltage, a non-inverting input connected to the second differential input terminal, and an output coupled to the second differential output terminal; a sample-and-hold circuit connected between the outputs of the first and second analog integrators and the first and second differential output terminals; and a control circuit configured to control the first and second current generators, first and second analog integrators, and sample-and-hold circuit.

12. The amplification interface of claim 11: wherein the first analog integrator also includes: a first feedback capacitor coupled between the inverting input and output of the first operational amplifier; and a first switch coupled between the inverting input and output of the first operational amplifier; and wherein the second analog integrator also includes: a second feedback capacitor coupled between the inverting input and output of the second operational amplifier; and a second switch coupled between the inverting input and output of the second operational amplifier.

13. The amplification interface of claim 11: wherein the first current generator comprises: a first current source selectively coupled to the first differential input terminal by a first switch; and a second current source selectively coupled to the first differential input terminal by a second switch; and wherein the second current generator comprises: a third current source selectively coupled to the second differential input terminal by a third switch; and a fourth current source selectively coupled to the second differential input terminal by a fourth switch.

14. An amplification interface, comprising: a first analog integrator having an input receiving a measurement sensor current, wherein the first analog integrator is configured to be reset or activated in response to a reset signal; a second analog integrator having an input receiving a reference sensor current, wherein the second analog integrator is configured to be reset or activated in response to the reset signal; a first current generator having an output connected to the input of the first analog integrator, wherein the first current generator is configured to generate a first compensation current as a function of a drive signal; a second current generator having an output connected to the input of the second analog integrator, wherein the second current generator is configured to generate a second compensation current as a function of a complement of the drive signal; a control circuit configured to: generate the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval; and generate the drive signal based upon an offset in the sensor current and the reference sensor current; wherein the current generator is further configured to generate a first current or a second current based upon a logic value of the drive signal; and wherein the control circuit is configured to: determine a first duration and a second duration, wherein a sum of the first duration and the second duration corresponds to a duration of the measurement interval; and during the measurement interval, set the drive signal to a first logic value for the first duration and set the drive signal to a second logic value for the second duration.

15. The amplification interface according to claim 14, wherein the control circuit is configured to generate the reset signal and the drive signal via a counter circuit in a synchronous manner in response to a clock signal.

16. The amplification interface according to claim 15, wherein the measurement interval corresponds to an even number of 2N sub-intervals, wherein a duration of each sub-interval corresponds to a multiple of a period of the clock signal, with N being an integer corresponding to a number of current generators in the amplification interface.

17. The amplification interface according to claim 16, wherein the control circuit is configured to determine the first duration, T.sub.4, and the second duration, T.sub.5, as: $T_4=\frac{T_2}{2}-COMP\frac{T_2}{2N}{T}_5=\frac{T_2}{2}-COMP\frac{T_2}{2N}$ where T.sub.2 is the duration of the measurement interval, and COMP is an integer number between −N and +N and corresponding to a control signal indicative of an offset in the sensor current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:

(2) FIG. 1 shows a measurement system;

(3) FIG. 2 shows an example of an amplification interface;

(4) FIG. 3 shows a first example of an offset compensation for the amplification interface of FIG. 2;

(5) FIG. 4 shows a second example of an offset compensation for the amplification interface of FIG. 2;

(6) FIG. 5 shows an embodiment of an offset compensation for the amplification interface of FIG. 2;

(7) FIGS. 6 and 7 show embodiments of driving of the amplification interface of FIG. 5; and

(8) FIG. 8 shows another embodiment of an offset compensation for the amplification interface of FIG. 2.

DETAILED DESCRIPTION

(9) In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

(10) Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is contained in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(11) The references used herein are provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(12) In FIGS. 5 to 7 described below, parts, elements or components that have already been described with reference to FIGS. 1 to 4 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

(13) As explained previously, various embodiments of the present description regard an electronic amplification interface for a sensor 10, in particular a sensor 10 configured for supplying a measurement current signal representing a quantity to be measured. FIG. 5 shows a first embodiment of an electronic amplification interface according to the present description.

(14) In particular, in the embodiment considered, the electronic amplification interface comprises an input terminal IN for receiving an input current UN, and an output terminal OUT for supplying an output voltage V.sub.out. Consequently, in line with what has been described with reference to FIG. 1, the input terminal IN may be connected to a sensor 10, and the terminal OUT may be connected to an A/D converter 30 or directly to a processing circuit 40. In general, the amplification interface and the A/D converter 30 and/or the processing circuit 40 may even be integrated in a single integrated circuit.

(15) In the embodiment considered, the electronic amplification interface comprises an analog integrator 20. Operation of such an analog integrator 20 has already been described with reference to FIG. 2 and the corresponding description applies entirely.

(16) In general, the analog integrator 20 comprises an input connected (for example, directly) to the input terminal IN, and an output that supplies the output voltage V.sub.out. In particular, the analog integrator 202 is configured for supplying a voltage V.sub.out representing the integral of the current i.sub.INT received at input to the analog integrator 20.

(17) For example, in the embodiment considered, the analog integrator 20 is implemented with: an operational amplifier 202, where a first input terminal of the operational amplifier 202 (typically the negative terminal) is connected to the input of the analog integrator 20, i.e., the terminal IN, and the second input terminal of the operational amplifier 202 (typically the positive terminal) is connected to a reference voltage Vref; and a capacitor Cfb, connected (for example, directly) between the first input terminal of the operational amplifier 202 and the output terminal of the operational amplifier 202.

(18) Hence, in the embodiment considered, the analog integrator 202 is configured for charging the capacitor Cfb as a function of the current i.sub.INT received at the input of the analog integrator 20. In addition, since the output voltage V.sub.out corresponds to the sum of the reference voltage Vref (which is constant and may even be zero) and the voltage across the capacitor Cfb, the output voltage V.sub.out is directly linked to the integral of the current i.sub.INT.

(19) In the embodiment considered, the analog integrator further comprises a reset circuit, configured for selectively discharging the capacitor Cfb. For example, in the embodiment considered, the reset circuit is implemented with an electronic switch SW.sub.RST connected in parallel to the capacitor Cfb.

(20) In various embodiments, the analog integrator may also comprise a sample-and-hold circuit 80. In particular, this circuit represents an analog memory configured for storing the value of the voltage V.sub.out as a function of a control signal SAMPLE. For example, in the simplest case, such a circuit 80 may be implemented with a capacitor, which is selectively connected, for example through one or more electronic switches, to the voltage V.sub.out as a function of the signal SAMPLE.

(21) For instance, for this purpose, the reset signal RST and the signal SAMPLE are generated by a single control circuit 70, which sets the reset signal RST in a first time interval T.sub.1 at a first logic level (typically high) for resetting the analog integrator and in a second time interval T.sub.2 at a second logic level (typically low) for activating the analog integrator. Consequently, the interval T.sub.2 represents a measurement interval that corresponds to the period of integration used by the analog integrator 20. In various embodiments, the time intervals T.sub.1 and T.sub.2 are constant.

(22) In general, on the basis of the implementation of the circuit 80, the signal SAMPLE may also correspond to the reset signal RST or to its inverted version. However, preferably, the control circuit 70 is configured for generating the signal SAMPLE so as to cause sampling of the voltage V.sub.out through the circuit 80 before the reset signal RST is set for discharging the capacitor Cfb; i.e., with respect to activation of the analog integrator 20 (switching of the signal RST from the second logic level to the first level), the signal SAMPLE is set after an interval T.sub.3, which is shorter than the interval T.sub.2, i.e., T.sub.3<T.sub.2.

(23) In the embodiment considered, the electronic amplification interface further comprises a current generator 50a. In particular, in various embodiments, the current generator 50a comprises an output for supplying a current i.sub.COMP, where the output of the current generator 50a is connected to the input terminal IN, i.e., the input of the analog integrator 20. Consequently, the current i.sub.INT received at input to the analog integrator 20 corresponds to:

(24) $\begin{array}{cc}{i}_{\mathrm{INT}}=i_{COMP}+i_{\mathrm{IN}}& \left(3\right)\end{array}$

(25) In various embodiments, the current generator 50a is configured for generating the current i.sub.COMP as a function of at least one control signal. For example, in the embodiment considered, a single control signal SW is used, where the current generator 50a is configured for supplying: a positive current i.sub.COMP=i.sub.1, with i.sub.1>0, when the control signal SW has a first logic level; and a negative current i.sub.COMP=i.sub.2, with i.sub.2<0, when the control signal SW has a second logic level.

(26) For example, in the embodiment considered, the current generator 50a comprises: a first current generator 52 configured for supplying the current i.sub.1; a first electronic switch 54 configured for connecting the first current generator 52 to the output of the current generator 50a, i.e., to the input of the integrator 20, when the control signal SW has the first logic level; a second current generator 58 configured for supplying the current i.sub.2; and a second electronic switch 56 configured for connecting the second current generator 52 to the output of the current generator 50a, i.e., to the input of the integrator 20, when the control signal SW has the second logic level.

(27) Consequently, in the embodiment considered, the current generator 50a supplies alternatively the current i.sub.1 or i.sub.2 as a function of the control signal SW. In various embodiments, the currents i.sub.1 or i.sub.2 have the same amplitude but opposite sign, i.e., i.sub.1=−i.sub.2. In addition, in various embodiments, the currents i.sub.1 and i.sub.2 are constant.

(28) Hence, as compared to the approach described with reference to FIG. 4, the current generator 50a supplies two possible current levels. Instead, in FIG. 4, the current generator 50 supplies N levels both for positive currents and for negative currents. Hence, apparently, the approach shown in FIG. 5 presents a considerably lower resolution. However, as will be explained herein, the present approach enables calibration of the offset with a high resolution of correction (and hence a low residual error) and without requiring the use of low unit currents.

(29) In particular, as described previously, the current generator 50a has a single branch configured for supplying a positive current (i.sub.1) or a negative current (i.sub.2). Preferably, the currents have the same amplitude, denoted hereinafter by IFS, which represents the full-scale current value, i.e., the maximum offset current that can be corrected.

(30) The main difference from the solution shown in FIG. 4 lies in the fact that the current i.sub.COMP supplied by the current generator is not set at a fixed value, but the control signal SW is used for switching the current i.sub.COMP supplied by the current generator between the values i.sub.1/IFS and i.sub.2/−IFS in such a way as to reach on average (for each measurement interval) a required value.

(31) For this purpose, the control circuit 70 is also configured for generating the control signal SW for the current generator 50a in such a way as to synchronize the control signal SW with switching of the reset signal RST for the analog integrator 20.

(32) FIG. 6 shows possible operation of the control circuit 70.

(33) In particular, as explained previously, the control circuit 70 generates the reset signal RST; in particular the control circuit 70 is configured for repeating periodically the following operations: at an instant t.sub.0, the signal RST is set at a first logic level (high) for resetting the analog integrator 20; and at an instant t.sub.1, the signal RST is set at a second logic level (low), thus determining the end of the reset step, whereas the signal SAMPLE is set at a logic level (high), thus determining start of the integration step.

(34) Consequently, the time interval between the instants t.sub.0 and t.sub.1 corresponds to the reset interval T.sub.1, whereas the time interval between the instant t.sub.1 and the subsequent instant t.sub.0′ corresponds to the measurement interval T.sub.2. In various embodiments, between the instant t.sub.0 and t.sub.1 the signal SW is set at the first logic level (high).

(35) In the embodiment considered, also an example of the signal SAMPLE is shown. In particular, as explained previously, the signal SAMPLE stores the value of the voltage V.sub.out before the analog integrator 20 is reset. For example, for this purpose, the signal SAMPLE can be set with respect to start of the measurement interval T.sub.2 (i.e., with respect to the instant t.sub.1) for a sampling time T.sub.3 at a first logic value, in which the circuit 80 stores the value of the signal V.sub.out, and for a hold time (T.sub.2-T.sub.3) it does not store the value of the signal V.sub.out and holds the value stored at the end of the interval T.sub.3. Consequently, to enable a comparison of different measured values, the duration of the measurement interval T.sub.2 is not particularly important, but the sampling time T.sub.3 should be constant.

(36) As explained previously, the control circuit 70 also generates the control signal SW for the current generator 50a. In particular, during each measurement interval T.sub.2, the control circuit 70 sets the signal SW at the first logic level (generation of the current i.sub.1/IFS) for an interval T.sub.4 and at the second logic level (generation of the current i.sub.2/−IFS) for an interval T.sub.5=T.sub.2−T.sub.4. In general, switching during the reset interval T.sub.1 is not particularly important, since the analog integrator is de-activated during this step.

(37) Consequently, the control signal SW is characterized in that (within each integration period T.sub.2) it activates the current i.sub.1/IFS for an interval T.sub.4 and activates the current i.sub.2/−IFS for an interval T.sub.5.

(38) In particular, in the embodiment shown in FIG. 6, a single interval T.sub.4 is used at start of the measurement interval T.sub.2, and a single interval T.sub.5 is used at the end of the measurement interval T.sub.2. Instead, FIG. 7 shows an embodiment in which the time interval T.sub.4 and the time interval T.sub.5 are obtained by a plurality of sub-intervals that have the total durations T.sub.4 and T.sub.5, respectively.

(39) Consequently, in the embodiment considered, the time interval T.sub.2 can be divided into an even number of sub-intervals, referred to hereinafter as 2N, i.e., each sub-interval has a duration T.sub.2/(2N).

(40) For example, in various embodiments, the control circuit 70 generates the reset signal RST using a counter/timer 702 configured for incrementing a count value as a function of a clock signal CLK (see also FIG. 5) and for setting the logic level of the reset signal RST by comparing the count value with at least one threshold that identifies the duration of the measurement interval T.sub.2. Consequently, in this case, the period T.sub.CLK of the clock signal CLK corresponds to the minimum duration of each of the 2N sub-intervals. However, in general, each sub-interval may also have a duration T.sub.2/(2N) that corresponds to a multiple of the time T.sub.CLK.

(41) Hence, the duration T.sub.4 may be determined by a control signal COMP that identifies the number of sub-intervals during which the control signal SW should have the first logic level, i.e.:

(42) $\begin{array}{cc}{T}_4=COMP\frac{T_2}{2N}& \left(4\right)\end{array}$
Instead, the duration T.sub.5 can be calculated from the duration T.sub.4; namely:

(43) $\begin{array}{cc}{T}_5=T_2-COMP\frac{T_2}{2N}& \left(5\right)\end{array}$
In general, when the sensor 10 does not comprise any offset, for example, in the absence of a sensor 10 connected to the input terminal IN of the electronic amplification interface, the time interval T.sub.5 corresponds to the duration T.sub.4, i.e.:

(44) $\begin{array}{cc}{T}_5=T_4=\frac{T_2}{2}& \left(6\right)\end{array}$

(45) Consequently, in various embodiments, the duration T.sub.2/2 may correspond to a default duration, and the signal COMP may also indicate the number of sub-intervals by which this default duration may be increased or decreased; for example:

(46) $\begin{array}{cc}{T}_4=\frac{T_2}{2}-COMP\frac{T_2}{2N}& \left(7\right)\\ T_5=\frac{T_2}{2}+\mathrm{COMP}\frac{T_2}{2N}& \left(8\right)\end{array}$

(47) For instance, in the case where the signal COMP has the value −N, T.sub.4 is equal to T.sub.2, and T.sub.5 is zero. Instead, in the case where the signal COMP has the value +N, T.sub.4 is zero, and T.sub.5 is equal to T.sub.2. In any case, typically the durations T.sub.4 and T.sub.5 are not zero.

(48) In various embodiments, the output voltage V.sub.out may hence correspond to:

(49) $\begin{array}{cc}{V}_{out}=-\frac{I_{FS}}{\mathrm{Cfb}}{T}_4+\frac{I_{FS}}{\mathrm{Cfb}}{T}_5+\frac{\mathrm{ID}1}{\mathrm{Cfb}}{T}_2& \left(9\right)\end{array}$

(50) For example, using the definition of the signal COMP appearing in Eqs. (7) and (8), the output voltage V.sub.out corresponds to:

(51) 0$\begin{array}{cc}{V}_{out}=-\frac{T_2}{\mathrm{Cfb}}\left(i_{\mathrm{FS}}\frac{\mathrm{COMP}}{N}+\mathrm{ID}1\right)& \left(10\right)\end{array}$

(52) From a mathematical standpoint, the result of Eq. (9) is hence equal to the result of Eq. (2); i.e., the system proposed is able to provide the same correction as the system shown in FIG. 4. Also in this case, the control word COMP is an integer (comprised between −N and +N). Hence, in a way similar to what has been described with reference to FIG. 4, the offset current can be corrected within a range between −I.sub.FS and +I.sub.FS with a correction resolution equal to I.sub.FS/N. The residual error deriving from offset correction may be comprised between −0.5.Math.(I.sub.FS/N) and 0.5.Math.(I.sub.FS/N), and this residual error may lead to an output signal that may not be zero after offset calibration but may be comprised between −0.5.Math.(T.sub.2/Cfb).Math.(I.sub.FS/N) and 0.5.Math.(T.sub.2/Cfb).Math.(I.sub.FS/N).

(53) However, whereas the approach shown in FIG. 4 is based on a plurality of current generators that use a high precision, the present approach is based upon switching in time, which can be controlled more easily. If, for example, (T.sub.2/Cfb)=100.Math.10.sup.6 and the residual error from the correction is to be limited at +/−0.05 V, assuming that the current I.sub.FS is 100 nA, then the number N should be equal to 100.

(54) There is thus overcome the main limit of the approach shown in FIG. 4, where to reduce further the residual error from the offset correction, the road is to decrease the unit current of the branch of the DAC (I.sub.FS/N). In the approach proposed, to increase the resolution it is sufficient to increase the number of sub-intervals of the signal SW, and this can be easily obtained considering a clock frequency CLK that is sufficiently high for obtaining the desired resolution.

(55) As shown in FIG. 5, in the calibration step and in the absence of signal applied, the word COMP can be chosen and fixed to the value that renders Eq. (8) as close as possible to zero. For example, in the embodiments shown in FIG. 5, a circuit 90 is configured for measuring the output voltage V.sub.out and for varying the signal COMP. In general, this circuit 90 may be implemented as a circuit that is external to the amplification interface or may also be integrated in the amplification interface. For example, for this purpose, it is possible to use the processing circuit 40, which could also implement the control circuit 70 directly.

(56) While the approach has been described with reference to a sensor 10 that supplies a current signal of the single-ended type, the approach could be used also when the sensor supplies a current signal of a differential type. For example, as shown in FIG. 8 the sensor 10 can supply such a differential signal when in actual fact the sensor itself comprises two such sensors: a first sensor 10 that supplies a first current, where the first sensor is exposed to the quantity to be measured; and a second sensor 10ref that supplies a second current, where the second sensor is not exposed to the quantity to be measured; i.e., the sensor represents a reference sensor.

(57) In this case, as shown in FIG. 8, the circuit shown in FIG. 5 can hence be doubled so that the first circuit 100 is used for the first sensor 10 and the second circuit 101 is used for the second sensor 10ref, and the output signal may correspond to the voltage V.sub.OUT+, V.sub.OUT− between the output terminals OUT+ and OUT− of the two circuits 100 and 101. Alternatively, it is also possible to use directly a differential current integrator as described, for example, in the paper by A. Youssef, Mohamed & Soliman, A. M., “A Novel CMOS Realization of the Differential Input Balanced Output Current Operational Amplifier and its Applications”, Analog Integrated Circuits and Signal Processing 44(1):37-53, July 2005, DOI: 10.1007/s10470-005-1613-2 (incorporated by reference).

(58) The claims form an integral part of the technical teaching of the description provided herein.

(59) Of course, without prejudice to the principles described herein, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of this disclosure as defined by the ensuing claims.