Modulation agnostic digital hybrid mode power amplifier system and method

Abstract

A RF-digital hybrid mode power amplifier system for achieving high efficiency and high linearity in wideband communication systems is disclosed. The present invention is based on the method of adaptive digital predistortion to linearize a power amplifier in the RF domain. The present disclosure enables a power amplifier system to be field reconfigurable and support multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels. As a result, the digital hybrid mode power amplifier system is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems, where baseband I-Q signal information is not readily available.

Claims

1. A digital predistortion system for linearizing the output of power amplifiers comprising: input signal suitable for wireless communications; at least one power amplifier for outputting an amplified signal; at least one feedback signal derived from the amplified signal including a representation of a noise characteristic of the at least one power amplifier; estimator logic responsive to the at least one feedback signal for generating predistortion coefficients a.sub.ij, based at least in part on feedback path delay determined from the correlation given by the equation $c\left(m\right)=\underset{i=0}{\overset{N-1}{.Math.}}\mathrm{sign}\left(.Math.x\left(i+1\right).Math.-.Math.x\left(i\right).Math.\right)\mathrm{sign}\left(.Math.y\left(i+m+1\right).Math.-.Math.y\left(i+m\right).Math.\right)$ where C(m) is a correlation function, x(n) represents transmission data, y(n) represents feedback data, c(m) is a correlation function, N is a number of data per block, m is a variable representing time, i is a counter for summation, and n(delay) is a delay determined by the value of m where C(m) is maximized; and digital predistortion logic for predistorting the input signal and for supplying a predistorted signal to the at least one power amplifier, wherein the digital predistortion logic complies with the equation: $z\left(n\right)=\underset{i=0}{\overset{n-1}{.Math.}}{x}_t\left(n-i\right)\left(\underset{j=0}{\overset{k-1}{.Math.}}{a}_{\mathrm{ij}}{.Math.x_t\left(n-i\right).Math.}^j\right)$ where z(n) is a predistortion function, n is a variable representing time, x.sub.t is the input signal, i and j are counters for summation, and a.sub.ij are the predistortion coefficients determined by the estimator logic.

2. The digital predistortion system of claim 1 configured for base station applications further comprising a digital field programmable gate array that includes one or more of a digital up-converter, a crest factor reduction, a predistorter, or a digital quadrature modulator.

3. The digital predistortion system of claim 1 configured for repeater applications further comprising a digital field programmable gate array that includes at least one of a digital quadrature demodulator, a crest factor reduction, a predistorter, or a digital quadrature modulator.

4. The digital predistortion system of claim 1 further comprising a digital field programmable gate array that provides predistortion that compensates adaptively for both nonlinearity and memory effects by generating asymmetric distortion of the power amplifier.

5. The digital predistortion system of claim 1 further comprising a digital field programmable gate array that includes an adaptation algorithm to determine the optimum gate bias voltage of the power amplifier for stabilizing the linearity fluctuations due to the temperature changes of the power amplifier.

6. The digital predistortion system of claim 1 wherein the at least one power amplifier uses at least one of the following efficiency boosting techniques: Doherty, Envelope Elimination and Restoration, Envelope Tracking, Envelope Following, or Linear amplification using Nonlinear Components in order to maximize the efficiency of the power amplifier system.

7. A digital predistortion method for linearizing the output of power amplifiers comprising: receiving an input signal suitable for wireless communications, amplifying the input signal using at least one power amplifier, deriving at least one feedback signal from the amplified signal including a representation of a noise characteristic of the at least one power amplifier, generating predistortion coefficients a.sub.ij, using estimator logic responsive to the at least one feedback signal based at least in part on feedback path delay determined from the correlation given by the equation $c\left(m\right)=\underset{i=0}{\overset{N-1}{.Math.}}\mathrm{sign}\left(.Math.x\left(i+1\right).Math.-.Math.x\left(i\right).Math.\right)\mathrm{sign}\left(.Math.y\left(i+m+1\right).Math.-.Math.y\left(i+m\right).Math.\right)$ where C(m) is a correlation function, x(n) represents transmission data, y(n) represents feedback data, c(m) is a correlation function, N is a number of data per block, m is a variable representing time, I is a counter for summation, and n(delay) is a delay determined by the value of m where C(m) is maximized; and predistorting the input signal and supplying a predistorted signal to the at least one power amplifier, wherein the predistorting complies with the equation: $z\left(n\right)=\underset{i=0}{\overset{n-1}{.Math.}}{x}_t\left(n-i\right)\left(\underset{j=0}{\overset{k-1}{.Math.}}{a}_{\mathrm{ij}}{.Math.x_t\left(n-i\right).Math.}^j\right)$ where z(n) is a predistortion function, n is a variable representing time, x.sub.t is the input signal, i and j are counters for summation, and a.sub.ij are the predistortion coefficients determined by the estimator logic.

8. The digital predistortion method of claim 7 further comprising providing predistortion that compensates adaptively for both nonlinearity and memory effects by generating asymmetric distortion of the power amplifier using a digital field programmable gate array.

9. The digital predistortion method of claim 7 further comprising determining the optimum gate bias voltage of the power amplifier for stabilizing the linearity fluctuations due to the temperature changes of the power amplifier using an adaptation algorithm of a digital field programmable gate array.

10. The digital predistortion method of claim 7 wherein the at least one power amplifier uses at least one of the following efficiency boosting techniques: Doherty, Envelope Elimination and Restoration, Envelope Tracking, Envelope Following, or Linear amplification using Nonlinear Components in order to maximize the efficiency of the power amplifier system.

11. The digital predistortion method of claim 7 configured for base station applications further comprising digitally upconverting the input signal, reducing crest factor of the input signal, predistorting the input signal, or modulating the input signal.

12. The digital predistortion method of claim 7 configured for repeater applications further comprising demodulating the input signal, reducing crest factor of the input signal, predistorting the input signal, or modulating the input signal.

Description

THE FIGURES

(1) Further objects and advantages of the present invention can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which:

(2) FIG. 1 is a block diagram showing the basic form of a digital hybrid mode power amplifier system.

(3) FIG. 2 is a block diagram showing a simple digital predistortion block diagram for a power amplifier system according to one embodiment of the present invention.

(4) FIG. 3 is a block diagram showing polynomial-based predistortion in a digital hybrid mode power amplifier system of the present invention.

(5) FIG. 4 is a block diagram of the digital predistortion algorithm applied for self-adaptation in a digital hybrid mode power amplifier system of the present invention.

(6) FIG. 5 is a delay estimation block diagram of the present invention.

(7) FIG. 6 is a block diagram of a fractional delay for the present invention.

(8) FIG. 7 is a block diagram showing a digital hybrid mode power amplifier system implemented with a down converter (DNC) and UPC-based clipping error restoration path according to another embodiment of the present invention.

(9) FIG. 8 is a block diagram showing a digital hybrid mode power amplifier system implemented with a DNC and an analog quadrature modulator (AQM) according to another embodiment of the present invention.

(10) FIG. 9 is a block diagram showing an embodiment of the analog quadrature modulator compensation structure.

GLOSSARY

(11) The acronyms used herein have the following meanings: ACLR Adjacent Channel Leakage Ratio ACPR Adjacent Channel Power Ratio ADC Analog to Digital Converter AQDM Analog Quadrature Demodulator AQM Analog Quadrature Modulator AQDMC Analog Quadrature Demodulator Corrector AQMC Analog Quadrature Modulator Corrector BPF Bandpass Filter CDMA Code Division Multiple Access CFR Crest Factor Reduction DAC Digital to Analog Converter DET Detector DHMPA Digital Hybrid Mode Power Amplifier DDC Digital Down Converter DNC Down Converter DPA Doherty Power Amplifier DQDM Digital Quadrature Demodulator DQM Digital Quadrature Modulator DSP Digital Signal Processing DUC Digital Up Converter EER Envelope Elimination and Restoration EF Envelope Following ET Envelope Tracking EVM Error Vector Magnitude FFLPA Feedforward Linear Power Amplifier FIR Finite Impulse Response FPGA Field-Programmable Gate Array GSM Global System for Mobile communications I-Q In-phase/Quadrature IF Intermediate Frequency LINC Linear Amplification using Nonlinear Components LO Local Oscillator LPF Low Pass Filter MCPA Multi-Carrier Power Amplifier MDS Multi-Directional Search OFDM Orthogonal Frequency Division Multiplexing PA Power Amplifier PAPR Peak-to-Average Power Ratio PD Digital Baseband Predistortion PLL Phase Locked Loop QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency SAW Surface Acoustic Wave Filter UMTS Universal Mobile Telecommunications System UPC Up Converter WCDMA Wideband Code Division Multiple Access WLAN Wireless Local Area Network

DETAILED DESCRIPTION OF THE INVENTION

(12) The present invention is a novel RF-out PA system that utilizes an adaptive digital predistortion algorithm. The present invention is a hybrid system of digital and analog modules. The interplay of the digital and analog modules of the hybrid system both linearize the spectral regrowth and enhance the power efficiency of the PA while maintaining or increasing the wide bandwidth. The present invention, therefore, achieves higher efficiency and higher linearity for wideband complex modulation carriers.

(13) FIG. 1 is a high level block diagram showing the basic system architecture which can be thought of, at least for some embodiments, as comprising digital and analog modules and a feedback path. The digital module is the digital predistortion controller 101 which comprises the PD algorithm, other auxiliary DSP algorithms, and related digital circuitries. The analog module is the main power amplifier 102, other auxiliary analog circuitries such as DPA, and related peripheral analog circuitries of the overall system. The present invention is a black box, plug-and-play type system because it accepts RF modulated signal 100 as its input, and provides a substantially identical but amplified RF signal 103 as its output, therefore, it is RF-in/RF-out. Baseband input signals can be applied directly to the Digital Predistorter Controller according to one embodiment of the present invention. An Optical input signal can be applied directly to the Digital Predistorter Controller according to one embodiment of the present invention. The feedback path essentially provides a representation of the output signal to the predistortion controller 101. The present invention is sometimes referred to as a digital hybrid mode power-amplifier (DHMPA) system hereinafter.

(14) Digital Predistorter Algorithm

(15) Digital Predistortion (DPD) is a technique to linearize a power amplifier (PA). FIG. 2 shows in block diagram form an embodiment of a linear digitally predistorted PA. In the DPD block, a memory polynomial model is used as the predistortion function (FIG. 3), and complies with the formula:

(16) $z\left(n\right)=\underset{i=0}{\overset{n-1}{.Math.}}{x}_i\left(x-i\right)\left(\underset{j=0}{\overset{k-1}{.Math.}}{a}_{\mathrm{ij}}{.Math.x_i\left(n-i\right).Math.}^j\right)$
where a.sub.ij are the DPD coefficients.

(17) In the DPD estimator block, a least square algorithm is utilized to find the DPD coefficients, and then transfer them to DPD block. The detailed DPD algorithm is shown in FIG. 4.

(18) FIG. 3 is a block diagram showing a predistortion (PD) part in the DHMPA system of the present invention. The PD in the present invention generally utilizes an adaptive polynomial-based digital predistortion system. Another embodiment of the PD utilizes a LUT-based digital predistortion system. More specifically, the PD illustrated in FIG. 3 and in embodiments disclosed in FIG. 7 and FIG. 8, discussed below, are processed in the digital processor by an adaptive algorithm, presented in U.S. patent application Ser. No. 11/961,969, entitled A Method for Baseband Predistortion Linearization in Multi-Channel Wideband Communication Systems. The PD for the DHMPA system in FIG. 3 has multiple finite impulse response (FIR) filters, that is, FIR1 301, FIR2 303, FIR 305, and FIR4 307. The PD also contains the third order product generation block 302, the fifth order product generation block 304, and the seventh order product generation block 306. The output signals from FIR filters are combined in the summation block 308. Coefficients for multiple FIR filters are updated by the digital predistortion algorithm.

(19) Delay Estimation Algorithm:

(20) The DPD estimator compares x(n) and its corresponding feedback signal y(nd) to find the DPD coefficients, where d is the delay of the feedback path. As the feedback path delay is different for each PA, this delay should be identified before the signal arrives at the coefficient estimation. In this design, the amplitude difference correlation function of the transmission, x(n), and feedback data, y(n), is applied to find the feedback path delay. The correlation is given by

(21) $C\left(m\right)=\underset{i=0}{\overset{N-1}{.Math.}}\mathrm{sign}\left(.Math.x\left(i+1\right).Math.-.Math.x\left(i\right).Math.\right)\mathrm{sign}\left(.Math.y\left(i+m+1\right).Math.-.Math.y\left(i+m\right).Math.\right)$
The delay n that maximizes the correlation C(m) is the feedback path delay. The delay estimation block is shown in FIG. 5.

(22) Since the feedback path goes through analog circuitry, the delay between the transmission and feedback path could be a fractional sample delay. To synchronize the signals more accurately, fractional delay estimation is necessary. To simplify the design, only a half-sample delay is considered in this design, as shown in FIG. 6. It will be appreciated that smaller fractional delays can also be utilized in at least some embodiments.

(23) To get the half-sample delay data, an upsampling approach is the common choice, but in this design, in order to avoid a very high sampling frequency in the FPGA, an interpolation method is used to get the half-sample delay data. The data with integer delay and fractional delay are transferred in parallel. The interpolation function for fractional delay is

(24) $y\left(n\right)=\underset{i=0}{\overset{3}{.Math.}}{c}_{i}x\left(n+i\right)$
in which c.sub.i is the weight coefficient.

(25) Whether the fractional delay path or the integer delay path will be chosen is decided by the result of the amplitude difference correlator. If the correlation result is odd, the integer path will be chosen, otherwise the fractional delay path will be chosen.

(26) Phase Offset Estimation and Correction Algorithm:

(27) Phase offset between the transmission signal and the feedback signal exists in the circuit. For a better and faster convergence of the DPD coefficient estimation, this phase offset should be removed.

(28) The transmission signal x(n) and feedback signal y(n) can be expressed as
x(n)=|x(n)|e.sup.j.sup.x and y(n)=|y(n)|e.sup.j .sup.y,
The phase offset e.sup.j(x-y) can be calculated through

(29) $e^{j\left({}_x-y\right)}=\frac{x\left(n\right){y\left(n\right)}^{*}}{.Math.x\left(n\right).Math..Math.y\left(n\right).Math.}$
So, the phase offset between the transmission and feedback paths is

(30) $e^{jo,}=\mathrm{mean}\left(\frac{x\left(n\right){y\left(n\right)}^{*}}{.Math.x\left(n\right).Math..Math.y\left(n\right).Math.}\right)$
The feedback signal with the phase offset removed can be calculated by
y(n)=y(n)e.sup.jo

(31) Magnitude Correction:

(32) As the gain of the PA may change slightly, the feedback gain should be corrected to avoid the error from the gain mismatch. The feedback signal is corrected according to the function

(33) $\stackrel{\_}{y}\left(n\right)=y\left(n\right)\frac{\underset{i=1}{\overset{N}{.Math.}}.Math.x\left(i\right).Math.}{\underset{i=1}{\overset{N}{.Math.}}.Math.y\left(i\right).Math.}$
In this design, N is chosen to be 4096. The choice of N will depend on the desired accuracy.

(34) QR_RLS Adaptive Algorithm:

(35) The least square solution for DPD coefficient estimation is formulated as

(36) $F\left(x\left(n\right)\right)=y\left(n\right)$$F\left(x\left(n\right)\right)=\underset{i-1}{\overset{N}{.Math.}}\underset{j=0}{\overset{K}{.Math.}}{a}_{\mathrm{ij}}x\left(n-i\right){.Math.x\left(n-i\right).Math.}^j$
Define h.sub.k=x(ni)|x(ni)|.sup.j, where k=(i1)N+j. The least square formulation can be expressed as:

(37) $\underset{k=1}{\overset{NK}{.Math.}}{w}_k{h}_k=y\left(n\right)$
In this design, QR-RLS algorithm (Haykin, 1996) is implemented to solve this problem. The formulas of QR_RLS algorithm are

(38) $\{\begin{array}{c}d\left(i\right)\stackrel{}{=}y\left(i\right)-h_i\stackrel{\_}{w}\\ {\stackrel{\_}{w}}_i\stackrel{}{=}{w}_i-\stackrel{\_}{w}\\ q_i\stackrel{}{=}{}_i^{*/2}\left[w_i-\stackrel{\_}{w}\right]\end{array}$
where .sub.i is a diagonal matrix, and q.sub.i is a vector.

(39) The QR_RLS algorithm gets the ith moment .sub.i; and q.sub.i from its (i1)th moment through a unitary transformation:

(40) 0$A=\left[\begin{array}{cc}{}_i^{1/2}& 0\\ q_i^{*}& e_a^{*}\left(i\right){}^{\frac{1}{2}}\left(i\right)\\ h_i{}_i^{*/2}& {}^{\frac{1}{2}}\left(i\right)\end{array}\right]=\left[\begin{array}{cc}{}^{1/2}{}_{i-1}^{1/2}& h_i^{*}\\ {}^{1/2}{q}_{i-1}^{*}& {d\left(i\right)}^{*}\\ 0& 1\end{array}\right]{}_i$ .sub.i is a unitary matrix for unitary transformation.

(41) To apply QR_RLS algorithm more efficiently in FPGA, a squared-root-free Givens rotation is applied for the unitary transformation process (E. N. Frantzeskakis, 1994)

(42) $\left[\begin{array}{cccc}{a}_i& a_2& \mathrm{.Math.}& a_n\\ b_1& b_2& \mathrm{.Math.}& b_n\end{array}\right]=\left[\begin{array}{cc}\sqrt{k_a}& 0\\ 0& \sqrt{k_b}\end{array}\right]\left[\begin{array}{cccc}{a}_1^{}& a_2^{}& \mathrm{.Math.}& a_n^{}\\ b_1^{}& b_2^{}& \mathrm{.Math.}& b_n^{}\end{array}\right]\left[\begin{array}{cccc}{a}_1^{}& a_2^{}& \mathrm{.Math.}& a_n^{}\\ b_1^{}& b_2^{}& \mathrm{.Math.}& b_n^{}\end{array}\right]=\left[\begin{array}{cc}\sqrt{k_a^{}}& 0\\ 0& \sqrt{k_b^{}}\end{array}\right]\left[\begin{array}{cccc}1& a_2^{}& \mathrm{.Math.}& a_n^{}\\ 0& b_2^{}& \mathrm{.Math.}& b_n^{}\end{array}\right]$$k_a^{}=k_a{a}_1^2+k_b{b}_1^2$$k_b^{}=k_a{k}_b/k_a^{}$$a_j^{}=\left(k_a{a}_1{a}_j+k_b{b}_1{b}_j\right)/k_a^{}$$b_j^{}=-b_1{a}_j+a_1{b}_j$

(43) For RLS algorithm, the ith moment is achieved as below:

(44) $\left[\begin{array}{cc}{}^{1/2}{}_{i-1}^{*/2}& h_i^{*}\\ {}^{1/2}{q}_{i-1}^{*}& \stackrel{\_}{{d\left(i\right)}^{*}}\\ 0& 1\end{array}\right]{}_i=\left[\begin{array}{cc}\stackrel{\_}{{}_i^{1/2}}& 0\\ \stackrel{\_}{q_i^{*}}& \stackrel{\_}{e_a^{*}\left(i\right){}^{\frac{1}{2}}\left(i\right)}\\ \stackrel{\_}{h_i{}_i^{*/2}}& \stackrel{\_}{{}^{\frac{1}{2}}\left(i\right)}\end{array}\right]\left[\begin{array}{cc}\sqrt{k_a}& 0\\ 0& \sqrt{k_b}\end{array}\right]$ w.sub.i can be obtained by solving
.sup.2*[w.sub.iw]=q.sub.i

(45) In the iterative process, a block of data (in this design, there are 4096 data in one block) is stored in memory, and the algorithm uses all the data in memory to estimate the DPD coefficient. In order to make the DPD performance more stable, the DPD coefficients are only updated after one block of data is processed. The matrix A will be used for the next iteration process, which will make the convergence faster.

(46) To make sure the performance of the DPD is stable, a weighting factor f is used when updating the DPD coefficients as
w.sub.i=fw.sub.i-1+(1f)w.sub.i

(47) The DPD coefficient estimator calculates coefficients w.sub.i by using QR_RLS algorithm. These w.sub.i are copied to the DPD block to linearize the PA.

(48) FIGS. 7 and 8 are block diagrams showing more sophisticated embodiments of DHMPA system, where like elements are indicated with like numerals and elements not numbered in FIG. 8 have the same reference numerals as shown in FIG. 7. The embodiments of FIGS. 7 and 8 apply crest factor reduction (CFR) prior to the PD with an adaptation algorithm in one digital processor, so as to reduce the PAPR, EVM and ACPR and compensate the memory effects and variation of the linearity due to the temperature changing of the PA. The digital processor can take nearly any form; for convenience, an FPGA implementation is shown as an example, but a general purpose processor is also acceptable in many embodiments. The CFR implemented in the digital module of the embodiments is based on the scaled iterative pulse cancellation presented in patent application U.S. 61/041,164, filed Mar. 31, 2008, entitled An Efficient Peak Cancellation Method For Reducing The Peak-To-Average Power Ratio In Wideband Communication Systems, incorporated herein by reference. The CFR is included to enhance performance and hence optional. The CFR can be removed from the embodiments without affecting the overall functionality.

(49) FIG. 7 is a block diagram showing a Digital Hybrid Mode Predistortion Power Amplifier (DHMPA) system implemented with DQM in accordance with an embodiment of the present invention. As illustrated in FIG. 7, DQM is implemented with an upconverter-based clipping error restoration path and an optional or alternative multi-channel digital input. The system shown in FIG. 7 has a dual mode of RF-in 700 and/or multi-carrier digital signal 705 at the input, and an RF signal at the output 710. The dual mode of signal input allows maximum flexibility: RF-in (the RF-in Mode) or baseband digital-in (the Baseband-in Mode). The system shown in FIG. 7 comprises three key portions: a reconfigurable digital (hereinafter referred as FPGA-based Digital) module 715, a power amplifier module 760 and a feedback path 725.

(50) The FPGA-based Digital part comprises a digital processor 715 (e.g. FPGA), digital-to-analog converters 735 (DACs), analog-to-digital converters 740 (ADCs), and a phase-locked loop (PLL) 745. Since the embodiment of FIG. 7 has a dual input mode, the digital processor has two paths of signal processing. For the RF signal input path, the digital processor has implemented a digital quadrature demodulator (DQDM), a CFR, a PD, and a digital quadrature modulator (DQM). For the baseband digital input path, a digital up-converter (DUC), CFR, PD, and a DQM are implemented.

(51) The RF-in Mode of the embodiment shown in FIG. 7 has implemented a down converter (DNC) 750 prior to the FPGA-based Digital part and an ADC 740 prior to the FPGA. An analog down converted signal is provided to the FPGA-based Digital module and converted to a digital signal by the ADC 740. The digitally converted signal is demodulated by the DQDM to generate both real and imaginary signals and then PAPR of the signal is reduced by CFR. The peak reduced signal is predistorted to linearize the amplifier and is passed through a DQM to generate the real signal and then converted to an intermediate frequency (IF) analog signal by a DAC in the FPGA-based Digital part. However, it is not required in all embodiments to implement DQDM and DQM in the FPGA. If, as shown in FIGS. 7 and 8, a digital modulator will not be used, then two DAC's 801 behind the FPGA feeding AQM module 800 can be used to generate real and imaginary signals, respectively (the AQM Implementation).

(52) The Baseband-in Mode of the system of FIG. 7 works slightly differently from the RF-in Mode. Digital data streams from multi-channels as I-Q signals are coming to the FPGA-based Digital module and are digitally up-converted to digital IF signals by the DUC. From this point onwards, the Baseband-in Mode and RF-in Mode proceeds identically. These IF signals are then passed through the CFR block so as to reduce the signal's PAPR. This PAPR suppressed signal is digitally predistorted in order to pre-compensate for nonlinear distortions of the power amplifier.

(53) In either input mode, the memory effects due to self-heating, bias networks, and frequency dependencies of the active device are compensated by the adaptation algorithm in the PD, as well. The coefficients of the PD are adapted by a synchronizing the wideband captured output signal from the feedback path 725 with the reference signal. The digital predistortion algorithm performs the synchronization and compensation. The predistorted signal is passed through a DQM in order to generate the real signal and then converted to an IF analog signal by the DAC 740 as shown. As disclosed above, the DQM is not required to be implemented in the FPGA, or at all, in all embodiments. Alternatively, if the DQM is not used in the FPGA, then the AQM Implementation can be implemented with two DACs to generate real and imaginary signals, respectively. The gate bias voltage 753 of the power amplifier is determined by the adaptation algorithm and then adjusted through the DACs 535 in order to stabilize the linearity fluctuations due to the temperature changes in the power amplifier.

(54) The power amplifier part comprises a UPC for a real signal (such as illustrated in the embodiment shown in FIG. 7), or an AQM for real and complex signals (such as the embodiment of a DHMPA system depicted in FIG. 8) from the FPGA-based Digital module, a high power amplifier with multi-stage drive amplifiers, and a temperature sensor. In order to improve the efficiency performance of the DHMPA system, efficiency boosting techniques such as Doherty, Envelope Elimination and Restoration (EER), Envelope Tracking (ET), Envelope Following (EF), and Linear amplification using Nonlinear Components (LINC) can be used, depending upon the embodiment. These power efficiency techniques can be mixed and matched and are optional features to the fundamental DHMPA system. One such Doherty power amplifier technique is presented in commonly assigned U.S. Provisional Patent Application Ser. No. 60/925,577, filed Apr. 23, 2007, entitled N-Way Doherty Distributed Power Amplifier, incorporated herein by reference, together with U.S. patent application Ser. No. 12/603,419, filed Oct. 21, 2009, entitled N-Way Doherty Distributed Power Amplifier with Power Tracking. To stabilize the linearity performance of the amplifier, the temperature of the amplifier is monitored by the temperature sensor and then the gate bias of the amplifier is controlled by the FPGA-based Digital part.

(55) The feedback portion comprises a directional coupler, a mixer, a gain amplifier, a band pass filter (BPF), and a Digital to Analog Converter (DAC). Depending upon the embodiment, these analog components can be mixed and matched with other analog components. Part of the RF output signal of the amplifier is sampled by the directional coupler and then down converted to an IF analog signal by the local oscillation signal in the mixer. The IF analog signal is passing through the gain amplifier, and the BPF (e.g., surface acoustic wave filter) which can capture the out-of-band distortions. The output of the BPF is provided to the ADC of the FPGA-based Digital module in order to determine the dynamic parameters of the digital PD depending on output power levels and asymmetrical distortions due to the memory effects. In addition, temperature is also detected by the detector 580 to calculate the variation of linearity and then adjust gate bias voltage of the PA. More details of the PD algorithm and self-adaptation feedback algorithm can be appreciated from FIG. 3, discussed above, which shows a polynomial-based predistortion algorithm and from FIG. 4, also discussed above, which shows the block diagram of the digital predistorter synchronization algorithm which can be used in some embodiments of the invention.

(56) In the case of a strict EVM requirement for broadband wireless access such as WiMAX or other OFDM based schemes (EVM<2.5%), the CFR in the FPGA-based Digital part is only able to achieve a small reduction of the PAPR in order to meet the strict EVM specification. In general circumstances, this means the CFR's power efficiency enhancement capability is limited. In some embodiments of the present invention, a novel technique is included to compensate the in-band distortions from CFR by use of a Clipping Error Restoration Path 790, hence maximizing the DHMPA system power efficiency in those strict EVM environments. As noted above, the Clipping Error Restoration Path has an additional DAC 735 in the FPGA-based Digital portion and an extra UPC 720 in the power amplifier part (see FIGS. 7 and 8). The Clipping Error Restoration Path can allow compensation of in-band distortions resulting from the CFR at the output of the power amplifier. Further, any delay mismatch between the main path and the Clipping Error Restoration Path can be aligned using digital delay in the FPGA.

(57) Referring again to FIG. 7, the RF input signal is first down-converted to baseband digital signals, and then digitally up-converted to digital IF signals (7.5 MHz, 2.5 MHz, 2.5 MHz, 7.5 MHz). If the system of FIG. 7 has a Baseband-in Mode, then the digital data streams from multi-channels are digitally up-converted to digital IF signals (7.5 MHz, 2.5 MHz, 2.5 MHz, 7.5 MHz) directly as they enter the digital processor. The CFR then reduces the PAPR. The peak-reduced signal is predistorted to linearize the DPA and is passing through two DACs for real and imaginary signals and finally through an AQM.

(58) FIG. 9. is a block diagram showing an embodiment of the analog quadrature modulator compensation structure. The input signal is separated into an in-phase component X.sub.1 and a quadrature component X.sub.Q. The analog quadrature modulator compensation structure comprises four real filters {g11, g12, g21, g22} and two DC offset compensation parameters c1, c2. The DC offsets in the AQM will be compensated by the parameters c1, c2. The frequency dependence of the AQM will be compensated by the filters {g11, g12, g21, g22}. The order of the real filters is dependent on the level of compensation required. The output signals YI and YQ will be presented to the AQM's in-phase and quadrature ports.

(59) The configuration of the power amplifier part and the feedback part of the system shown in FIG. 8 are the same as for the system shown in FIG. 7.

(60) FIG. 8 illustrates an embodiment of a Digital Hybrid Mode Predistortion PA System implemented using a digital quadrature modulator with an upconversion-based clipping error restoration path and an optional or alternative multi-channel digital input with feedback calibration. In the system shown in FIG. 8, the DNC frequency translates the RF signal into a low IF signal. The IF signal is then presented to the ADC whereupon it is digitally down-converted to baseband followed by CFR and predistortion (PD). The output of the PD is a baseband signal which will then be digitally upconverted to an IF frequency and presented to the DAC. The output of the DAC is then further frequency translated to a RF frequency through the up-converter (UPC.) The configuration of the power amplifier part and the feedback part of system of FIG. 8 are the same as for the FIG. 7 System.

(61) In summary, the DHMPA system of the present invention enhances efficiency and linearity relative to the prior art since the DHMPA system is able to implement CFR, DPD and adaptation algorithms in one digital processor, which consequently saves hardware resources and processing time. The DHMPA system is also reconfigurable and field-programmable since the algorithms and power-efficiency-enhancing features can be adjusted like software in the digital processor at anytime.

(62) Furthermore, since the DHMPA system accepts RF modulated signal as input, it is not necessary to use coded I and Q channel signals in the baseband. Therefore, the performance of wireless base-station systems can be enhanced simply by replacing the existing PA modules with the DHMPA. The result is that the present invention provides a plug and play PA system solution such that the structure of existing base-station systems does not need to be modified or rebuilt for a new set of signal channels in order to benefit from high efficiency and high linearity PA system performance.

(63) Moreover, the DHMPA system is agnostic to modulation schemes such as quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), Orthogonal Frequency Division Multiplexing (OFDM), etc. in code division multiple access (CDMA), global system for wireless communications (GSM), WCDMA, CDMA2000, and wireless LAN systems. This means that the DHMPA system is capable of supporting multi-modulation schemes, multi-carriers and multi-channels. Other benefits of the DHMPA system of the present invention include correction of PA non-linearities in repeater or indoor coverage systems that do not have the necessary baseband signals information readily available.

(64) Although the present invention has been described with reference to the preferred embodiments, it will be understood that the invention is not limited to the details described thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.