Memory redundancy repair

Abstract

Memories, and their operation, might include a plurality of content addressable memory (CAM) cells each for storing a respective data value, a match signal generator configured to generate an indication whether each CAM cell of the plurality of CAM cells indicates a match between its respective data value and a respective received signal value, and a plurality of storage elements each for storing a respective data value, wherein each storage element of the plurality of storage elements corresponds to a respective CAM cell of the plurality of CAM cells in a one-to-one relationship, and wherein each storage element of the plurality of storage elements is responsive to the indication of the match signal generator to generate a data signal indicative of the respective data value of that storage element if a match of their corresponding CAM cells is indicated.

Claims

1. A memory, comprising: a plurality of content addressable memory (CAM) cells, wherein each CAM cell of the plurality of CAM cells is configured to store a respective data value; a match signal generator configured to generate an indication whether each CAM cell of the plurality of CAM cells indicates a match between its respective data value and a respective received signal value; and a plurality of storage elements, wherein each storage element of the plurality of storage elements corresponds to a respective CAM cell of the plurality of CAM cells in a one-to-one relationship, wherein each storage element of the plurality of storage elements is configured to store a respective data value, and wherein each storage element of the plurality of storage elements is responsive to the indication of the match signal generator to selectively generate a data signal indicative of the respective data value of that storage element.

2. The memory of claim 1, wherein the respective data value of each CAM cell of the plurality of CAM cells corresponds to a digit of an address portion of a defective memory element, and wherein the respective data value of each storage element of the plurality of storage elements corresponds to a digit of an address portion of a redundant memory element.

3. The memory of claim 1, wherein, for at least one storage element of the plurality of storage elements, the respective data value for that storage element is different than the respective data value of its corresponding CAM cell of the plurality of CAM cells.

4. The memory of claim 1, wherein the indication of the match signal generator comprises a signal having a first logic level when in response to each CAM cell of the plurality of CAM cells indicating a match between its respective data value and its respective received signal value, and having a second logic level, different than the first logic level, in response to any CAM cell of the plurality of CAM cells indicating a mis-match between its respective data value and its respective received signal value.

5. The memory of claim 4, wherein the signal of the indication is a first signal, and wherein the indication of the match signal generator further comprises a second signal having the second logic level in response to each CAM cell of the plurality of CAM cells indicating a match between its respective data value and its respective received signal value, and having the first logic level in response to any CAM cell of the plurality of CAM cells indicating a mis-match between its respective data value and its respective received signal value.

6. The memory of claim 5, wherein each storage element of the plurality of storage elements whose respective data value has a particular logic level is responsive to the logic level of the first signal without regard to the logic level of the second signal, and wherein each storage element of the plurality of storage elements whose respective data value has a different logic level, different than the particular logic level, is responsive to the logic level of the second signal without regard to the logic level of the first signal.

7. The memory of claim 6, wherein the particular logic level and the second logic level are a same logic level, and wherein the different logic level and the first logic level are a same logic level.

8. The memory of claim 1, wherein a particular storage element of the plurality of storage elements comprises a first field-effect transistor (FET) having a first source/drain connected to a first voltage node and a second source/drain connected to a first source/drain of a second FET, wherein the second FET has a second source/drain connected to a second voltage node, wherein the first voltage node is configured to receive a first voltage level, wherein the second voltage node is configured to receive a second voltage level lower than the first voltage level, wherein the first FET is configured to be selectively activated in response to the indication if the particular storage element stores a data value having a first logic level and to be deactivated regardless of the indication if the particular storage element stores the data value having a second logic level different than the first logic level, and wherein the second FET is configured to be selectively activated in response to the indication whet-if the particular storage element stores the data value having the second logic level and to be deactivated regardless of the indication if the particular storage element stores the data value having the first logic level.

9. The memory of claim 8, wherein the particular storage element is of a type selected from a group consisting of a hard-wired storage element, a read-only storage element, and a register-based storage element.

10. A memory, comprising: an array of content addressable memory (CAM) cells comprising a plurality of groupings of CAM cells, wherein each CAM cell of the array of CAM cells is configured to store a respective data value; a plurality of signal nodes, wherein each signal node of the plurality of signal nodes is in communication with a respective CAM cell for each grouping of CAM cells of the plurality of groupings of CAM cells; a plurality of match signal generators, wherein each match signal generator of the plurality of match signal generators corresponds to a respective grouping of CAM cells of the plurality of groupings of CAM cells, and wherein each match signal generator of the plurality of match signal generators is configured to generate an indication whether each CAM cell of its respective grouping of CAM cells indicates a match between its respective data value and a signal value received from its respective signal node of the plurality of signal nodes; a plurality of groupings of storage elements, wherein each grouping of storage elements of the plurality of groupings of storage elements corresponds to a respective grouping of CAM cells of the plurality of groupings of CAM cells and to the respective match signal generator for that respective grouping of CAM cells; and a multiplexer having a first plurality of inputs, and having a plurality of outputs, wherein each input of the first plurality of inputs is in communication with a respective signal node of the plurality of signal nodes, and wherein each input of the second plurality of inputs is in communication with the output of a respective storage element of each grouping of storage elements of the plurality of groupings of storage elements; wherein each storage element of the plurality of groupings of storage elements corresponds to a respective CAM cell of its respective grouping of CAM cells in a one-to-one relationship, wherein each storage element of the plurality of groupings of storage elements is configured to store a respective data value, and wherein each storage element of the plurality of groupings of storage elements is responsive to the indication of its match signal generator to generate a data signal on an output of that storage element indicative of the respective data value of that storage element in response to the indication of the respective match signal generator for that storage element indicating a match, and to present a high impedance to the output of that storage element in response to the indication of the respective match signal generator for that storage element indicating a mis-match; and wherein the multiplexer is configured to connect its plurality of outputs to the first plurality of inputs in response to no match signal generator of the plurality of match signal generators indicating a match, and to connect its plurality of outputs to the second plurality of inputs in response to any match signal generator of the plurality of match signal generators indicating a match.

11. The memory of claim 10, wherein the multiplexer is responsive to a logic level of an input of the second plurality of inputs to determine whether a match signal generator of the plurality of match signal generators indicates a match.

12. The memory of claim 10, wherein, for each storage element of a particular grouping of storage elements of the plurality of groupings of storage elements, the output of that storage element is commonly connected to a respective storage element of each remaining grouping of storage elements of the plurality of groupings of storage elements.

13. The memory of claim 10, wherein, for each match signal generator of the plurality of match signal generators, the indication for that match signal generator comprises a pair of complementary signals.

14. The memory of claim 13, wherein, for each storage element of the plurality of storage elements, that storage element is responsive to a first signal of the pair of complementary signals if that storage element stores a first data value, and is responsive to a second signal of the pair of complementary signals if that storage element stores a second data value, different than the first data value.

15. A method of operating a memory, comprising: comparing a received address portion to a stored address portion; generating an indication whether a match was detected between the received address portion and the stored address portion; activating a plurality of storage elements responsive to the indication indicating that a match between the received address portion and the stored address portion is detected, wherein activating the plurality of storage elements comprises, for each storage element of the plurality of storage elements, causing that storage element to generate a respective address signal at an output of that storage element; and accessing a redundant memory element in response to the outputs of the activated plurality of storage elements.

16. The method of claim 15, wherein comparing the received address portion to the stored address portion comprises comparing a received address portion corresponding to a memory element of the memory to be accessed to a stored address portion corresponding to a memory element of the memory deemed to be defective.

17. The method of claim 15, wherein activating the plurality of storage elements comprises activating a plurality of storage elements collectively storing an address portion corresponding to the redundant memory element.

18. The method of claim 15, wherein the stored address portion is a first stored address portion, wherein the indication is a first indication, wherein the plurality of storage elements is a first plurality of storage elements, and wherein the redundant memory element is a first redundant memory element, the method further comprising: comparing the received address portion to a second stored address portion; generating a second indication whether a match was detected between the received address portion and the second stored address portion; deactivating the first plurality of storage elements responsive to the first indication indicating that a mis-match between the received address portion and the first stored address portion is detected; activating a second plurality of storage elements responsive to the second indication indicating that a match between the received address portion and the second stored address portion is detected; deactivating the second plurality of storage elements responsive to the first indication indicating that a mis-match between the received address portion and the first stored address portion is detected; and accessing a second redundant memory element in response to outputs of the activated second plurality of storage elements.

19. The method of claim 18, wherein, for each storage element of the first plurality of storage elements, the output of that storage element is connected to the output of a corresponding storage element of the second plurality of storage elements.

20. The method of claim 15, further comprising: deactivating the plurality of storage elements responsive to the indication indicating that a mis-match between the received address portion and the stored address portion is detected.

21. The method of claim 20, wherein deactivating the plurality of storage elements comprises, for each storage element of the plurality of storage elements, presenting a high impedance to the output of that storage element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a simplified block diagram of a memory in communication with a processor as part of an electronic system, according to an embodiment.

(2) FIGS. 2A-2B are schematics of portions of an array of memory cells as could be used in a memory of the type described with reference to FIG. 1.

(3) FIGS. 3A-3B are block schematics of repair logic and control circuitry of the related art.

(4) FIGS. 4A-4D are block schematics of repair logic and control circuitry in accordance with embodiments.

(5) FIG. 5 is a schematic of a content-addressable memory cell and associated storage element for communication with a match signal generator in accordance with an embodiment.

(6) FIGS. 6A-6D are schematics of storage elements and corresponding logic in accordance with embodiments.

(7) FIG. 7 is a flowchart of a method of operating a memory in accordance with an embodiment.

DETAILED DESCRIPTION

(8) In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments might be utilized and structural, logical and electrical changes might be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

(9) The term “semiconductor” used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps might have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.

(10) The term “conductive” as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term “connecting” as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting unless otherwise apparent from the context.

(11) FIG. 1 is a simplified block diagram of a first apparatus, in the form of a memory (e.g., memory device) 100, in communication with a second apparatus, in the form of a processor 130, as part of a third apparatus, in the form of an electronic system, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The processor 130, e.g., a controller external to the memory device 100, might be a memory controller or other external host device.

(12) Memory device 100 includes an array of memory cells 104 logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line might be associated with more than one logical row of memory cells and a single data line might be associated with more than one logical column. Memory cells (not shown in FIG. 1) of at least a portion of array of memory cells 104 are capable of being programmed to one of at least two target data states.

(13) A row decode circuitry 108 and a column decode circuitry 110 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 104. Memory device 100 also includes input/output (I/O) control circuitry 112 to manage input of commands, addresses and data to the memory device 100 as well as output of data and status information from the memory device 100. An address register 114 is in communication with I/O control circuitry 112 and row decode circuitry 108 and column decode circuitry 110 to latch the address signals prior to decoding. The address register 114 might further be in communication with a repair logic and control circuitry 128 in accordance with an embodiment. While the repair logic and control circuitry 128 is depicted to be in communication with the column decode circuitry 110 for redundancy repair of defective columns of memory cells, the concepts described herein could be equally applied to the redundancy repair of defective rows of memory cell. A command register 124 is in communication with I/O control circuitry 112 and control logic 116 to latch incoming commands.

(14) A controller (e.g., the control logic 116 internal to the memory device 100) controls access to the array of memory cells 104 in response to the commands and generates status information for the external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which might include read operations and verify operations], programming operations and/or erase operations) on the array of memory cells 104. The control logic 116 is in communication with row decode circuitry 108 and column decode circuitry 110 to control the row decode circuitry 108 and column decode circuitry 110 in response to the addresses. The control logic 116 might include instruction registers 128 which might represent computer-usable memory for storing computer-readable instructions. For some embodiments, the instruction registers 128 might represent firmware. Alternatively, the instruction registers 128 might represent a grouping of memory cells, e.g., reserved block(s) of memory cells, of the array of memory cells 104.

(15) Control logic 116 is also in communication with a cache register 118. Cache register 118 latches data, either incoming or outgoing, as directed by control logic 116 to temporarily store data while the array of memory cells 104 is busy writing or reading, respectively, other data. During a programming operation (e.g., write operation), data might be passed from the cache register 118 to the data register 120 for transfer to the array of memory cells 104; then new data might be latched in the cache register 118 from the I/O control circuitry 112. During a read operation, data might be passed from the cache register 118 to the I/O control circuitry 112 for output to the external processor 130; then new data might be passed from the data register 120 to the cache register 118. The cache register 118 and/or the data register 120 might form (e.g., might form a portion of) a page buffer of the memory device 100. A page buffer might further include sensing devices (not shown in FIG. 1) to sense a data state of a memory cell of the array of memory cells 104, e.g., by sensing a state of a data line connected to that memory cell. A status register 122 might be in communication with I/O control circuitry 112 and control logic 116 to latch the status information for output to the processor 130.

(16) Memory device 100 receives control signals at control logic 116 from processor 130 over a control link 132. The control signals might include a chip enable CE #, a command latch enable CLE, an address latch enable ALE, a write enable WE #, a read enable RE #, and a write protect WP #. Additional or alternative control signals (not shown) might be further received over control link 132 depending upon the nature of the memory device 100. Memory device 100 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor 130 over a multiplexed input/output (I/O) bus 134 and outputs data to processor 130 over I/O bus 134.

(17) For example, the commands might be received over input/output (I/O) pins [7:0] of I/O bus 134 at I/O control circuitry 112 and might then be written into command register 124. The addresses might be received over input/output (I/O) pins [7:0] of I/O bus 134 at I/O control circuitry 112 and might then be written into address register 114. The data might be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry 112 and then might be written into cache register 118. The data might be subsequently written into data register 120 for programming the array of memory cells 104. For another embodiment, cache register 118 might be omitted, and the data might be written directly into data register 120. Data might also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference might be made to I/O pins, they might include any conductive node providing for electrical connection to the memory device 100 by an external device (e.g., processor 130), such as conductive pads or conductive bumps as are commonly used.

(18) It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device 100 of FIG. 1 has been simplified. It should be recognized that the functionality of the various block components described with reference to FIG. 1 might not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of FIG. 1. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of FIG. 1.

(19) Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) might be used in the various embodiments.

(20) FIG. 2A is a schematic of a portion of an array of memory cells 200A, such as a NAND memory array, as could be used in a memory of the type described with reference to FIG. 1, e.g., as a portion of array of memory cells 104. Memory array 200A includes access lines, such as word lines 202.sub.0 to 202.sub.N, and data lines, such as bit lines 204.sub.0 to 204.sub.M. The word lines 202 might be connected to global access lines (e.g., global word lines), not shown in FIG. 2A, in a many-to-one relationship. For some embodiments, memory array 200A might be formed over a semiconductor that, for example, might be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

(21) Memory array 200A might be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column might include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings 206.sub.0 to 206.sub.M. Each NAND string 206 might be connected (e.g., selectively connected) to a common source (SRC) 216 and might include memory cells 208.sub.0 to 208.sub.N. The memory cells 208 might represent non-volatile memory cells for storage of data. The memory cells 208 of each NAND string 206 might be connected in series between a select gate 210 (e.g., a field-effect transistor), such as one of the select gates 210.sub.0 to 210.sub.M (e.g., that might be source select transistors, commonly referred to as select gate source), and a select gate 212 (e.g., a field-effect transistor), such as one of the select gates 212.sub.0 to 212.sub.M (e.g., that might be drain select transistors, commonly referred to as select gate drain). Select gates 210.sub.0 to 210.sub.M might be commonly connected to a select line 214, such as a source select line (SGS), and select gates 212.sub.0 to 212.sub.M might be commonly connected to a select line 215, such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gates 210 and 212 might utilize a structure similar to (e.g., the same as) the memory cells 208. The select gates 210 and 212 might represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal.

(22) A source of each select gate 210 might be connected to common source 216. The drain of each select gate 210 might be connected to a memory cell 208.sub.0 of the corresponding NAND string 206. For example, the drain of select gate 210.sub.0 might be connected to memory cell 208.sub.0 of the corresponding NAND string 206.sub.0. Therefore, each select gate 210 might be configured to selectively connect a corresponding NAND string 206 to common source 216. A control gate of each select gate 210 might be connected to select line 214.

(23) The drain of each select gate 212 might be connected to the bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 212.sub.0 might be connected to the bit line 204.sub.0 for the corresponding NAND string 206.sub.0. The source of each select gate 212 might be connected to a memory cell 208.sub.N of the corresponding NAND string 206. For example, the source of select gate 212.sub.0 might be connected to memory cell 208.sub.N of the corresponding NAND string 206.sub.0. Therefore, each select gate 212 might be configured to selectively connect a corresponding NAND string 206 to the corresponding bit line 204. A control gate of each select gate 212 might be connected to select line 215.

(24) The memory array in FIG. 2A might be a quasi-two-dimensional memory array and might have a generally planar structure, e.g., where the common source 216, NAND strings 206 and bit lines 204 extend in substantially parallel planes. Alternatively, the memory array in FIG. 2A might be a three-dimensional memory array, e.g., where NAND strings 206 might extend substantially perpendicular to a plane containing the common source 216 and to a plane containing the bit lines 204 that might be substantially parallel to the plane containing the common source 216.

(25) Typical construction of memory cells 208 includes a data-storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate 236, as shown in FIG. 2A. The data-storage structure 234 might include both conductive and dielectric structures while the control gate 236 is generally formed of one or more conductive materials. In some cases, memory cells 208 might further have a defined source/drain (e.g., source) 230 and a defined source/drain (e.g., drain) 232. Memory cells 208 have their control gates 236 connected to (and in some cases form) a word line 202.

(26) A column of the memory cells 208 might be a NAND string 206 or a plurality of NAND strings 206 selectively connected to a given bit line 204. A row of the memory cells 208 might be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 can, but need not, include all memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 might often be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 often include every other memory cell 208 commonly connected to a given word line 202. For example, memory cells 208 commonly connected to word line 202.sub.N and selectively connected to even bit lines 204 (e.g., bit lines 204.sub.0, 204.sub.2, 204.sub.4, etc.) might be one physical page of memory cells 208 (e.g., even memory cells) while memory cells 208 commonly connected to word line 202.sub.N and selectively connected to odd bit lines 204 (e.g., bit lines 204.sub.1, 204.sub.3, 204.sub.5, etc.) might be another physical page of memory cells 208 (e.g., odd memory cells). Although bit lines 204.sub.3-204.sub.5 are not explicitly depicted in FIG. 2A, it is apparent from the figure that the bit lines 204 of the array of memory cells 200A might be numbered consecutively from bit line 204.sub.0 to bit line 204.sub.M. Other groupings of memory cells 208 commonly connected to a given word line 202 might also define a physical page of memory cells 208. For certain memory devices, all memory cells commonly connected to a given word line might be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) might be deemed a logical page of memory cells. A block of memory cells might include those memory cells that are configured to be erased together, such as all memory cells connected to word lines 202.sub.0-202.sub.N (e.g., all NAND strings 206 sharing common word lines 202). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells.

(27) Although the example of FIG. 2A is discussed in conjunction with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS or other data storage structure configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

(28) FIG. 2B is another schematic of a portion of an array of memory cells 200B as could be used in a memory of the type described with reference to FIG. 1, e.g., as a portion of array of memory cells 104. Like numbered elements in FIG. 2B correspond to the description as provided with respect to FIG. 2A. FIG. 2B provides additional detail of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B might incorporate vertical structures which might include semiconductor pillars where a portion of a pillar might act as a channel region of the memory cells of NAND strings 206. The NAND strings 206 might be each selectively connected to a bit line 204.sub.0-204.sub.M by a select transistor 212 (e.g., that might be drain select transistors, commonly referred to as select gate drain) and to a common source 216 by a select transistor 210 (e.g., that might be source select transistors, commonly referred to as select gate source). Multiple NAND strings 206 might be selectively connected to the same bit line 204. Subsets of NAND strings 206 can be connected to their respective bit lines 204 by biasing the select lines 215.sub.0-215.sub.K to selectively activate particular select transistors 212 each between a NAND string 206 and a bit line 204. The select transistors 210 can be activated by biasing the select line 214. Each word line 202 might be connected to multiple rows of memory cells of the memory array 200B. Rows of memory cells that are commonly connected to each other by a particular word line 202 might collectively be referred to as tiers.

(29) The three-dimensional NAND memory array 200B might be formed over peripheral circuitry 226. The peripheral circuitry 226 might represent a variety of circuitry for accessing the memory array 200B. The peripheral circuitry 226 might include complementary circuit elements. For example, the peripheral circuitry 226 might include both n-channel and p-channel transistors formed on a same semiconductor substrate, a process commonly referred to as CMOS, or complementary metal-oxide-semiconductors. Although CMOS often no longer utilizes a strict metal-oxide-semiconductor construction due to advancements in integrated circuit fabrication and design, the CMOS designation remains as a matter of convenience. The repair logic and control circuitry might represent a portion of the peripheral circuitry 226.

(30) As arrays of memory cells increase in memory density, e.g., increasing numbers of memory cells for a given area of an integrated circuit die, demands placed on the area within the peripheral circuitry 226 might also increase. Repair logic and control circuitry has traditionally taken a large portion of the peripheral circuitry of a memory. Various embodiments seek to facilitate a reduction in size of the repair logic and control circuitry, while providing similar functionality for redundancy repair of a memory.

(31) FIGS. 3A-3B are block schematics of repair logic and control circuitry of the related art. FIG. 3A depicts an array of content-addressable memory (CAM) cells 300 as a portion of a repair logic and control circuitry of the related art. The array of CAM cells 300 might have a number of rows 340, e.g., rows 340.sub.0 to 340.sub.j, where j is any natural number, i.e., a non-negative integer value. Each row 340 of the array of CAM cells 300 might include a number of CAM cells 342, e.g., CAM cells 342.sub.0 to 342.sub.i, wherein i is any natural number. In general, the value of i might be selected such that i+1 is equal to a number of digits of an address portion to be stored to the array of CAM cells 300. For example, for column redundancy, the address portion might correspond to the column address of the memory cells to be accessed.

(32) The CAM cells 342 generally might each be configured to store a data value, e.g., corresponding to a digit of an address signal, and to provide an output signal having a logic level representative of whether or not a received signal value matches the stored data value. For example, each CAM cell 342 might include a register 344, e.g., registers 344.sub.0 to 344.sub.i, in communication with, e.g., connected to, a corresponding compare logic 346, e.g., compare logic 346.sub.0 to 346.sub.i, respectively. Each compare logic 346 might be connected to receive a signal value from a corresponding signal node 354, e.g., signal nodes 354.sub.0 to 354.sub.i, respectively. The signal nodes 354, which might be referred to as signal nodes 354[i:0], might each be connected to receive a corresponding digit of an address signal, such as from the address register 114 of FIG. 1, for example. Each compare logic 346 might be configured to generate a signal at its output 348, e.g., outputs 348.sub.0 to 348.sub.i, respectively, having a first logic level if the data value (e.g., logic level) stored in its register 344 is deemed to be the same as (e.g., equal to) a signal value (e.g., logic level) received from its corresponding signal node 354 (referred to as a match), and a second logic level, different than (e.g., opposite of) its first logic level, if the data value stored in its register 344 is deemed to be different than the signal value received from its corresponding signal node 354 (referred to as a mis-match). For example, each compare logic 346 might represent an XOR gate or an XNOR gate.

(33) Programming the registers 344 of one or more rows 340 might include accessing (e.g., reading) a particular portion of an array of memory cells 104 storing address portions corresponding to defective memory elements. In general, testing of a memory might be used to determine which memory elements are deemed to be usable, and which are deemed to be defective. When a memory element is deemed to be defective, an address portion corresponding to that memory element might be stored to a non-volatile storage location of the memory, e.g., the array of memory cells 104. These address portions might then be accessed during power-up of the memory to program the registers 344 accordingly.

(34) The outputs 348 of each CAM cell 342 of a row 340 of the array of CAM cells 300 might be connected to a match signal generator 350 corresponding to that row 340. Each row 340.sub.0 to 340.sub.j might have a corresponding match signal generator 350, e.g., match signal generators 350.sub.0 to 350.sub.j, respectively, in the same manner as depicted in row 340.sub.0. Each match signal generator 350 might be configured to generate a signal at its output 352, e.g., outputs 352.sub.0 to 352.sub.j, respectively, having a first logic level if each of the outputs 348 of its corresponding CAM cells 342 indicates a match, and having a second logic level, different than (e.g., opposite of) its first logic level if any of the outputs 348 of its corresponding CAM cells 342 indicates a mis-match. Note that the first logic level for the output 352 of a match signal generator 350 might be the same as, or different from, the first logic level for the output 348 of a CAM cell 342. Each row 340 of the array of CAM cells 300 might be configured in a same manner as depicted with regard to row 340.sub.0, with each compare logic 346.sub.0 to 346, connected to its corresponding signal node 354.sub.0 to 354.sub.i, respectively.

(35) In practice, an address portion for a corresponding defective memory element, e.g., a column of memory cells containing one or more memory cells identified as being defective, might be stored in the CAM cells 342 of a row 340 of the array of CAM cells 300. Each row 340 of the array of CAM cells 300 might store a different address portion, each corresponding to a different defective memory element. It is noted that where a number of identified defective memory elements is less than the number of rows 340 of the array of CAM cells 300, one or more of the rows 340 might not store any address portion, but might instead store values not corresponding to any accessible address. For example, values of all logic low levels or all logic high levels might not correspond to any address to be received on the signal nodes 354. In this manner, a row 340 of the array of CAM cells 300 not corresponding to a defective memory element might be configured to always indicate a mis-match in response to an address received on the signal nodes 354.

(36) Each row 340 storing an address portion might further correspond to a respective redundant memory element, and each redundant memory element might have a corresponding address portion outside of the address space, e.g., of the array of memory cells 104, that might be received on the signal nodes 354. For example, assuming i=7, valid addresses to be received from the signal nodes 354 might correspond to an address space contained in 00000000 to 01111111, while addresses for redundant memory elements might correspond to an address space beginning with 10000000. With each row 340 storing a different address portion, or not storing any valid address portion, it might be expected that no more than one output 352 would indicate a match between its stored address portion and the address portion received from the signal nodes 354. In this manner, the output 352 indicating a match might serve to indicate that the redundant memory element corresponding to the row 340 generating that output 352 should be accessed instead of the defective memory element corresponding to the address portion received on the signal nodes 354.

(37) Prior repair logic and control circuitry might utilize an encoder responsive to the outputs 352 to generate an address portion corresponding to the redundant memory element for the row 340 indicating a match on its output 352. Encoders for such uses might typically have been formed of complex combination logic circuits, generating an output of j+1 unique combinations of i+1 digits within a defined address space from an input of j digits having a particular logic level (e.g., a logic low level), and 1 digit having a different logic level (e.g., a logic high level). Such circuits might utilize a significant area of the peripheral circuitry of a memory.

(38) FIG. 3B depicts an encoder 356 and multiplexer (MUX) 360 used to generate an address portion for a redundant memory element if a match is indicated by one of the match signal generators 350 of FIG. 3A, and to select the address portion for the redundant memory element if the match is indicated, or to select the address portion received on the signal nodes 354 if no match is indicated. The encoder 356 is responsive to the outputs 352.sub.0 to 352.sub.j, which might be referred to as outputs 352[j:0], to generate i+1 address signals at an output 358[i:0] corresponding to an address portion of a redundant memory element corresponding to a row 340 having an output 352 indicating a match. The multiplexer 360 is connected to receive the i+1 address signals from the output 358[i:0] and to receive the i+1 address signals from the signal nodes 354[i:0]. The multiplexer 360 is responsive to a control signal from control signal node 364 to select the address signals from the signal nodes 354[i:0] for output if no match is indicated, and to select the address signals from the output 358[i:0] of the encoder 356 if a match is indicated. The selected address signals are then provided at an output 362[i:0], e.g., for input to column decode circuitry 110.

(39) For example, the signal received at the control signal node 364 might correspond to an output of an OR gate (not shown) receiving the outputs 352.sub.0 to 352.sub.j as inputs. In this manner, a logic low level from the OR gate might indicate no match in order to select the address signals from the signal nodes 354[i:0], while a logic high level from the OR gate might indicate a match in order to select the address signals from the encoder 356. Alternatively, where a particular digit of the address portion represented by the output 358[i:0], e.g., the i.sup.th digit from the output 358[i:0], has a particular value when a match is indicated, and a different value when no match is indicated, this digit of the address portion could be used as the control signal at the control signal node 364.

(40) FIGS. 4A-4D are block schematics of repair logic and control circuitry in accordance with embodiments. FIG. 4A depicts an array of content-addressable memory (CAM) cells 400 as a portion of a repair logic and control circuitry in accordance with an embodiment. The array of CAM cells 400 might have a number of rows 440, e.g., rows 440.sub.0 to 440.sub.j, where j is any natural number, i.e., a non-negative integer value. Each row 440 of the array of CAM cells 400 might include a number of CAM cells 442, e.g., CAM cells 442.sub.0 to 442.sub.i, wherein i is any natural number. Each row 440 of the array of CAM cells 400 might be referred to as a grouping of CAM cells 442. In general, the value of i might be selected such that i+1 is equal to a number of digits of an address portion to be stored to the array of CAM cells 400. For example, for column redundancy, the address portion might correspond to the column address of the memory cells addressed for access. In this example, each row 440 of the array of CAM cells 400 might correspond to a different column address.

(41) The CAM cells 442 generally might each be configured to store a data value, e.g., corresponding to a digit of an address signal, and to provide an output signal having a logic level representative of whether or not a received signal value matches the stored data value. For example, each CAM cell 442 might include a register 444, e.g., registers 444.sub.0 to 444.sub.i, in communication with, e.g., connected to, a corresponding compare logic 446, e.g., compare logic 446.sub.0 to 446.sub.i, respectively. Each compare logic 446 might be connected to receive a signal value from a corresponding signal node 454, e.g., signal nodes 454.sub.0 to 454.sub.i, respectively. The signal nodes 454, which might be referred to as signal nodes 454[i:0], might each be connected to receive a corresponding digit of an address signal, such as from the address register 114 of FIG. 1, for example. Each compare logic 446 might be configured to generate a signal at its output 448, e.g., outputs 448.sub.0 to 448.sub.i, respectively, having a first logic level if the data value (e.g., logic level) stored in its register 444 is deemed to be the same as (e.g., equal to) a signal value (e.g., logic level) received from its corresponding signal node 454 (referred to as a match), and a second logic level, different than (e.g., opposite of) its first logic level, if the data value stored in its register 444 is deemed to be different than the signal value received from its corresponding signal node 454 (referred to as a mis-match). For example, each compare logic 446 might represent an XOR gate or an XNOR gate.

(42) Programming the registers 444 of one or more rows 440 might include accessing (e.g., reading) a particular portion of an array of memory cells 104 storing address portions corresponding to defective memory elements. In general, testing of a memory might be used to determine which memory elements are deemed to be usable, and which are deemed to be defective. When a memory element is deemed to be defective, an address portion corresponding to that memory element might be stored to a non-volatile storage location of the memory, e.g., the array of memory cells 104. These address portions might then be accessed during power-up of the memory to program the registers 444 accordingly.

(43) The outputs 448 of each CAM cell 442 of a row 440 of the array of CAM cells 400 might be connected to a match signal generator 450 corresponding to that row 440. Each row 440.sub.0 to 440.sub.j might have a corresponding match signal generator 450, e.g., match signal generators 450.sub.0 to 450.sub.j, respectively, in the same manner as depicted in row 440.sub.0. Each match signal generator 450 might be configured to generate an indication at its output 474, e.g., outputs 474.sub.0 to 474.sub.j, respectively, indicative of whether a match is indicated between the signals received from the signal nodes 454.sub.0 to 454.sub.i, and the values stored in the registers 444.sub.0 to 444.sub.i of the corresponding row 440.

(44) As one example, the indication might be a signal having a first logic level if each of the outputs 448 of its corresponding CAM cells 442 indicates a match, and having a second logic level, different than (e.g., opposite of) its first logic level if any of the outputs 448 of its corresponding CAM cells 442 indicates a mis-match. For example, if its CAM cells 442 indicate a match with a logic high level, the match signal generator 450 might represent an AND gate or a NAND gate. Conversely, if its CAM cells indicate a match with a logic low level, the match signal generator 450 might represent an OR gate or a NOR gate. Note that the first logic level for the output 474 of a match signal generator 450 might be the same as, or different from, the first logic level for the output 448 of a CAM cell 442. Each row 440 of the array of CAM cells 400 might be configured in a same manner as depicted with regard to row 440.sub.0, with each compare logic 446.sub.0 to 446.sub.i connected to its corresponding signal node 454.sub.0 to 454.sub.i, respectively.

(45) Alternatively, the indication of a match signal generator 450 might include a pair of complementary signals, where a first signal of the pair of complementary signals has the first logic level, and the second signal of the pair of complementary signals has the second logic level, if each of the outputs 448 of its corresponding CAM cells 442 indicates a match, and where the first signal of the pair of complementary signals has the second logic level, and the second signal of the pair of complementary signals has the first logic level, if any of the outputs 448 of its corresponding CAM cells 442 indicates a mis-match.

(46) In practice, an address portion for a corresponding defective memory element, e.g., a column of memory cells containing one or more memory cells identified as being defective, might be stored in the CAM cells 442 of a row 440 of the array of CAM cells 400. Each row 440 of the array of CAM cells 400 might store a different address portion, each corresponding to a different defective memory element. It is noted that where a number of identified defective memory elements is less than the number of rows 440 of the array of CAM cells 400, one or more of the rows 440 might not store any address portion, but might instead store values not corresponding to any accessible address. For example, values of all logic low levels or all logic high levels might not correspond to any address to be received on the signal nodes 454. In this manner, a row 440 of the array of CAM cells 400 not corresponding to a defective memory element might be configured to always indicate a mis-match in response to an address received on the signal nodes 454.

(47) Each row 440 storing an address portion might correspond to a respective redundant memory element, and each redundant memory element might have a corresponding address portion outside of the address space, e.g., of the array of memory cells 104, that might be received on the signal nodes 454. For example, assuming i=7, valid addresses to be received from the signal nodes 454 might correspond to an address space contained in 00000000 to 01111111, while addresses for redundant memory elements might correspond to an address space beginning with 10000000. With each row 440 storing a different address portion, or not storing any valid address portion, it might be expected that no more than one output 474 would indicate a match between its stored address portion and the address portion received from the signal nodes 454. In this manner, the output 474 indicating a match might serve to indicate that the redundant memory element corresponding to the row 440 generating that output 474 should be accessed instead of the defective memory element corresponding to the address portion received on the signal nodes 454.

(48) Instead of utilizing an encoder to generate an address of a redundant memory element, various embodiments include selectively-activated storage elements 470, e.g., storage elements 470.sub.0 to 470.sub.1, corresponding to each row 440. The storage elements 470 for a particular row 440 each might be configured to store a value of a respective digit of the address portion of the redundant memory element for that row 440. The storage elements 470 might be responsive to the indication on the output 474 of their corresponding match signal generator 450. For example, the storage elements 470, e.g., storage elements 470.sub.0 to 470.sub.i, each might be configured to generate a signal on its respective output 472, e.g., outputs 472.sub.0 to 472.sub.i, respectively, corresponding to its respective digit of the address portion of the corresponding redundant memory element for that row 440 when the indication on its corresponding output 474 indicates a match for that row 440, and to present a high-impedance, e.g., high Z, when the indication on its corresponding output 474 indicates a mis-match for that row 440. Each output 472.sub.0 to 472.sub.i of one row 440 might be commonly connected to the corresponding outputs 472.sub.0 to 472.sub.i, respectively, of each remaining row 440.

(49) Although the storage elements 470 are depicted to be in close physical proximity to their corresponding CAM cells 442, the storage element 470 could be located away from their corresponding CAM cells 442 provided they are in communication with their corresponding match signal generator 450, and there need not be any connection to the CAM cells 442 themselves.

(50) Programming the storage elements 470 of one or more rows 440 might include accessing (e.g., reading) a particular portion of an array of memory cells 104 storing address portions corresponding to redundant memory elements. As previously noted, testing of a memory might be used to determine which memory elements are deemed to be usable, and which are deemed to be defective. When a memory element is deemed to be defective, an address portion corresponding to that memory element might be stored to a non-volatile storage location of the memory, e.g., the array of memory cells 104. Similarly, a redundant memory element might be assigned to replace the defective memory element. Address portions for the redundant memory elements might be assigned prior to or subsequent to determining addresses of defective memory elements. These address portions might then be accessed during power-up of the memory to program the storage elements 470 accordingly. Alternatively, the address portions for the redundant memory elements might be hard coded into the circuitry as discussed with reference to FIGS. 6A-6C.

(51) FIG. 4B depicts a multiplexer (MUX) 460 used to select the address portion for the redundant memory element if a match is indicated by one of the match signal generators 450 of FIG. 4A, or to select the address portion received on the signal nodes 454 if no match is indicated. The multiplexer 460 is connected to receive the i+1 address signals from the outputs 472[i:0] and to the receive i+1 address signals from the signal nodes 454[i:0]. The multiplexer 460 is responsive to a control signal from control signal node 464 to select the address signals from the signal nodes 454[i:0] for output if no match is indicated, and to select the address signals from the outputs 472[i:0] if a match is indicated. The selected address signals are then provided at an output 462[i:0], e.g., for input to column decode circuitry 110.

(52) For example, the signal received at the control signal node 464 might correspond to an output of an OR gate (not shown) receiving the outputs 472.sub.0 to 472.sub.j as inputs. In this manner, a logic low level from the OR gate might indicate no match in order to select the address signals from the signal nodes 454[i:0], while a logic high level from the OR gate might indicate a match in order to select the address signals from the outputs 472[i:0]. Alternatively, where a particular digit of the address portion represented by the outputs 472[i:0], e.g., the i.sup.th digit from the outputs 472[i:0], has a particular value when a match is indicated, and a different value when no match is indicated, this digit of the address portion could be used as the control signal at the control signal node 464. The i.sup.th digit from the outputs 472[i:0] might correspond to a most significant digit of the address portion.

(53) FIG. 4C depicts a common connection of the outputs 472[i:0] among the storage elements 470 across multiple rows 440. For example, FIG. 4C depicts the output 472.sub.x connected to storage elements 470.sub.x(z−1), 470.sub.xz, and 470.sub.x(z+1), which might correspond to storage elements 470.sub.x for rows 440.sub.z−1, 440.sub.z, and 440.sub.z+1, respectively. With reference to FIG. 4A, x might represent any natural number from 0 to i, and z might represent any natural number from 1 to j−1.

(54) FIG. 4D depicts an output 474.sub.y providing a pair of complementary signals, e.g., on outputs 474.sub.0y and 474.sub.1y, where the output 474.sub.1y is connected to an output of an inverter 475.sub.y that has an input connected to the match signal generator 450.sub.y. With reference to FIG. 4A, y might represent any natural number from 0 to j. In this manner, the output 474.sub.y0 might provide a first signal having its first logic level if each of the outputs 448 of its corresponding CAM cells 442 indicates a match, and having its second logic level if any of the outputs 448 of its corresponding CAM cells 442 indicates a mis-match. Similarly, the output 474.sub.y1 might provide a second signal having its second logic level if each of the outputs 448 of its corresponding CAM cells 442 indicates a match, and having its first logic level if any of the outputs 448 of its corresponding CAM cells 442 indicates a mis-match.

(55) FIG. 5 is a schematic of a CAM cell 442.sub.x and associated storage element 470.sub.x for communication with a match signal generator 450y (e.g., of a row 440y) in accordance with an embodiment. The CAM cell 442.sub.x might represent any CAM cell 442.sub.0 to 442.sub.i of FIG. 4A corresponding to a match signal generator 450.sub.y, where the match signal generator 450.sub.y might represent any match signal generator 450.sub.0 to 450.sub.j of FIG. 4A, for example. For example, with reference to FIG. 4A, x might represent any natural number from 0 to i, and y might represent any natural number from 0 to j.

(56) The CAM cell 442.sub.x might include a register 444.sub.x and a compare logic 446.sub.x. The register 444.sub.x might include a pair of cross-coupled inverters 584.sub.0 and 584.sub.1. The data value stored in the register 444.sub.x might be represented by a logic level at its node 586.sub.0. The compare logic 446.sub.x might include an XOR gate, providing a logic low level at its output 448.sub.x when the data value of the register 444.sub.x is equal to (e.g., has a same logic level as) the signal value received at its corresponding signal node 454.sub.x, and providing a logic high level at its output 448.sub.x when the data value of the register 444.sub.x is different than (e.g., has a different logic level than) the signal value received at its corresponding signal node 454.sub.x.

(57) The register 444.sub.x of FIG. 5 has been simplified by not depicting circuitry for setting and resetting the cross-coupled inverters 584.sub.0 and 584.sub.1, e.g., for storing one data value or another to the register 444.sub.x. However, circuitry for setting or resetting a pair of cross-coupled inverters is well understood in the relevant art, and an example of suitable circuitry is presented in FIG. 6D for a different pair of cross-coupled inverters.

(58) Referring back to FIG. 5, the compare logic 446.sub.x might include a first pFET 576.sub.0 having a first source/drain connected to a voltage node 580.sub.0 and a control gate connected to the node 586.sub.1 of the register 444.sub.x. The voltage node 580.sub.0 might be configured to receive a top-rail supply voltage, such as the supply voltage Vcc. The compare logic 446.sub.x might further include a second pFET 576.sub.1 having a first source/drain connected to a second source/drain of the pFET 576.sub.0, a control gate connected to the signal node 454.sub.x, and a second source/drain connected to the output 448.sub.x.

(59) The compare logic 446x might further include a first nFET 578.sub.0 having a first source/drain connected to a voltage node 582.sub.0 and a control gate connected to the node 586.sub.0. The voltage node 582.sub.0 might be configured to receive a bottom-rail supply voltage, e.g., a reference potential, such as the supply voltage Vss, which might be ground or 0V. The compare logic 446.sub.x might further include a second nFET 578.sub.1 having a first source/drain connected to a second source/drain of the nFET 578.sub.0, a control gate connected to the signal node 454.sub.x, and a second source/drain connected to the output 448.sub.x.

(60) The compare logic 446.sub.x might further include a third pFET 576.sub.2 having a first source/drain connected to a voltage node 580.sub.1 and a control gate connected to the node 586.sub.0 of the register 444.sub.x, and connected to the control gate of the first nFET 578.sub.0. The voltage node 580.sub.1 might be configured to receive a top-rail supply voltage, such as the supply voltage Vcc. The compare logic 446.sub.x might further include a fourth pFET 576.sub.3 having a first source/drain connected to a second source/drain of the pFET 576.sub.2, a control gate connected to an output of an inverter 588 having an input connected to the signal node 454.sub.x, and a second source/drain connected to the output 448.sub.x.

(61) The compare logic 446.sub.x might further include a third nFET 578.sub.2 having a first source/drain connected to a voltage node 582.sub.1 and a control gate connected to the node 586.sub.1, and connected to the control gate of the first pFET 576.sub.0. The voltage node 582.sub.1 might be configured to receive a bottom-rail supply voltage, e.g., a reference potential, such as the supply voltage Vss, which might be ground or 0V. The compare logic 446.sub.x might further include a fourth nFET 578.sub.3 having a first source/drain connected to a second source/drain of the nFET 578.sub.2, a control gate connected to the output of the inverter 588, and a second source/drain connected to the output 448.sub.x.

(62) The storage element 470.sub.x might include a pFET 590 having a first source/drain connected to a voltage node 594, a second source/drain connected to the output 472.sub.x, and a control gate connected to a first control signal node 598.sub.0. The voltage node 594 might be configured to receive a top-rail supply voltage, such as the supply voltage Vcc. The storage element 470.sub.x might further include an nFET 592 having a first source/drain connected to a voltage node 596, a second source/drain connected to the output 472.sub.x, and a control gate connected to a second control signal node 598.sub.1. The voltage node 596 might be configured to receive a bottom-rail supply voltage, e.g., a reference potential, such as the supply voltage Vss, which might be ground or 0V. One of the control signal nodes 598.sub.0 or 598.sub.1 might be configured to receive a control signal indicative of whether its corresponding match signal generator 450.sub.y indicates a match, while the other control signal node 598.sub.1 or 598.sub.0, respectively, might be configured to receive a fixed control signal regardless of whether its corresponding match signal generator 450.sub.y indicates a match. Additional detail will be provided with reference to FIGS. 6A-6D.

(63) FIG. 5 further depicts a bias element 549 that might be connected to the output 472.sub.x. The bias element 549 is depicted as a pull-down resistance, e.g., to discharge a logic high level at the output 472.sub.x to transition its resting state to a logic low level. In particular, a resistance (e.g., resistor) 547 has a first end connected to the output 472.sub.x, and a second end connected to a voltage node 545. The voltage node 545 might be configured to receive a bottom-rail supply voltage, e.g., a reference potential, such as the supply voltage Vss, which might be ground or 0V. Alternatively, the bias element 549 could be a pull-up resistance, e.g., to charge a logic low level at the output 472.sub.x to transition its resting state to a logic high level. For a pull-up resistance, the voltage node 545 might instead be configured to receive a top-rail supply voltage, such as the supply voltage Vcc.

(64) A bias element 549 might be included to restore the logic states of an output 472.sub.x to some known logic level as the output 472.sub.x might be electrically floating if its corresponding storage elements 470 are all at a high impedance state. A bias element 549 might be used on less than all of the outputs 472[i:0]. For example, if a digit of the address portion is used as the control signal to the control signal node 464, e.g., the i.sup.th digit, the corresponding output 472.sub.i might include a bias element 549, while remaining outputs 472.sub.0 to 472.sub.i−1 might not include a bias element 549 as their resting logic state might be inconsequential. If a logic high level of the i.sup.th digit of the address portion indicates a match, and thus a desire to select the address portion for the redundant memory element, the bias element 549 might be a pull-down resistance such that the control signal node 464 would indicate a desire to select the received address portion absent the output 472, being actively driven high by one of its corresponding storage elements 470.sub.i. Alternatively, if a logic low level of the i.sup.th digit of the address portion indicates a match, the bias element 549 might be a pull-up resistance such that the control signal node 464 would indicate a desire to select the received address portion absent the output 472.sub.i being actively driven low by one of its corresponding storage elements 470.sub.i.

(65) FIG. 5 further depicts a selectively-activated inverter 551 having an output connected to the output 472.sub.x and having an input connected to the node 586.sub.1 of the register 444.sub.x. The inverter 551 might be used to read the register 444x, e.g., to provide a signal at the output 472.sub.x having a same logic level as the node 586.sub.0, e.g., representing the data value stored to the register 444.sub.x. The inverter 551 might be responsive to complementary controls signals received on control signal nodes 553.sub.0y and 553.sub.1y. For example, when the control signal node 553.sub.0y has a first logic level and the control signal node 553.sub.1y has a second logic level, different than the first logic level, the inverter 551 might generate a signal at its output having the logic level of the node 586.sub.0, and when the control signal node 553.sub.0y has the second logic level and the control signal node 553.sub.1y has the first logic level, the inverter 551 might be at a high impedance state. The control signal nodes 553.sub.0y and 553.sub.1y might be common for each register 444.sub.x of a row 440.sub.y, thus providing the stored data values for each CAM cell 442 of a row 440.sub.y at the outputs 472[i:0]. The signal at one of the control signal nodes 553.sub.0y or 553.sub.1y might be logically combined with the control signal provided to the node 464 in order to pass the address signals from the outputs 472[i:0] to the outputs 462[i:0] of the multiplexer 460 when either there is a desire to read the registers 444 of a particular row 440, or there is an indication of a match from one of the match signal generators 450.

(66) FIGS. 6A-6D are schematics of storage elements 470.sub.x and corresponding logic for communication with a match signal generator 450.sub.y (e.g., of a row 440.sub.y) in accordance with embodiments. With reference to FIG. 4A, x might represent any natural number from 0 to i, and y might represent any natural number from 0 to y.

(67) The examples of FIGS. 6A and 6B might represent storage element 470.sub.x as hard-wired storage elements storing a logic high level and a logic low level, respectively. The assignment of redundant memory elements to a row 440 of an array of CAM cells 400 might occur prior to fabrication of the memory. As such, the circuitry of the storage elements 470 could be predetermined and simply fabricated to have the connectivity to present a logic high level or a logic low level upon activation.

(68) In the example of FIG. 6A, the first control signal node 598.sub.0 might be in communication with (e.g., connected to) an output 474.sub.0y of a match signal generator 450.sub.y. For such an embodiment, an indication of a match might be represented by a logic low level on the output 474.sub.0y. The second control signal node 598.sub.1 might be connected to a voltage node 657. The voltage node 657 might be configured to receive a bottom-rail supply voltage, e.g., a reference potential, such as the supply voltage Vss, which might be ground or 0V.

(69) With this connectivity, when the output 474.sub.0y indicates a match of its corresponding match signal generator 450.sub.y by presenting a signal having a logic low level, the pFET 590 might be activated while the nFET 592 might be deactivated, thus connecting the output 472x to the voltage node 594. Similarly, if the output 474.sub.0y presents a signal having a logic high level, e.g., indicating a mis-match, both the pFET 590 and the nFET 592 might be deactivated.

(70) In the example of FIG. 6B, the first control signal node 598.sub.0 might be connected to a voltage node 655. The voltage node 655 might be configured to receive a top-rail supply voltage, such as the supply voltage Vcc. The second control signal node 598.sub.1 might be in communication with (e.g., connected to) an output 474.sub.1y of a match signal generator 450.sub.y. For such an embodiment, an indication of a match might be represented by a logic high level on the output 474.sub.1y.

(71) With this connectivity, when the output 474.sub.1y indicates a match of its corresponding match signal generator 450.sub.y by presenting a signal having a logic high level, the nFET 592 might be activated while the pFET 590 might be deactivated, thus connecting the output 472.sub.x to the voltage node 596. Similarly, if the output 474.sub.1y presents a signal having a logic low level, e.g., indicating a mis-match, both the nFET 592 and the pFET 590 might be deactivated.

(72) It should be noted that in the example of FIG. 6A, the nFET 592, voltage node 596 and voltage node 657 could be eliminated from the schematic while providing similar functionality of selectively presenting a logic high level at the output 472.sub.x, and that in the example of FIG. 6B, the pFET 590, voltage node 594 and voltage node 655 could be eliminated from the schematic while providing similar functionality of selectively presenting a logic low level at the output 472.sub.x.

(73) The example of FIG. 6C might represent a storage element 470.sub.x as a read-only storage element. In particular, the first control signal node 598.sub.0 might be connected to an output of a first programmable element 659.sub.0 and to an output of a second programmable element 659.sub.1. The second control signal node 598.sub.1 might be connected to an output of a third programmable element 659.sub.2 and to an output of a fourth programmable element 659.sub.3.

(74) The first programmable element 659.sub.0 might have an input in communication with (e.g., connected to) an output 474.sub.0y of a match signal generator 450.sub.y. For such an embodiment, an indication of a match might be represented by a logic low level on the output 474.sub.0y. The second programmable element 659.sub.1 might have an input connected to a voltage node 655. The voltage node 655 might be configured to receive a top-rail supply voltage, such as the supply voltage Vcc.

(75) The third programmable element 659.sub.2 might have an input in communication with (e.g., connected to) an output 474.sub.1y of a match signal generator 450.sub.y. The fourth programmable element 659.sub.3 might have an input connected to a voltage node 657. The voltage node 657 might be configured to receive a bottom-rail supply voltage, e.g., a reference potential, such as the supply voltage Vss, which might be ground or 0V.

(76) The programmable elements 659.sub.0-659.sub.3 might each be a fuse or antifuse (F/A) element. Such programmable elements are well understood in the relevant art. In particular, a fuse element normally presents a closed circuit between its input and output, while an antifuse element normally presents an open circuit between its input and output. Through the application of appropriate voltage levels to the programmable element, a fuse element can be altered (e.g., permanently altered) to present an open circuit between its input and output, or an antifuse element can be altered (e.g., permanently altered) to present a closed circuit between its input and output.

(77) Programming the storage element 470.sub.x of FIG. 6C to store a logic high level might include programming the first programmable element 659.sub.0 to present a closed circuit, programming the second programmable element 659.sub.1 to present an open circuit, programming the third programmable element 659.sub.2 to present an open circuit, and programming the fourth programmable element 659.sub.3 to present a closed circuit. In this manner, when the output 474.sub.0y indicates a match of its corresponding match signal generator 450.sub.y by presenting a signal having a logic low level, the pFET 590 might be activated while the nFET 592 might be deactivated, thus connecting the output 472.sub.x to the voltage node 594. Similarly, if the output 474.sub.0y presents a signal having a logic high level, e.g., indicating a mis-match, both the pFET 590 and the nFET 592 might be deactivated.

(78) Programming the storage element 470.sub.x of FIG. 6C to store a logic low level might include programming the first programmable element 659.sub.0 to present an open circuit, programming the second programmable element 659.sub.1 to present a closed circuit, programming the third programmable element 659.sub.2 to present a closed circuit, and programming the fourth programmable element 659.sub.3 to present an open circuit. In this manner, when the output 474.sub.1y indicates a match of its corresponding match signal generator 450.sub.y by presenting a signal having a logic high level, the nFET 592 might be activated while the pFET 590 might be deactivated, thus connecting the output 472.sub.x to the voltage node 596. Similarly, if the output 474.sub.1y presents a signal having a logic low level, e.g., indicating a mis-match, both the nFET 592 and the pFET 590 might be deactivated.

(79) The example of FIG. 6D might represent a storage element 470.sub.x as a register-based storage element. In particular, the first control signal node 598.sub.0 might be connected to a first source/drain of a first nFET 661.sub.0 and to a first source/drain of first pFET 663.sub.0. The second control signal node 598.sub.1 might be connected to a first source/drain of a second nFET 661.sub.1 and to a first source/drain of second pFET 663.sub.1.

(80) The first nFET 661.sub.0 might have a second source/drain in communication with (e.g., connected to) an output 474.sub.0y of a match signal generator 450.sub.y. For such an embodiment, an indication of a match might be represented by a logic low level on the output 474.sub.0y. The first pFET 663.sub.0 might have a second source/drain connected to a voltage node 655. The voltage node 655 might be configured to receive a top-rail supply voltage, such as the supply voltage Vcc.

(81) The second pFET 663.sub.1 might have a second source/drain in communication with (e.g., connected to) an output 474.sub.1y of a match signal generator 450.sub.y. The second nFET 661.sub.1 might have a second source/drain connected to a voltage node 657. The voltage node 657 might be configured to receive a bottom-rail supply voltage, e.g., a reference potential, such as the supply voltage Vss, which might be ground or 0V.

(82) The first nFET 661.sub.0, second nFET 661.sub.1, first pFET 663.sub.0 and second pFET 663.sub.1 might each have their control gates in communication with (e.g., connected to) the node 665 of a register 669. The node 665 might be configured to have a logic level corresponding to a data value stored to the register 669. In this example, the register 669 includes a pair of cross-coupled inverters 667.sub.0 and 667.sub.1. The input of the inverter 667.sub.1, and the output of the inverter 667.sub.0, might be connected to a first source/drain of a first nFET 671.sub.0. The first nFET 671.sub.0 might have a second source/drain connected to a first voltage node 673.sub.0, and might have a control gate connected to a first control signal node 675.sub.0. The input of the inverter 667.sub.0, and the output of the inverter 667.sub.1, might be connected to a first source/drain of a second nFET 671.sub.1. The second nFET 671.sub.1 might have a second source/drain connected to a second voltage node 673.sub.1, and might have a control gate connected to a second control signal node 675.sub.1. The voltage nodes 673.sub.0 and 673.sub.1 each might be configured to receive a bottom-rail supply voltage, e.g., a reference potential, such as the supply voltage Vss, which might be ground or 0V.

(83) Programming the storage element 470.sub.x of FIG. 6D to store a logic high level might include momentarily applying a logic high level to the control signal node 675.sub.0 sufficient to develop a logic high level at the node 665, and otherwise maintaining the control signal nodes 675.sub.0 and 675.sub.1 at a logic low level. In this manner, the control signal node 598.sub.0 might be in communication with the output 474.sub.0y and isolated from the voltage node 655, and the control signal node 598.sub.1 might be connected to the voltage node 657 and isolated from the output 474.sub.1y. As such, when the output 474.sub.0y indicates a match of its corresponding match signal generator 450.sub.y by presenting a signal having a logic low level, the pFET 590 might be activated while the nFET 592 might be deactivated, thus connecting the output 472.sub.x to the voltage node 594. Similarly, if the output 474.sub.0y presents a signal having a logic high level, e.g., indicating a mis-match, both the pFET 590 and the nFET 592 might be deactivated.

(84) Programming the storage element 470.sub.x of FIG. 6D to store a logic low level might include momentarily applying a logic high level to the control signal node 675.sub.1 sufficient to develop a logic low level at the node 665, and otherwise maintaining the control signal nodes 675.sub.0 and 675.sub.1 at a logic low level. In this manner, the control signal node 598.sub.0 might be isolated from the output 474.sub.0y and connected to the voltage node 655, and the control signal node 598.sub.1 might be isolated from the voltage node 657 and in communication with (e.g., connected to) the output 474.sub.1y. As such, when the output 474.sub.1y indicates a match of its corresponding match signal generator 450.sub.y by presenting a signal having a logic high level, the nFET 592 might be activated while the pFET 590 might be deactivated, thus connecting the output 472.sub.x to the voltage node 596. Similarly, if the output 474.sub.1y presents a signal having a logic low level, e.g., indicating a mis-match, both the nFET 592 and the pFET 590 might be deactivated.

(85) It should be noted that although the examples of FIGS. 6A-6D utilized an indication of a match signal generator having a pair of complementary outputs 474.sub.0y and 474.sub.1y, an inverter could be added if the indication has only one signal value, in order to convert the logic level of the indication to the appropriate value to selectively activate either the pFET 590 or the nFET 592, depending upon the stored data value.

(86) FIG. 7 is a flowchart of a method of operating a memory in accordance with an embodiment. The method might be in the form of computer-readable instructions, e.g., stored to the instruction registers 128. Such computer-readable instructions might be executed by a controller, e.g., the control logic 116, to cause the memory (e.g., relevant components of the memory) to perform the method. At 701, a received address portion might be compared to a stored address portion. For example, a column address of a memory cell to be accessed might be received at an array of CAM cells, and compared to address portions stored to one or more rows of the array of CAM cells.

(87) At 703, an indication whether a match was detected might be generated. For example, outputs of each row of CAM cells might be provided to a corresponding match signal generator, and each match signal generator might generate an indication whether a match was detected, e.g., whether each of its corresponding CAM cells indicated a match between a respective digit of the stored address portion for that row and a respective digit of the received address portion, or a mis-match was detected, e.g., whether any of its corresponding CAM cells did not indicate a match between a respective digit of the stored address portion for that row and a respective digit of the received address portion.

(88) At 705, a plurality of storage elements might be activated responsive to the indication when a match is detected. For example, each storage element of the plurality of storage elements might present either a signal corresponding to a stored data value when activated, and might present a high-impedance when deactivated. Such activation might be responsive to a logic level of the indication.

(89) At 707, a redundant memory element might be accessed in response to outputs of the activated plurality of storage elements. For example, the outputs of the activated plurality of storage elements might represent an address portion corresponding to a redundant memory element predetermined to be used to replace any access request of a memory element deemed to be defective, and corresponding to the matched received address portion.

CONCLUSION

(90) Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose might be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the embodiments.