Method for fabricating semiconductor structure

Abstract

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Claims

1. A method for fabricating a semiconductor structure, comprising: forming, over a semiconductor substrate, a first gate of a first device and a second gate of a second device, wherein the first device comprises a logic device and the second device comprises an NVM device; forming first LDD regions in the substrate beside the first gate using the first gate as a mask; after the first LDD regions are formed, forming a conformal layer covering top and sidewalls of each of the first gate and the second gate and covering the substrate, wherein the conformal layer has sidewall portions on the sidewalls of the second gate, and comprises a first silicon oxide (SiO.sub.2) layer; forming second LDD regions in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask, wherein an inner border of each of the second LDD regions is positioned between a corresponding one of the sidewalls of the second gate and a sidewall of a corresponding one of the sidewall portions of the conformal layer; forming, after the second LDD regions are formed, a silicon nitride (SiN) layer on the first SiO.sub.2 layer; forming a second SiO.sub.2 layer on the SiN layer; and anisotropically etching the second SiO.sub.2 layer, the SiN layer and the first SiO.sub.2 layer to form an ONO spacer on the sidewalls of the second gate and on sidewalls of the first gate.

2. The method of claim 1, wherein a thickness of the first SiO.sub.2 layer ranges from 30 to 150 .

3. The method of claim 1, wherein the NVM device comprises an NVM cell and a select transistor coupled to the NVM cell.

4. The method of claim 1, wherein the NVM device comprises an NVM cell that has a charge storage layer under the second gate.

5. A method for fabricating a semiconductor structure, comprising: forming, over a semiconductor substrate, a first gate of a first device and a second gate of a second device, wherein the first device comprises a logic device and the second device comprises an NVM device; forming first LDD regions in the substrate beside the first gate using the first gate as a mask; after the first LDD regions are formed, forming a conformal layer covering top and sidewalls of each of the first gate and the second gate and covering the substrate, wherein the conformal layer has sidewall portions on the sidewalls of the second gate, and comprises a first SiO.sub.2 layer and an SiN layer on the first SiO.sub.2 layer; forming second LDD regions in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask, wherein an inner border of each of the second LDD regions is positioned between a corresponding one of the sidewalls of the second gate and a sidewall of a corresponding one of the sidewall portions of the conformal layer; forming, after the second LDD regions are formed, a second SiO.sub.2 layer on the SiN layer; and anisotropically etching the second SiO.sub.2 layer, the SiN layer and the first SiO.sub.2 layer to form an ONO spacer on the sidewalls of the second gate and on sidewalls of the first gate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A to 1D illustrate, in a cross-sectional view, a method for fabricating a semiconductor structure according to a first embodiment of this invention in which the LDD is implanted after the first oxide layer of the ONO spacer is deposited, wherein FIG. 1D also shows the semiconductor structure according to the first embodiment.

(2) FIG. 1B-1 shows an exemplary structure of NVM device in the semiconductor structure in the first embodiment of this invention.

(3) FIG. 2 illustrates a method for fabricating a semiconductor structure according to a second embodiment of this invention in which the LDD is implanted after the nitride layer of the ONO spacer is deposited.

DESCRIPTION OF EMBODIMENTS

(4) This invention will be further explained with the following embodiments and the accompanying drawings, which are however not intended to restrict the scope of this invention. For example, although the first device comprises a logic device and the second device comprises an NVM device in the following embodiments, this invention can be applied to fabrication of any two types of devices for which the distance between the gate and each LDD region of the second-type device is required to be greater than the distance between the gate and each LDD region of the first-type device. In addition, although the spacer is an ONO spacer in the following embodiments, the spacer may alternatively be other kind of composite spacer.

(5) FIGS. 1A to 1D illustrate, in a cross-sectional view, a method for fabricating a semiconductor structure according to the first embodiment of this invention in which the LDD is implanted after the first oxide layer of the ONO spacer is deposited, wherein FIG. 1D also shows the semiconductor structure according to the first embodiment.

(6) Referring to FIG. 1 A, over a semiconductor substrate 100, an under-gate layer 102 is formed on the substrate 100 in an NVM device area 12, and a gate dielectric layer 104 is formed on the substrate 100 in a logic device area 14. The under-gate layer 102 may represent the charge storage layer of the NVM cell in the NVM device area 12, or both of the charge storage layer of the NVM cell and the gate dielectric layer of the select transistor that is also in the NVM device area 12 and coupled to the NVM cell. Then, the gate 106a of the NVM device is formed on the under-gate layer 102 in the NVM device area 12, and the gate 106b of the logic device is formed on the gate dielectric layer 104 in the logic device area 14 usually at the same time. The gate 106a may represent the gate of the NVM cell, or may represent both of the gate of the NVM cell and the gate of the select transistor, as described later.

(7) Thereafter, a patterned photoresist layer 108 is formed covering the NVM area 12, and LDD implantation 110 is performed to form LDD regions 112 in the substrate 100 beside the gate 106b in the logic device area 14, using the patterned photoresist layer 108 and the gate 106b of the logic device as a mask. Each LDD region 112 slightly overlaps with the gate 106b of the logic device due to dopant diffusion.

(8) Referring to FIG. 1B, after the patterned photoresist layer 108 is removed, a substantially conformal silicon oxide (SiO.sub.2) layer 114, which is for forming the first oxide layer of the ONO spacer later, is formed covering the gate 106a of the NVM device, the gate 106b of the logic device, and the substrate 100. The SiO.sub.2 layer 114 has, on the sidewalls of the gate 106a of the NVM device, sidewall portions 1142 that will serve as an implantation mask later. The SiO.sub.2 layer 114 serve as the aforementioned conformal layer in the first embodiment. The thickness of the SiO.sub.2 layer 114 may range from 30 to 150 .

(9) Thereafter, another patterned photoresist layer 116 is formed covering the logic device area 14, and another LDD implantation 118 is performed to form LDD regions 120 in the substrate 100 beside the gate 106a in the NVM device area 12, using the patterned photoresist layer 116, the gate 106a of the NVM device and the sidewall portions 1142 of the SiO.sub.2 layer 114 as a mask. Since the sidewall portions 1142 of the SiO.sub.2 layer 114 also serves as an implantation mask, the distance d.sub.1 between the gate 106a and each LDD region 120 of the NVM device is greater than the distance between the gate 106b and each LDD region 112 of the logic device, wherein the latter distance can be considered as zero because the gate 106b overlaps with each LDD region 112. Meanwhile, due to the dopant diffusion, the inner border 1201 of each LDD region 120 of the NVM device is positioned between the corresponding sidewall 1061 of the NVM gate 106a and the corresponding sidewall 1141 of the SiO.sub.2 layer 114, as indicated by the dash line. The junction depth of the LDD 120 may range from 290 to 1900 .

(10) In a case where the under-gate layer 102 in the NVM device area 12 represents both of the charge storage layer of the NVM cell and the gate dielectric of the select transistor and the gate 106a represents both of the gate of the NVM cell and the gate of the select transistor, an exemplary structure in the NVM device area 12 under the LDD implantation 118 is illustrated in FIG. 1B-1.

(11) Referring to FIG. 1B-1, the NVM device area 12 includes an NVM cell area 12-1 and a select transistor area 12-2. A charge storage layer 102-1 of the NVM cell is formed on the substrate 100 in the NVM cell area 12-1. A gate dielectric layer 102-2 of the select transistor is formed on the substrate 100 in the select transistor area 12-2. The gate 106a-1 of the NVM cell is formed on the charge storage layer 102-1. The gate 106a-2 of the select transistor is formed on the gate dielectric layer 102-2. Both of the gates 106a-1 and 106a-2 are covered by the SiO.sub.2 layer 114 for forming the first oxide layer of an ONO spacer, so that the distance between the gate 106a-1 of the NVM cell and each neighboring LDD region 120, and the distance between the gate 106a-2 of the select transistor and each neighboring LDD region 120 are both greater than the distance (zero) between the gate 106b and each LDD region 112 of the logic device.

(12) The NVM cell to be finished in the area 12-1 will be coupled to the select transistor to be finished in the area 12-2, while sharing an LDD region 120 and a later formed source/drain (S/D) region with the select transistor. In addition, the charge storage layer 102-1 of the NVM cell may include an ONO composite layer including a tunnel SiO.sub.2 layer 1023, a trapping SiN layer 1025 and a blocking SiO.sub.2 layer 1027, from bottom to top, or include a stacked layer including a tunnel SiO.sub.2 layer 1023, a floating gate 1025 and a blocking SiO.sub.2 layer 1027, from bottom to top.

(13) Referring to FIG. 1C, after the LDD regions 120 of the NVM device are formed, a substantially conformal SiN layer 122 for forming the nitride layer of the ONO spacer is formed on the SiO.sub.2 layer 114, and then another substantially conformal SiO.sub.2 layer 124 for forming the second oxide layer of the ONO spacer is formed on the SiN layer 122. The thickness of the SiN layer 122 may range from 150 to 300 . The thickness of the SiO.sub.2 layer 124 may range from 250 to 500 .

(14) Referring to FIG. 1D, the SiO.sub.2 layer 124, the SiN layer 122 and the SiO.sub.2 layer 114 are anisotropically etched to form an ONO spacer 130 on the sidewall of each of the gate 106a in the NVM device area 12 and the gate 106b in the logic device area 14. The ONO spacer 130 includes an L-shaped oxide layer 114a, an L-shaped nitride layer 122a on the sidewall and the bottom of the oxide layer 114a, and a thicker oxide layer 124a on the sidewall and the bottom of the nitride layer 122a. Since the inner border 1201 of each LDD region 120 of the NVM device is positioned between the corresponding sidewall 1061 of the gate 106a of the NVM device and the corresponding sidewall 1141 of the deposited SiO.sub.2 layer 114 in the precedent process, the inner border 1201 is also positioned between the corresponding sidewall 1061 of the gate 106a of the NVM device and the corresponding sidewall 1141 of the oxide layer 114a of the ONO spacer 130 that is formed from the deposited SiO.sub.2 layer 114.

(15) Thereafter, S/D regions 132 of the NVM device are formed in the substrate 100 beside the ONO spacer 130 on the sidewall of the gate 106a of the NVM device in the NVM device area 12, and S/D regions 134 of the logic device formed in the substrate 100 beside the ONO spacer 130 on the sidewall of the gate 106b of the logic device in the logic device area 14.

(16) Though the LDD implantation 118 is performed after the SiO.sub.2 layer 114 for forming the first oxide layer of the ONO spacer is deposited in the first embodiment, it may alternatively be performed after the SiN layer 122 for forming the nitride layer of the ONO spacer is deposited in a second embodiment, as illustrated in FIG. 2. The SiO.sub.2 layer 114 and the SiN layer 122 together serve as the claimed conformal layer in the second embodiment.

(17) Referring to FIG. 2, in the second embodiment, the process of forming the patterned photoresist layer 116 and performing the LDD implantation 118 is moved to after the deposition of the SiN layer 122, so it is the sidewall portions 200 of the combination of the SiO.sub.2 layer 114 and the SiN layer 122 that serve as an additional implantation mask, wherein each sidewall portion 200 is wider than each sidewall portion 1142 of the SiO.sub.2 layer 114 that serves an additional implantation mask in the first embodiment. As a result, the distance d.sub.2 between the gate 106a and each LDD region 120 of the NVM device in the second embodiment is greater than the distance d.sub.1 between the gate 106a and each LDD region 120 of the NVM device in the first embodiment, and is even greater than the distance (zero) between the gate 106b and each LDD region 112 of the logic device.

(18) In addition, due to the dopant diffusion, the inner border 1201 of each LDD region 120 of the NVM device in the second embodiment is positioned between the corresponding sidewall 1141 of the SiO.sub.2 layer 114 and the corresponding sidewall 1221 of the SiN layer 122, as indicated by the dash line.

(19) Since the conformal layer, which may include the first SiO.sub.2 layer (114) for forming an ONO spacer or the combination of the first SiO.sub.2 layer (114) and the SiN layer (122) for forming the same, has sidewall portions (1142 or 200) that also serve as a mask in the LDD implantation of the NVM device in the above embodiments, the opposite LDD regions beside the gate of the NVM device can be pulled back so that their distance is increased and problems such as the short-channel effect are avoided.

(20) This invention has been disclosed above in the embodiments, but is not limited to those. It is known to people of ordinary skill in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.