Digital to analog convertor, failure bit number detector and non-volatile semiconductor storage device

Abstract

An offset voltage V.sub.OFST is compensated in a digital to analog (DA) convertor using a switched-capacitor circuit, including an input circuit, a first differential amplifier, and an offset cancel circuit comprising a second differential amplifier, in a sampling period, when the second feedback circuit is short, an output voltage of the first differential amplifier is input to a first end of a first capacitor, the offset cancel circuit feeds back a reference voltage to an inverting input terminal of the second differential amplifier and a second end of the first capacitor from an output of the second differential amplifier, in a holding period, when the second feedback circuit is not short, the offset cancel circuit inputs a differential voltage between the reference voltage and the output voltage of the first differential amplifier into an inverting input terminal of the first differential amplifier via a second capacitor.

Claims

1. A digital to analog (DA) convertor, comprising a switched-capacitor circuit, the switched-capacitor circuit comprises an input circuit having a plurality of input capacitors relative to a plurality of input digital voltages and a first differential amplifier having a first feedback circuit, wherein the DA convertor is a parallel integrated DA convertor for converting the plurality of input digital voltages into analog voltages, and comprises: an offset cancel circuit comprising a second differential amplifier having a second feedback circuit, wherein in a sampling period, when the second feedback circuit is short, an output voltage of the first differential amplifier is input to a first end of a first capacitor, the offset cancel circuit feeds back a reference voltage to an inverting input terminal of the second differential amplifier and a second end of the first capacitor from an output of the second differential amplifier, in a holding period, when the second feedback circuit is not short, the offset cancel circuit inputs a differential voltage between the reference voltage and the output voltage of the first differential amplifier into an inverting input terminal of the first differential amplifier via a second capacitor, such that an offset voltage of the first differential amplifier is compensated regardless of existence of an offset voltage of the second differential amplifier.

2. A failure bit number detector, comprising the DA convertor according to claim 1, wherein the failure bit number detector is used in a non-volatile semiconductor storage device and comprises: a failure bit detecting number setting circuit connecting to the inverting input terminal of the first differential amplifier, and sets the number of a plurality of third capacitors performing grounding via the plurality of third capacitors to a failure bit detecting number, wherein when the input circuit fails in verification of each memory unit in a memory array of the non-volatile semiconductor storage device, a specified voltage is input into the inverting input terminal of the first differential amplifier via each of the input capacitors, and when the number of failure bit of the memory unit in the memory array of the non-volatile semiconductor storage device is less than the failure bit detecting number, the output voltage of the first differential amplifier is higher than the reference voltage.

3. A non-volatile semiconductor storage device, comprising the failure bit number detector according to claim 2.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram that represents a structural example of a parallel integrated DA convertor of a previous example;

(2) FIG. 2 is a chart that represents a concept of a bit error in the DA convertor in

(3) FIG. 1, and a chart that represents an output voltage V.sub.OUT1 relative to a bit count value;

(4) FIG. 3 is a circuit diagram that represents a structural example of a parallel integrated DA convertor of Embodiment 1;

(5) FIG. 4A is a circuit diagram that represents an action of a differential amplifier 1 in FIG. 3 and a peripheral circuit thereof in a sampling period;

(6) FIG. 4B is a circuit diagram that represents an action of a differential amplifier 1 in FIG. 3 and a peripheral circuit thereof in a holding period;

(7) FIG. 5A is a circuit diagram that represents an action of a differential amplifier 2 in FIG. 3 and a peripheral circuit thereof in a sampling period;

(8) FIG. 5B is a circuit diagram that represents an action of a differential amplifier 2 in FIG. 3 and a peripheral circuit thereof in a holding period;

(9) FIG. 6A is a circuit diagram that represents a structural example of a failure bit number detector for a flash memory in Embodiment 2 and is a circuit diagram that represents an action in a sampling period;

(10) FIG. 6B is a circuit diagram that represents an action of the failure bit number detector in FIG. 6A in a holding period;

(11) FIG. 7 is a setting table of a relationship between the failure bit detecting numbers and a set number S.sub.DETn in the failure bit number detector in FIG. 6A; and

(12) FIG. 8 is a flowchart that represents a programming process of a flash memory using the failure bit number detector in FIG. 6A.

DESCRIPTION OF THE EMBODIMENTS

(13) The following embodiments of the present invention are described by reference to the accompanying drawings. Furthermore, the same symbol is assigned to the same or identical constituent component.

Embodiment 1

(14) FIG. 3 is a circuit diagram that represents a structural example of a parallel integrated DA convertor of Embodiment 1. Compared with the DA convertor in FIG. 1, the DA convertor in FIG. 3 further includes an offset cancel circuit 40.

(15) In FIG. 3, the offset cancel circuit 40 includes a differential amplifier 2, a feedback circuit 2F, a capacitor 6, and a capacitor 8. The feedback circuit 2F contains a switch S.sub.2 and a parallel circuit in which a capacitor 7 has a capacitance C.sub.20. The capacitor 6 has a capacitance C.sub.21, and the capacitor 8 has a capacitance C.sub.22. An output terminal of the differential amplifier 1 is connected to an inverting input terminal of the differential amplifier 2 via a contact a of the switch S.sub.3 and the capacitor 6, and the inverting input terminal of the differential amplifier 2 is connected to the output terminal of the differential amplifier 2 via the feedback circuit 2F. The output terminal is connected to the inverting input terminal of the differential amplifier 1 via the capacitor 8. A specified reference voltage VREF is applied to a non-inverting input terminal of the differential amplifier 2, and the reference voltage VREF is applied to the inverting input terminal of the differential amplifier 2 via a contact b of the switch S.sub.3 and the capacitor 6. Furthermore, a control signal generation circuit 50 generates a control signal for switching the switch S.sub.1 to the switch S.sub.3 and outputs the control signal to control terminals of the switch S.sub.1 to the switch S.sub.3.

(16) Herein, the capacitance C.sub.10 and the capacitance C.sub.22 of the capacitor 5 and the capacitor 8 are set to the same value, and the capacitance C.sub.21 and the capacitance C.sub.20 of the capacitor 6 and the capacitor 7 are set to the same value. Furthermore, the offset voltage of the differential amplifier 1 is set to V.sub.OFST1, and the offset voltage of the differential amplifier 2 is set to V.sub.OFST2.

(17) In this embodiment, the offset voltage V.sub.OFST is corrected in the holding period. Therefore, since the input digital voltage V.sub.INn is a 1-bit logical signal, the output voltage V.sub.OUT1 is represented by the following formula.

(18) [Mathematical Formula 5]

(19) $\begin{array}{cc}{V}_{\mathrm{OUT}1}=\mathrm{VREF}+\frac{C_1}{C_{10}}\left(V_{\mathrm{IN}1}+V_{\mathrm{IN}2}+\mathrm{.Math.}+V_{\mathrm{INn}}\right)& \left(5\right)\end{array}$

(20) FIG. 4A is a circuit diagram that represents an action of a differential amplifier 1 in FIG. 3 and a peripheral circuit thereof in a sampling period. In addition, FIG. 4B is a circuit diagram that represents an action of a differential amplifier 1 in FIG. 3 and a peripheral circuit thereof in a holding period. Herein, FIG. 4 A and FIG. 4B represent a method to compensate the offset voltage V.sub.OFST1.

(21) In the sampling period of FIG. 4A, the switch S.sub.1 is turned on, the voltage V.sub.OUT1-1 is applied to one end of the capacitor 8 via the switch S.sub.1, and the voltage V.sub.OUT2-1 is applied to the other end of the capacitor 8. In this case, the output voltage V.sub.OUT1-1 is represented by the following formula.

(22) [Mathematical Formula 6]
V.sub.OUT1-1=VREF+V.sub.OFST1(6)

(23) Then, in the holding period of FIG. 4B, the switch S.sub.1 is turned off. In this case, the voltage V.sub.OUT2-1 becomes the voltage V.sub.OUT2-2. Therefore, the voltage V.sub.OUT1-2 is represented by the following formula.

(24) [Mathematical Formula 7]

(25) $\begin{array}{cc}{V}_{\mathrm{OUT}1-2}=\mathrm{VREF}+V_{\mathrm{OFST}{1}^{-}}\frac{C_{22}}{C_{10}}\left(V_{\mathrm{OUT}2-1^{-}}{V}_{\mathrm{OUT}2-2}\right)& \left(7\right)\end{array}$

(26) FIG. 5A is a circuit diagram that represents an action of a differential amplifier 2 in FIG. 3 and a peripheral circuit thereof in a sampling period. In addition, FIG. 5B is a circuit diagram that represents an action of a differential amplifier 2 in FIG. 3 and a peripheral circuit thereof in a holding period. FIG. 5A and FIG. 5B represent detailed actions of the differential amplifier 2.

(27) In the sampling period of FIG. 5A, the switch S.sub.2 is turned on, and the switch S.sub.3 is switched to the side of the contact a and connected to the voltage V.sub.OUT1-1. In this case, the voltage V.sub.OUT1-1 is applied to one end of the capacitor 6, and the voltage V.sub.OUT2-1 is applied to the other end of the capacitor 6 via the switch S.sub.2. In this case, the voltage V.sub.OUT2-1 is represented by the following formula.

(28) [Mathematical Formula 8]
V.sub.OUT2-1=VREF+V.sub.OFST2(8)

(29) Then, in the holding period of FIG. 5B, the switch S.sub.2 is turned off, and the switch S.sub.3 is switched to the side of the contact b and connected to the reference voltage VREF. In this case, the voltage V.sub.OUT2-2 is represented by the following formula.

(30) [Mathematical Formula 9]

(31) $\begin{array}{cc}{V}_{\mathrm{OUT}2-2}=\mathrm{VREF}+V_{\mathrm{OFST}{2}^{-}}\frac{C_{21}}{C_{20}}\left(V_{\mathrm{OUT}1-1^{-}}\mathrm{VREF}\right)& \left(9\right)\end{array}$

(32) Here, since C.sub.21=C.sub.20, formula (6) is substituted into formula (9), and then the following formula is obtained.

(33) [Mathematical Formula 10]
V.sub.OUT2-2=VREF+V.sub.OFST2V.sub.OFST1(10)

(34) Further, since C.sub.22=C.sub.10, formula (8) and (10) are substituted into formula (7), and then the following formula is obtained.

(35) [Mathematical Formula 11]
V.sub.OUT1-2=VREF(11)

(36) As specified in formula (11), there is no offset in the output voltage V.sub.OUT1 during the holding period. Moreover, the offset voltage V.sub.OFST2 of the differential amplifier 2 does not affect the action of the differential amplifier 1. In order to correctly feed back the offset voltage V.sub.OFST1, a condition of C.sub.21=C.sub.20 and C.sub.22=C.sub.10 is required. Therefore, the offset voltage V.sub.OFST1 of the differential amplifier 1 can be canceled.

(37) As described above, according to the DA convertor in Embodiment 1, a plurality of input digital voltages, that is, the input digital voltage V.sub.IN1 to the input digital voltage V.sub.INn DA is converted into the output voltage V.sub.OUT1 as analog voltages. Herein, the offset voltage V.sub.OFST1 of the differential amplifier 1 can be cancelled and compensated by the offset cancel circuit 40 having the differential amplifier 2.

Embodiment 2

(38) FIG. 6A is a circuit diagram that represents a structural example of a failure bit number detector for a flash memory in Embodiment 2 and is a circuit diagram that represents an action in a sampling period. FIG. 6B is a circuit diagram that represents an action of the failure bit number detector in FIG. 6A in a holding period.

(39) Compared with the DA convertor in FIG. 3, the failure bit number detector in FIG. 6A and FIG. 6B is different in the following aspects.

(40) (1) The failure bit number detector is used as the input circuit 30; for example, a page buffer 20-1 to a page buffer 20-n that include flash memories are used to replace the input circuit 30.

(41) (2) The failure bit number detector further includes a failure bit detecting number setting circuit 32 that sets a failure bit detecting number and that is connected to the inverting input terminal of the differential amplifier 1.

(42) The failure bit number detector in FIG. 6A and FIG. 6B is a circuit used to check the degree of the failure bit number (detecting the failure bit number) in the program verify of the flash memory.

(43) In the page buffer 20-1, a sensing circuit 11, connected to a bit line of a memory array 10, detects the bit line voltage and outputs the bit line voltage as a sensing voltage SNS, the sensing voltage SNS is applied to one end of a latch LAT1 via a metal oxide semiconductor (MOS) transistor M13 of the switch S.sub.4, and program verify data Q1 is held. Furthermore, when a failure bit is detected, the program verify data Q1 becomes an Low level, and when a failure bit is not detected, the program verify data Q1 becomes an High level (referring to FIG. 6A). The latch LAT1 includes a pair of an inverter 12 and an inverter 13. Inverting data Q.sub.1B of the held program verify data Q1 is output to the inverting input terminal of the differential amplifier 1 via the switch S.sub.5 and the capacitor 4-1 having the capacitance C.sub.1. Herein, in order to convert the inverting data Q.sub.1B of the held program verify data Q.sub.1 into an analog voltage V.sub.OUT1 through the DA convertor, the switch S.sub.5 and the capacitor 4-1 (a component of a part of the input circuit 30) are set. Further, the page buffer 20-2 to the page buffer 20-n are composed in the same manner as the page buffer 20-1, and the inverting data of the held program verify data is output to the inverting input terminal of the differential amplifier 1.

(44) In the failure bit number detector of FIG. 6A and FIG. 6B, in order to set the failure bit detecting number M, the failure bit detecting number setting circuit 32 is provided. The failure bit detecting number setting circuit 32 includes a switch S.sub.6, a switch S.sub.DET1 to a switch S.sub.DETn, and a capacitor 15-0 to a capacitor 15-n. Herein, the capacitor 15-0 has a capacitance 0.5C.sub.1, the other end of the capacitor 15-0 is connected to the source voltage V.sub.DD via the contact a of the switch S.sub.6, and the contact b of the switch S.sub.6 is grounded. In addition, the capacitor 15-1 has a capacitance C.sub.1, the other end of the capacitor 15-1 is connected to the source voltage V.sub.DD by the contact a of the switching S.sub.DET1, and the contact b of the switch S.sub.DET1 is grounded. In the following, similarly, the capacitor 15-n has a capacitance C.sub.1, the other end of the capacitor 15-n is connected to the source voltage V.sub.DD via the contact a of the switch S.sub.DETn, and the contact b of the switch S.sub.DETn is grounded.

(45) Here, the switch S.sub.6 and the capacitor 15-0 are designed to make the output voltage V.sub.OUT1 of the differential amplifier 1 0.5LSB higher than the reference voltage VREF.

(46) FIG. 7 is a setting table of a relationship between the failure bit detecting numbers M and a set number S.sub.DETn in the failure bit number detector in FIG. 6A. As specified in FIG. 7, if the failure bit detecting number is set to M, the (M1) switches S.sub.DET1 to S.sub.DETn are switched to the side of the contact b and are turned on.

(47) If the number of the failure bit m becomes greater than M, then the output voltage V.sub.OUT1 becomes lower than the reference voltage VREF. The flash memory continues the program operation while the output voltage V.sub.OUT1 is lower than the reference voltage VREF.

(48) In the sampling period of FIG. 6A, the switch S.sub.4 is turned on. The sensing circuit 11 senses the voltage of the bit line from the specified memory unit of the memory array 10, and the program verify data of the sensing voltage SNS is transferred to the latch LAT1 via the switch S.sub.4 and is stored. Herein, when the program verify data is an High level, it indicates that verification succeeds; on the other hand, when the program verify data is an Low level, it indicates that verification fails (the number of failure bit m is more than M). Herein, in the DA convertor, the switch S.sub.1 and the switch S.sub.2 are turned on, the switch S.sub.3 is switched to the side of the contact a and connected to the output voltage V.sub.OUT1. The switch S.sub.5 is switched to the side of the contact a and grounded, and the switch S.sub.6 is switched to the side of the contact a and connected to the source voltage V.sub.DD. After it stored the data in the latch LAT1, the DA convertor turns to the holding period.

(49) Then, in the holding period of FIG. 6B, the switch S.sub.1 and switch S.sub.2 are turned off and the switch S.sub.3 is switched to the side of the contact b and connected to the reference voltage VREF. In addition, the switch S.sub.5 is switched to the side of the contact b and connected to the other end of the latch LAT1, and the switch S.sub.6 is switched to the side of the contact b and grounded. When the program verify data that has been stored in the latch LAT1 is an L level and verification fails, the potential at one end (the side of the latch LAT1) of the capacitor 14 in the page buffer 20-1 to the page buffer 20-n changes from 0 V to the source voltage V.sub.DD; on the other hand, LAT1 stores High level, the other end is maintained as 0 V. Therefore, when M1 switches in S.sub.DET1 to S.sub.DETn are set to be turned on, the output voltage V.sub.OUT1 is represented by the following formula.

(50) [Mathematical Formula 12]

(51) $\begin{array}{cc}{V}_{\mathrm{OUT}1}=\mathrm{VREF}+\frac{C_1}{C_{10}}\left\{\left(V_{\mathrm{IN}1+}{V}_{\mathrm{IN}2+\mathrm{.Math.}+}{V}_{\mathrm{INn}}\right)-0.5V_{\mathrm{DD}}-\left(M-1\right)V_{\mathrm{DD}}\right\}& \left(12\right)\end{array}$

(52) Furthermore, when the verification has failed, the input digital voltage V.sub.INn, of the differential amplifier 1 becomes the source voltage V.sub.DD, and when the verification succeeds, the input digital voltage V.sub.INn becomes 0 V.

(53) According to the failure bit number detector as composed in FIG. 6A and FIG. 6B, if the number of failure bit m becomes greater than M, and then the output voltage V.sub.OUT1 becomes lower than the reference voltage VREF. The flash memory continues the program operation while the output voltage V.sub.OUT1 is lower than the reference voltage VREF.

(54) FIG. 8 is a flowchart that represents a programming process of a flash memory using the failure bit number detector in FIG. 6A.

(55) In step S.sub.1 of FIG. 8, in order to program data into the memory unit, it forces to high-voltage. In step S.sub.2 as program verify operation, it verifies if the data is correctly programmed. In step S.sub.3, when the number of failure bit m detected by the failure bit number detector in FIG. 6A is more than the M, return to step S.sub.1 in order to continue the programming action. On the other hand, in step S.sub.3, if the number of failure bit m detected by the failure bit number detector in FIG. 6A is less than the M, the programming process ends.

(56) In the above embodiments, the failure bit number detector for detecting the failure bit number for use in a flash memory is described, but the present invention is not limited thereto, and can be applied to other various non-volatile semiconductor storage devices.

(57) As stated above, according to Embodiment 1 and Embodiment 2, the DA convertor that can compensate the offset voltage V.sub.OFST in the DA convertor using the switched-capacitor circuit can be implemented. In addition, the failure bit number detector for detecting the number of failure bit in a non-volatile semiconductor storage device such as a flash memory can be implemented by using the DA convertor. Further, the failure bit number detector may be included to implement the non-volatile semiconductor storage device such as a flash memory.