Low power oscillator using flipped-gate MOS

Abstract

Relax oscillation circuits have at least one comparison circuit that is structured with a flipped gate transistor and a normal MOS transistor wherein the two transistors having different threshold voltages. The relaxation oscillators are configured for charging and discharging capacitances between the threshold voltages of the flipped gate transistor and the normal MOS transistor by toggling the state of a latching circuit to control the charging and discharging of the capacitances.

Claims

1. A relaxation oscillator comprising: a capacitor having a first plate and a second plate; a trigger circuit connected to the first plate and second plate of the capacitor and configured for monitoring a voltage developed across the capacitor and configured for setting at least one state variable signal for indicating that the voltage developed across the capacitor is less than or greater than a difference between a first trigger voltage and a second trigger voltage, wherein the first trigger voltage is a gate to source threshold voltage of a first transistor and the second trigger voltage is a gate to source threshold voltage of a second transistor, wherein the first transistor is arranged such its gate to source threshold voltage is greater than the gate to source threshold voltage of the second transistor; a toggle circuit configured for selectively providing a charging current to the first plate and from the second plate of the capacitor or the charging current to the second plate and from the first plate of the capacitor for charging or discharging the capacitor according to the at least one state variable signal; and a latch circuit connected to receive the at least one state variable signal and configured for retaining the at least one state variable signal, transferring the at least one state variable signal to the toggle circuit and providing an oscillator output signal.

2. The relaxation oscillator of claim 1 wherein the trigger circuit comprises a first comparator circuit having an inverting input connected to the first plate of the capacitor and a noninverting input and configured for determining that the voltage developed across the capacitor greater than a positive difference between the first trigger voltage and the second trigger voltage; a second comparator circuit having an inverting input connected to the first plate of the capacitor and a noninverting input and configured for determining that the voltage developed across the capacitor less than a negative difference between the first trigger voltage and the second trigger voltage; at least one first voltage source configured for generating the first trigger voltage and having a first terminal connected to the noninverting input of the first comparator and second terminal connected to a reference voltage source; and at least one second voltage source configured for generating the second trigger voltage and having a first terminal connected to the inverting input of the first comparator and the first plate of the capacitor connected to the toggle circuit; wherein the output of the first comparator is connected to a reset terminal of the latch circuit and the output of the second comparator is connected to a set terminal of the latch circuit for transferring the at least one state variable signal to the latch circuit based on the positive and negative differences between the first trigger voltage and the second trigger voltage.

3. The relaxation oscillator of claim 2 further comprising a charging current source configured for generating the charging current for charging the capacitor from the first terminal to the second terminal and from the second terminal to the first terminal.

4. The relaxation oscillator of claim 3 wherein the toggle circuit comprises: a toggling switch having a common terminal connected to the charging current source for receiving the charging current; a normally open terminal connected to the first plate of the capacitor and the inverting terminal of the first comparator for receiving the charging current in the first state; and a normally closed terminal connected to the second plate of the capacitor and to the inverting terminal of the second comparator for receiving the charging current in the second state.

5. The relaxation oscillator of claim 4 wherein when the relaxation oscillator is placed in the first state and the oscillator output signal is deactivated, the voltage developed across the capacitor rises to the positive difference of the first trigger voltage and the second trigger voltage, at which time, a first state variable signal sets the latch and places the relaxation oscillator in the second state and activates the oscillator output signal.

6. The relaxation oscillator of claim 5 wherein when the relaxation oscillator is placed in the second state, the voltage developed across the capacitor falls to the negative difference between the first trigger voltage and the second trigger voltage, at which time, a second variable signal resets the latch and the relaxation oscillator is placed in the first state and the oscillator output changes to the inactive state, and the relaxation oscillator toggles repetitively between the first state and the second state.

7. The relaxation oscillator of claim 1 wherein the first transistor is a flipped gate MOS transistor and the second transistor is a normal MOS transistor.

8. The relaxation oscillator of claim 7 wherein the trigger circuit comprises: a first flipped gate MOS transistor comprising a gate connected to the first plate of the capacitor, a source, and a drain, and having the first gate to source threshold voltage; a second flipped gate MOS transistor comprising a gate connected to the second plate of the capacitor, source, and drain, and having the first gate to source threshold voltage; a first normal MOS transistor comprising a gate and drain connected together to form a first reference voltage source for the second trigger voltage and connected to the gate of the second flipped gate MOS transistor having the second gate to source threshold voltage; a second normal MOS transistor comprising a gate and drain connected together to form a second reference voltage source for the second trigger voltage and connected to the gate of the first flipped gate MOS transistor having the second gate to source threshold voltage; a first current source having a terminal connected to the drain of the first flipped gate MOS transistor for generating a first state variable signal of the at least one state variable signal indicating that a gate voltage of the first flipped gate MOS transistor is greater than the first gate to source threshold voltage; and a second current source having a terminal connected to the drain of the second flipped gate MOS transistor for generating a second state variable signal of the at least one state variable signal indicating that a gate voltage of the first flipped gate MOS transistor is greater than the first gate to source threshold voltage.

9. The relaxation oscillator of claim 8 wherein the toggle circuit comprises: a third current source having a terminal connected for transferring a charging current to the first plate and second plate of the capacitor to selectively charge and discharge the capacitor; a first toggling transistor having a source connected to the terminal of the third current source, a drain connected to the second plate of the capacitor and a gate connected to the latch circuit for receiving the first state variable signal for selectively transferring the charging current to the first plate of the capacitor; a second toggling transistor having a source connected to the terminal of the third current source, a drain connected to the first plate of the capacitor and a gate connected to the latch circuit for receiving the second state variable signal for selectively transferring the charging current to the first plate of the capacitor; a third toggling transistor having a gate connected to the latch circuit for receiving the first state variable signal and configured for selectively transferring the charging current from the first plate of the capacitor; and a fourth toggling transistor having a gate connected to the latch circuit for receiving the second state variable signal and configured for selectively transferring the charging current from the second plate of the capacitor.

10. The relaxation oscillator of claim 9 wherein when the state variable signal signifies a first state where the charging current is transferred to the first plate of the capacitor and from the second plate of the capacitor, such that the capacitor discharges to the second trigger voltage and then charges to the first trigger voltage.

11. The relaxation oscillator of claim 10 wherein when the state variable signal signifies a second state the charging current transferred to the second plate of the capacitor and from the second plate of the capacitor, such that the capacitor discharges to the second trigger voltage and then charges to the first trigger voltage.

12. A relaxation oscillator comprising: a first capacitor and a second capacitor each having a first plate and a second plate; a trigger circuit connected to the first plate and the second plate of the first and second capacitors and configured for monitoring a voltage developed across the first and second capacitors and configured for setting at least one state variable signal for indicating that the voltage developed across the first and second capacitors is less than or greater than a first trigger voltage and a second trigger voltage; a toggle circuit configured for selectively providing a charging current to the first plate and from the second plate of the first capacitor or the charging current to the second plate and from the first plate of the second capacitor for charging or discharging the first and second capacitors according to the at least one state variable signal; and a latch circuit connected to receive the at least one state variable signal and configured for retaining the at least one state variable signal, transferring the at least one state variable signal to the toggling circuit and providing an oscillator output signal.

13. The relaxation oscillator of claim 12 wherein the first trigger voltage is a first gate to source threshold voltage of a first transistor and the second trigger voltage is a second gate to source threshold voltage of a second transistor, wherein the first transistor is arranged such the first gate to source threshold voltage is greater than the second gate to source threshold voltage of the second transistor.

14. The relaxation oscillator of claim 13 wherein the first transistor is a flipped gate MOS transistor and the second transistor is a normal MOS transistor.

15. The relaxation oscillator of claim 14 wherein the trigger circuit comprises: a first flipped gate MOS transistor comprising a gate connected to the first plate of the first capacitor, a source, and a drain, and having the first gate to source threshold voltage; a second flipped gate MOS transistor comprising a gate connected to the second plate of the second capacitor, source, and drain, and having the first gate to source threshold voltage; a first normal MOS transistor comprising a gate connected to the gate of the first flipped gate transistor and the first plate of the first capacitor, a drain connected to the gate of the second flipped gate MOS transistor, a source connected to the second plate of the first capacitor, and having the second gate to source threshold voltage; and a second normal MOS transistor comprising a gate connected to the gate of the second flipped gate transistor, the first plate of the second capacitor and a drain connected to the gate of the first flipped gate MOS transistor, a source connected to the second plate of the second capacitor, and having the second gate to source threshold voltage; a first current source having a terminal connected to the drain of the first flipped gate MOS transistor for generating a first state variable signal of the at least one state variable signal indicating that a gate voltage of the first flipped gate MOS transistor is greater than the first gate to source threshold voltage; a second current source having a terminal connected to the drain of the second flipped gate MOS transistor for generating a second state variable signal of the at least one state variable signal indicating that a gate voltage of the first flipped gate MOS transistor is greater than the first gate to source threshold voltage.

16. The relaxation oscillator of claim 15 wherein the toggle circuit comprises: a third current source having a terminal connected for transferring a charging current to the first plate and second plate of the first and second capacitors to selectively charge and discharge the first and second capacitors; a first toggling switch having a common terminal connected to the terminal of the third current source, a normally closed terminal connected to the first plate of the second capacitor, a normally opened terminal connected to the first plate of the first capacitor and a control terminal connected to the latch circuit for receiving the first state variable signal for selectively transferring the charging current to the first plate of the first and second capacitors; a second toggling switch having a normally opened terminal connected to a source of the first flipped gate MOS transistor, a common terminal connected to a reference voltage source, a control terminal connected to the latch circuit for receiving the second state variable signal for selectively transferring a current from the first current source for generating the first state variable signal; a third toggling switch having a normally opened terminal connected to the second plate of the second capacitor and the source of the first normal MOS transistor, a common terminal connected to the reference voltage source, a control terminal connected to the latch circuit for receiving the first state variable signal for selectively transferring the charging current from the second plate of the first capacitor to the first plate of the second capacitor; a fourth toggling switch having a normally closed terminal connected to a source of the second flipped gate MOS transistor, a common terminal connected to the reference voltage source, a control terminal connected to the latch circuit for receiving the at least one state variable signal for selectively transferring a current from the second current source for generating the second state variable signal of the at least one state variable signal; and a fifth toggling switch having a normally closed terminal connected to the second plate of the second capacitor, a common terminal connected to the reference voltage source, a control terminal connected to the latch circuit for receiving the second state variable signal for selectively transferring the charging current from the second plate of the second capacitor.

17. The relaxation oscillator of claim 16 wherein when the state variable signal signifies a first state where the charging current transferred to the first plate of the first capacitor and discharged from the first plate of the second capacitor, such that the first capacitor charges to the first trigger voltage and the second capacitor discharges to the second trigger voltage.

18. The relaxation oscillator of claim 16 wherein when the state variable signal signifies a second state where the charging current transferred to the first plate of the second capacitor and discharged from the first plate of the first capacitor, such that the second capacitor charges to the first trigger voltage and the first capacitor discharges to the second trigger voltage.

19. The relaxation oscillator of claim 16 wherein the first toggling switch comprises a first toggling transistor having a source connected to the third current source, a drain connected to the drain of the first normal MOS transistor, the first plate of the second capacitor, the gate of the second normal MOS transistor, and the gate of the second flipped gate MOS transistor, and a gate connected to the latch circuit for receiving the first state variable signal for selectively transferring the charging current to the first plate of the second capacitor.

20. The relaxation oscillator of claim 16 wherein the first toggling switch further comprises a second toggling transistor having a source connected to the third current source, a drain connected to the drain of the second normal MOS transistor, the first plate of the first capacitor, the gate of the first normal MOS transistor, and the gate of the first flipped gate MOS transistor, and a gate connected to the latch circuit for receiving the second state variable signal for selectively transferring the charging current to the first plate of the second capacitor.

21. The relaxation oscillator of claim 16 wherein the second toggling switch comprises a third toggling transistor having a drain connected to the source of the first flipped gate MOS transistor, a source connected to the reference voltage source, and a gate connected to the latch circuit for receiving the second state variable signal for selectively transferring a current from the second current source for generating the second state variable signal.

22. The relaxation oscillator of claim 16 wherein the third toggling switch comprises a fourth toggling transistor having a drain connected to the source of the first normal MOS transistor and the second plate of the first capacitor, a source connected to the reference voltage source, and a gate connected to the latch circuit for receiving the second state variable signal for selectively transferring a current from the first plate of the second capacitor and from the second plate of the first capacitor.

23. The relaxation oscillator of claim 16 wherein the fourth toggling switch comprises a fifth toggling transistor having a drain connected to the source of the second flipped gate MOS transistor, a source connected to the reference voltage source, and a gate connected to the latch circuit for receiving the first state variable signal for selectively transferring a current from the first current source for generating the first state variable signal.

24. The relaxation oscillator of claim 16 wherein the fifth toggling switch comprises a sixth toggling transistor having a drain connected to the source of the second normal MOS transistor and the second plate of the second capacitor, a source connected to the reference voltage source, and a gate connected to the latch circuit for receiving the first state variable signal for selectively transferring a current from the first plate of the first capacitor and from the second plate of the second capacitor.

25. A relaxation oscillator comprising: a first capacitor and a second capacitor each having a first plate and a second plate that is connected to a reference voltage source; a trigger circuit connected to the first plate and second plate of the first and second capacitors and configured for monitoring a voltage developed across the first and second capacitors and configured for setting at least one state variable signal for indicating that the voltage developed across the first and second capacitors is less than or greater than a first trigger voltage and a second trigger voltage, wherein the first trigger voltage is a gate to source threshold voltage of a first transistor and the second trigger voltage is a gate to source threshold voltage of a second transistor, wherein the first transistor is arranged such its gate to source threshold voltage is greater than the gate to source threshold voltage of the second transistor; a toggle circuit configured for selectively charging or discharging the first and second capacitors according to the at least one state variable signal; and a latch circuit connected to receive the at least one state variable signal and configured for retaining the at least one state variable signal, transferring the at least one state variable signal to the toggling circuit and providing an oscillator output signal.

26. The relaxation oscillator of claim 25 wherein the first transistor is a flipped gate transistor and the second transistor is a normal MOS transistor.

27. The relaxation oscillator of claim 26 wherein the trigger circuit comprises: a diode connected flipped gate transistor having a gate and drain connected together and a source connected to a reference voltage source; a first current source connected to the gate and drain of the diode connected flipped gate transistor for biasing the diode connected flipped gate transistor for forming a first trigger voltage source; a first normal MOS transistor having a source connected to the first plate of the first capacitor, a gate connected to the gate and drain of the diode connected flipped gate transistor; a second current source connected to drain of the first normal MOS transistor for developing a first state variable signal; a second normal MOS transistor having a source connected to the first plate of the second capacitor, a gate connected to the gate and drain of the diode connected flipped gate transistor; a third current source connected to drain of the second normal MOS transistor for developing a second state variable signal.

28. The relaxation oscillator of claim 27 wherein the toggle circuit comprises: a first normally open switch having a common terminal connected to the source of the first normal MOS transistor and the first plate of the first capacitor, a normally open terminal connected to the reference voltage source, and a gate connected to the latch circuit for receiving the first state variable signal of the at least one state variable signal; a second normally open switch having a common terminal connected to the source of the second normal MOS transistor and the first plate of the second capacitor, a normally open terminal connected to the reference voltage source, and a gate connected to the latch circuit for receiving a second state variable signal of the at least one state variable signal.

29. The relaxation oscillator of claim 28 wherein the first and second normal MOS transistors are turned on for transferring the currents through the first and second normal MOS transistors, when the first state variable signal is deactivated and the second state variable signal is activated, the first normally open switch is closed and the second normally open switch is opened for charging the second capacitor, when the second capacitor charges to the second trigger level, the second normal MOS transistor turns off and the second state variable signal is deactivated and the first state variable signal is activated.

30. The relaxation oscillator of claim 29 wherein the first and second normal MOS transistors are turned on for transferring the currents through the first and second normal MOS transistors, when the first state variable signal is activated and the second state variable signal is deactivated, the first normally open switch is opened and the second normally open switch is closed for charging the first capacitor, when the second first charges to the second trigger level, the first normal MOS transistor turns off and the second state variable signal is activated and the first state variable signal is deactivated.

31. A relaxation oscillator comprising: a capacitor each a first plate and a second plate connected to a reference voltage source; a trigger circuit connected to the first plate configured for monitoring a voltage developed between the first plate of the capacitor and the reference voltage source and configured for setting at least one state variable signal for indicating that the voltage developed between the first plate of the capacitor and the reference voltage source is less than or greater than a first trigger voltage and a second trigger voltage, wherein the first trigger voltage is a gate to source threshold voltage of a first transistor and the second trigger voltage is a gate to source threshold voltage of a second transistor, wherein the first transistor is arranged such its gate to source threshold voltage is greater than the gate to source threshold voltage of the second transistor; a toggle circuit configured for selectively charging or discharging the capacitor according to the at least one state variable signal; and a latch circuit connected to receive the at least one state variable signal and configured for retaining the at least one state variable signal, transferring the at least one state variable signal to the toggling circuit and providing an oscillator output signal.

32. The relaxation oscillator of claim 31 wherein the first transistor is a flipped gate transistor and the second transistor is a normal MOS transistor.

33. The relaxation oscillator of claim 32 wherein the trigger circuit comprises: a flipped gate transistor having a gate connected to the first plate of the capacitor, a source connected to the reference voltage source, and a drain; a biasing current source connected to the drain of the flipped gate transistor for biasing the flipped gate transistor for setting the at least one state variable signal; a normal MOS transistor having a gate connected to the first plate of the capacitor, source connected to the reference voltage source, and a drain connected to the latch circuit.

34. The relaxation oscillator of claim 32 wherein the latch circuit comprises: an inverter circuit having a first input connected to the drain of the flipped gate transistor and the biasing current source for receiving the at least one state variable signal and configured for generating an inverse of the at least one state variable signal that is retained and an output for providing the clock signal that is the at least one state variable signal selecting the charging and discharging of the capacitor; and a gating transistor having a drain connected to the drain of the flipped gate transistor and the biasing current source for holding the at least one state variable signal, a source connected to the drain of the normal MOS transistor for gating the change of the level of the at least one state variable signal.

35. The relaxation oscillator of claim 34 wherein the trigger circuit comprises: a first toggle switch having a drain connected to the first plate of the capacitor, a gate connected for receiving the clock signal, a source; a charging current source connected to the source of the first toggle switch for providing a charging current to the first plate of the capacitor; a second toggle switch having a drain connected to the first plate of the capacitor, a gate connected for receiving the clock signal, a source; and a discharging current sink connected to the source of the first toggle switch for accepting a discharging current from the first plate of the capacitor.

36. The relaxation oscillator of claim 35 wherein when the capacitor is discharged a clock output is to set a level that the first toggle switch is activated and the charging current source is charging the capacitor, when the voltage at the first plate of the capacitor exceeds the second trigger level the normal MOS transistor turns on and when the voltage at the first plate of the capacitor exceeds the first trigger level the flipped gate MOS transistor turns on, the state variable signal is deactivated and the inverter changes the clock signal that deactivates the first toggle switch and activates the second toggle switch and the gating transistor, the capacitor begins to discharge, the flipped gate transistor is turned off and the normal MOS transistor remains turned on, when the voltage across the capacitor reaches the second trigger level, the normal MOS transistor turns off and the state variable is activated and the output of the inverter is deactivated and the cycle repeats continuously.

37. A method for operating a relaxation oscillator: providing a relaxation oscillator comprising: a capacitor having a first plate and a second plate; a trigger circuit connected to the first plate and second plate of the capacitor, a toggle circuit connected to the first and second plates of the capacitor for selectively providing a charging current; a latch circuit connected to the trigger circuit and the toggle circuit; monitoring a voltage developed across the capacitor; setting a state variable signal for indicating that the voltage developed across the capacitor is less than or greater than a difference between a first trigger voltage and a second trigger voltage, wherein the first trigger voltage is a gate to source threshold voltage of a first transistor and the second trigger voltage is a gate to source threshold voltage of a second transistor, wherein the first transistor is arranged such its gate to source threshold voltage is greater than the gate to source threshold voltage of the second transistor; selectively providing a charging current to the first plate and from the second plate of the capacitor or the charging current to the second plate and from the first plate of the capacitor for charging or discharging the capacitor according to the state variable signal; transferring the state variable signal from the latch circuit; retaining by the latch circuit the state variable signal; and transferring the state variable signal to the toggling circuit and providing an oscillator output signal to external circuits.

38. The method of claim 37 wherein the first transistor is a flipped gate transistor and the second transistor is a normal MOS transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1. is a schematic diagram of a relaxation oscillator of the prior art.

(2) FIG. 2a is a cross sectional diagram of a MOS transistor of the related art.

(3) FIG. 2b is a cross sectional diagram of a Flipped-Gate MOS transistor of the related art.

(4) FIGS. 3a and 3b are a state diagrams illustrating the operation of a state machine implementing a relaxation oscillator embodying the principles of the present disclosure.

(5) FIG. 4 is a functional block diagram illustrating the functional structure of a relaxation oscillator embodying the principles of the present disclosure.

(6) FIG. 5a is a simplified schematic diagram of one implementation of a relaxation oscillator embodying the principals of the present disclosure.

(7) FIG. 5b is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 5s embodying the principals of the present disclosure.

(8) FIG. 6a is a schematic diagram of a second implementation of a relaxation oscillator embodying the principals of the present disclosure.

(9) FIG. 6b is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 5 embodying the principals of the present disclosure.

(10) FIGS. 6c-6d are simplified schematics showing the current flow during operation of the relaxation oscillator of FIG. 5 embodying the principals of the present disclosure.

(11) FIG. 7 is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 5 embodying the principals of the present disclosure having mismatched component values.

(12) FIG. 8a is a simplified schematic diagram of a third implementation of a relaxation oscillator embodying the principals of the present disclosure.

(13) FIG. 8b is a detailed schematic diagram of the third implementation of the relaxation oscillator of FIG. 8a embodying the principals of the present disclosure.

(14) FIG. 9a is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 8b embodying the principals of the present disclosure.

(15) FIGS. 9b-9d are simplified schematics showing the current flow during operation of the relaxation oscillator of FIG. 8b embodying the principals of the present disclosure.

(16) FIG. 10a is a schematic diagram of a fourth implementation of a relaxation oscillator embodying the principals of the present disclosure.

(17) FIG. 10b is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 10a embodying the principals of the present disclosure.

(18) FIG. 11a is a schematic diagram of a fifth implementation of a relaxation oscillator embodying the principals of the present disclosure.

(19) FIG. 11b is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 11a embodying the principals of the present disclosure.

DETAILED DESCRIPTION

(20) The relaxation oscillator of this disclosure has a frequency determining capacitor where a voltage swing across the capacitor is defined by two different threshold voltages that differ by the bandgap of the semiconductor material from which the transistors are manufactured. To achieve the differences in the threshold levels, one transistor is a normal transistor manufactured using present materials and fabrication techniques and the second transistor is a flipped gate transistor as described in FIG. 2b.

(21) FIGS. 2a and 2b are a cross sectional diagrams respectively of a MOS transistor and a flipped-gate MOS transistor of the related art. In the related art as shown in FIGS. 2a and 2b, a flipped-gate transistor (FIG. 2b) has a threshold voltage that is greater than the threshold voltage of a normal transistor. The normal transistor is defined is one that employs the standard processing currently in practice and is similar to that shown in FIG. 2a. MOS voltage reference based on polysilicon gate work function difference, Oguey, et al., IEEE Journal of Solid-State Circuits, vol. 15, no. 3, pp. 264-269, June 1980 shows in FIGS. 3a and 3b and reproduced in FIGS. 2a and 2b. Quoting from Oguey et al., FIG. 3a (FIG. 2a of the present disclosure) shows a standard n-channel transistor 5 with an n-type gate 20 and FIG. 3b (FIG. 2b of the present disclosure) modified n-channel transistor 10 with a p-type gate 25 fabricated with a technology that uses doped oxides as diffusion sources. In the standard transistor 5, gate 20, drain 35, and source 40 are surrounded by a phosphorus-doped oxide 15. Source 40 and drain 35 are self-aligned with the gate 20. Effective channel length Leff is gate length minus two lateral diffusion lengths. In the modified transistor, the center part of the gate 25 is p-doped by leaving above it a region of boron-doped oxide 30. This structure behaves like a higher threshold transistor of channel length Leff in series with two short-channel low-threshold transistors. The additional transistors 50 produce a negligible effect in weak inversion, but contribute to a larger change in gate threshold voltage at higher current levels.

(22) FIG. 3a is a state diagram illustrating the operation of a state machine implementing a relaxation oscillator embodying the principles of the present disclosure. In FIG. 3a, the state machine starts in state ST0 with the output of the oscillator OUT being at the activated (1) state. A capacitor (described hereinafter) is charged until the voltage VCAP developed across the capacitor is greater than the positive bandgap (VCAP=BANDGAP) at which time the oscillator output OUT is deactivated (0). The state machine transfers to the state ST1 and the capacitor is discharged until the voltage developed across the capacitor is less than the trigger point V2 (Vth_nch). The capacitor then is charged in an opposite direction until the voltage developed across the capacitor is greater than the trigger point V1 (Vth_FGD). When the capacitor has discharged such that the voltage VCAP developed across the capacitor is less than the negative bandgap (VCAP=BANDGAP), the state machine transfers back to the state ST0. The oscillator output OUT is activated (1) and the capacitor is discharged until the voltage developed across the capacitor is less than the trigger point V2 (Vth_nch). The capacitor then is charged in an opposite direction until the voltage developed across the capacitor is greater than the trigger point V2 (Vth_FGD). The cycle is repeated continuously.

(23) FIG. 3b is a state diagram illustrating the operation of a state machine implementing a relaxation oscillator embodying the principles of the present disclosure. In FIG. 3, the state machine starts in state ST0 with the output of the oscillator OUT being at the activated (1) state. A capacitor (described hereinafter) is charged until the voltage VCAP developed across the capacitor is greater than the trigger point V1 (Vth_FGD) at which time the oscillator output OUT is deactivated (0). The state machine transfers to the state ST1 and the capacitor is discharged until the voltage developed across the capacitor is less than the trigger point V2 (Vth_nch). When the capacitor has discharged such that the voltage VCAP developed across the capacitor is less than the trigger point V2 (Vth_FGD), the state machine transfers back to the state ST0. The oscillator output OUT is deactivated (0) and the capacitor is charged until the voltage developed across the capacitor is greater than the trigger point V1 (Vth_FGD) at which time the oscillator output OUT is deactivated (0). The cycle is repeated continuously.

(24) FIG. 4 is a functional block diagram illustrating the functional structure of a relaxation oscillator embodying the principles of the present disclosure. The relaxation oscillator has a capacitor C having both of its plates connected to a toggle circuit TGL for transferring a charging current from current source ICAP alternately to the first plate and from the second plate of the capacitor C in a first state ST0 and transferring the charging current from the current source ICAP to the second plate and from the first plate of the capacitor C in a second state ST1. The first terminal T1 of the toggle circuit TGL is connected to the first plate of the capacitor C and the second terminal T2 of the toggle circuit TGL is connected to the second plate of the capacitor C.

(25) A latch L1 provides a memory cell for maintaining the state of the relaxation oscillator and providing the oscillator output signal OUT. The first of the inputs of the latch L1 is the indicator for the first state ST0 applied to the reset input R of the latch L1. The second of the inputs is the indicator for the second state ST1 that is applied to the set input S of the latch L1.

(26) The relaxation oscillator has a trigger circuit TGR that has a sense point S1 connected to the first plate of the capacitor C and a sense point S2 connected to the second plate of the capacitor C. The sense points S1 and S2 enable the trigger circuit to determine the voltage VCAP developed across the capacitor. The voltage sources V1 and V2 respectively provide the trigger voltages Vth_FGD and Vth_nch that set the voltage at which the trigger circuit TGR changes the trigger indicator output CMP1 and CMP2 at the outputs of the trigger circuit TGR. In the embodiments of this application the voltage sources V1 and V2 are implemented using a first flipped gate transistor having a threshold voltage that is the trigger voltage Vth_FGD and a normal NMOS transistor having a threshold voltage that is the trigger voltage Vth_nch. In the first state ST0, the trigger indicator output CMP1 is activated (1) and the trigger indicator output CMP2 is deactivated (0). In the second state ST1, the trigger indicator output CMP1 is deactivated (0) and the trigger indicator output CMP1 and CMP2 is activated (1). The set/reset latch changes state according the trigger indicator outputs CMP1 and CMP2.

(27) If the relaxation oscillator implements the state machine of FIG. 3a, when the relaxation oscillator is in the first state ST0, the voltage VCAP across the capacitor C is less than the trigger voltages Vth_FGD and the charging current ICAP is flowing from the first terminal T1 of the toggle circuit TGL to the first plate of the capacitor C and from the second plate of the capacitor C to the second terminal T2 of the toggle circuit When the voltage VCAP across the capacitor C reaches the trigger voltage that is the bandgap voltage that is equal to the difference of the trigger voltages Vth_FGD and Vth_nch, trigger indicator output CMP1 is deactivated (0) and the trigger indicator output CMP2 is activated (1) and the output of the latch L1 is activated (1) the state machine enters the second state ST1. The toggle circuit TGL is then changed such that the charging current ICAP flows from the second terminal T2 to the second plate of the capacitor C and from the first plate of the capacitor C to the first terminal T1 until the voltage VCAP across the capacitor C is greater than the trigger voltage Vth_nch. The capacitor C is then charged in the opposite polarity until voltage VCAP developed across the capacitor C VCAP reaches the trigger voltage that is the negative bandgap voltage that is equal to the negative of the difference of the trigger voltages Vth_FGD and Vth_nch. When the voltage VCAP across the capacitor C reaches the trigger voltage Vth_nch, trigger indicator output CMP1 is activated (1) and the trigger indicator output CMP2 is deactivated (0) and the output of the latch L1 is deactivated (0) the state machine enters the second state ST0. The process repeatedly continues providing the relaxation oscillator with a 50% duty cycle and no kickback to a reference voltage source.

(28) If the relaxation oscillator implements the state machine of FIG. 3b, when the relaxation oscillator is in the first state ST0, the voltage VCAP across the capacitor C is less than the trigger voltages Vth_FGD and the charging current ICAP is flowing from the first terminal T1 of the toggle circuit TGL to the first plate of the capacitor C and from the second plate of the capacitor C to the second terminal T2 of the toggle circuit When the voltage VCAP across the capacitor C reaches the trigger voltage Vth_FGD, trigger indicator output CMP1 is deactivated (0) and the trigger indicator output CMP2 is activated (1) and the output of the latch L1 is activated (1) the state machine enters the second state ST1. The toggle circuit TGL is then changed such that the charging current ICAP flows from the second terminal T2 to the second plate of the capacitor C and from the first plate of the capacitor C to the first terminal T1 as long as the voltage VCAP across the capacitor C is greater than the trigger voltage Vth_nch. When the voltage VCAP across the capacitor C reaches the trigger voltage Vth_nch, trigger indicator output CMP1 is activated (1) and the trigger indicator output CMP2 is deactivated (0) and the output of the latch L1 is deactivated (0) the state machine enters the second state ST0. The process repeatedly continues providing the relaxation oscillator with a 50% duty cycle and no kickback to a reference voltage source.

(29) FIG. 5a is a simplified schematic diagram of one implementation of a relaxation oscillator embodying the principals of the present disclosure according to the state diagram of FIG. 3a. The toggle circuit TGL and the trigger circuit TGR are connected to a first and second plates of the capacitor C.sub.1 as described in FIG. 4. The toggle circuit has a toggle switch S.sub.1 having a normally open terminal NOT connected to the first plate of the capacitor C.sub.1 and a normally closed terminal NCT connected to the second plate of the capacitor C.sub.1. The common terminal CT of the switch S.sub.1 is connected to a first terminal of a capacitor charging current source ICAP. A second terminal of the capacitor charging current source ICAP is connected to a power supply voltage source Vdd. The trigger circuit TGR provides the toggle signal from the clock signal CLK to the control terminal of the switch S.sub.1.

(30) The trigger circuit TGR has a first comparator circuit COMP1 with an inverting input () connected to the first plate of the capacitor C.sub.1 and the normally opened terminal NOT of the switch S.sub.1. A noninverting input (+) of the first comparator COMP1 is connected to a first terminal the first trigger voltage source V.sub.th1 that provides to a threshold voltage Vth_FGD that is equal to that of a flipped gate MOS transistor as described in FIG. 2b. A second terminal of the first trigger voltage source V.sub.th1 is connected to the reference voltage source Vss. A second trigger voltage source V.sub.th2 and provides a threshold voltage Vth_nch that is equal to that of a normal MOS transistor as described in FIG. 2a to the noninverting terminal (+) of the comparator COMP1. A second terminal of the second trigger voltage source V.sub.th2 is connected to the toggle circuit TGL.

(31) The trigger circuit TGR has a second comparator circuit COMP2 with an inverting input () connected to the second plate of the capacitor C.sub.1 and the normally closed terminal NCT of the switch S.sub.1. A noninverting input (+) of the second comparator COMP2 is connected to a first terminal the third trigger voltage source V.sub.th3 that provides to a threshold voltage Vth_FGD that is equal to that of a flipped gate MOS transistor as described in FIG. 2b. A second terminal of the third trigger voltage source V.sub.th3 is connected to the reference voltage source Vss. A fourth trigger voltage source V.sub.th4 and provides a threshold voltage Vth_nch that is equal to that of a normal MOS transistor as described in FIG. 2a to the noninverting terminal (+) of the comparator COMP2. A second terminal of the fourth trigger voltage source V.sub.th2 is connected to the toggle circuit TGL.

(32) The toggle circuit has a second switch S.sub.2 that has its normally closed terminal NCT connected to the second terminal of the second trigger voltage source V.sub.th3. The common terminal CT of the second switch S.sub.2 is connected to the reference voltage source Vss. The toggle circuit has a third switch S.sub.3 that has its normally opened terminal NOT connected to the second terminal of the third trigger voltage source V.sub.th3. The common terminal CT of the second switch S.sub.3 is connected to the reference voltage source Vss.

(33) The output terminal of the first comparator COMP1 provides the trigger indicator output CMP1 to the reset terminal RST of the latch L1 and the output terminal of the second comparator COMP2 provides the trigger indicator output CMP2 to the set terminal SET of the latch L1. The output of the latch L1 is the clock signal CLK that is transferred to external circuits. The control terminals of the switches S1, S2, and S2 are connected output CLK of the latch L1 for toggling the relaxation oscillator between the first state ST0 and the second state ST1 as shown in FIG. 3a.

(34) FIG. 5b is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 5a embodying the principals of the present disclosure. During the time period 0, the latch L1 is placed in the state ST0 and the clock is deactivated (0). The voltage developed across the capacitor C.sub.1 rises to the positive bandgap voltage (+Vth_FGDVth_nch). At which time, the trigger indicator CMP2 sets the latch L1 and the relaxation oscillator is placed in the state ST1 and the clock CLK changes to the active state (1). During the time period 1, the voltage developed across the capacitor C.sub.1 falls to the negative bandgap voltage (Vth_FGDVth_nch). At which time, the trigger indicator CMP1 resets the latch L1 and the relaxation oscillator is placed in the state ST0 and the clock CLK changes to the inactive state (0). During the time period 2, the voltage developed across the capacitor C.sub.1 rises to the positive bandgap voltage (+Vth_FGDVth_nch). At which time, the trigger indicator CMP2 sets the latch L1 and the relaxation oscillator is placed in the state ST1 and the clock CLK changes to the active state (1). This toggling between the state ST0 and the state ST1 continues repeated during the operation of the relaxation oscillator.

(35) FIG. 6a is a schematic diagram of one implementation of a relaxation oscillator embodying the principals of the present disclosure. The relaxation oscillator has a frequency determining capacitor C.sub.1, toggle circuit TGL, and a trigger circuit of FIG. 4. The trigger circuit is connected to a first plate and second plate of the capacitor C.sub.1. The trigger circuit TGR includes a first flipped gate transistor M.sub.FG1 having a threshold voltage that is the trigger voltage Vth_FGD and a first normal NMOS transistor M.sub.3 with a threshold voltage that is the trigger voltage VTH_nch. The first plate of the capacitor C.sub.1 is connected to a gate of the first flipped gate transistor M.sub.FG1 and a gate of the normal NMOS transistor M.sub.5. The trigger circuit TGR is connected to a second plate of the capacitor C.sub.1. The trigger circuit TGR includes a second flipped gate transistor M.sub.FG2 having the threshold voltage that is the trigger voltage Vth_FGD and a normal NMOS transistor M.sub.3 with a threshold voltage that is the trigger voltage Vth_nch. The second plate of the capacitor C.sub.1 is connected to a gate of a second flipped gate transistor M.sub.FG2 and the normal NMOS transistor M.sub.3. As described above, the threshold voltage of the first and second flipped gate transistors M.sub.FG1 and M.sub.FG2 and the threshold voltages of the NMOS transistors M.sub.3 and M.sub.5 are different by a bandgap of a semiconductor material from which the first and second transistors are manufactured. The first threshold voltage is greater than the second threshold voltage because the first and second flipped gate transistor M.sub.FG1 and M.sub.FG2 have the structure as described above in FIG. 2b.

(36) A drain of the first flipped gate transistor M.sub.FG1 is connected for receiving a current from a first current source I1 for providing a comparison signal CMP2. A drain of the second flipped gate transistor M.sub.FG2 is connected for receiving a current from a second current source I2 for providing a comparison signal CMP1. The relaxation oscillator has a set/reset latch L1 formed of the cross-coupled NAND gates N1 and N2. A first input of the NAND gate N1 forms the SET input of the set/reset latch L1 and is connected to receive the comparison signal CMP2. A second input of the NAND gate N1 is connected to an output ST0 of the second NAND gate N2. The first input of the NAND gate N2 is connected to the output ST1 of the first NAND gate N1. The second input of the NAND gate N2 forms the RESET input of the set/reset latch L1 and is connected to receive the comparison signal CMP1.

(37) A current source I.sub.3 provides a capacitor charging current ICAP to the toggle circuit TGL such that the charging current ICAP is selectively transferred to the first plate or the second plate of the frequency determining capacitor C.sub.1 and flows through the frequency determining capacitor C.sub.1 and the diode connected NMOS transistor M.sub.3 and the diode connected NMOS transistor M.sub.5 as selected by the toggle circuit TGL. The charging current ICAP provides a biasing current for diode connected of NMOS transistor M.sub.3 and the diode connected NMOS transistor M.sub.5 as selected by the toggle circuit TGL. The diode connected NMOS transistor M.sub.3 and the diode connected NMOS transistor M.sub.5 establish the second trigger voltage Vth_nch. The toggle circuit TGL is formed of a PMOS transistor P.sub.1, a P-type transistor P.sub.2, an NMOS transistor M.sub.7, and an NMOS transistor M.sub.8. The PMOS transistor P.sub.1 and a P-type transistor P.sub.2 have a source connected to receive the capacitor charging current ICAP. A gate of the PMOS transistor P.sub.1 is connected to receive a reset output signal ST0 from the set/reset latch L1 and a gate of the P-type transistor P.sub.2 is connected to receive a set output signal ST1 from the set/reset latch L1.

(38) A drain of the PMOS transistor P.sub.1 is connected to the second plate of the capacitor C.sub.1 and to a gate and drain of a diode connected of NMOS transistor M.sub.3. A source of the diode connected NMOS transistor M.sub.3 is connected to the drain of the normal NMOS transistor M.sub.4. The sources of the normal NMOS transistor M.sub.4 and the first flipped gate transistor M.sub.FG1 are connected to the drain of the NMOS transistor M.sub.7 of the toggle circuit TGL. The source of the NMOS transistor M.sub.7 is connected to the reference voltage source Vss. The gate of the NMOS transistor M.sub.7 is connected to receive the reset signal ST0.

(39) A drain of the PMOS transistor P.sub.2 is connected to the first plate of the capacitor C.sub.1 and to a gate and drain of a diode connected of NMOS transistor M.sub.5. A source of the diode connected NMOS transistor M.sub.5 is connected to the drain of the normal NMOS transistor M.sub.6. The sources of the normal NMOS transistor M.sub.6 and the first flipped gate transistor M.sub.FG2 are connected to the drain of the NMOS transistor M.sub.8 of the toggle circuit TGL. The source of the NMOS transistor M.sub.8 is connected to the reference voltage source Vss. The gate of the NMOS transistor M.sub.8 is connected to receive the set signal ST1.

(40) FIG. 6b is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 5a embodying the principals of the present disclosure. FIGS. 6b-6d are simplified schematics showing the current flow during operation of the relaxation oscillator of FIG. 6a embodying the principals of the present disclosure. Referring to FIGS. 6b to 6d for a description of the operation of the relaxation oscillator of FIG. 6a, the reset output ST0 of the set/reset latch L1 is activated (1) and the toggle circuit TGL activates the PMOS transistor P.sub.2 and the NMOS transistor M.sub.7 such that the current source I.sub.3 is connected to charge the first plate of the capacitor C.sub.1. The voltage V.sub.XCAP at the first plate of the capacitor C.sub.1 begins to rise when the voltage V.sub.CAP at the second plate of the capacitor C.sub.1 reaches the second trigger voltage Vth_nch and the second plate of the capacitor C.sub.1 is effectively connected to the second threshold voltage Vth_nch as established by the diode connected NMOS transistor M.sub.3. The voltage V.sub.XCAP at the first plate the capacitor C.sub.1 continues to rise until the first flipped gate transistor M.sub.FG1 is turned on. At this moment, the voltage across capacitor C.sub.1 is the difference between first trigger voltage Vth_FG1 and the second trigger voltage Vth_nch (Vth_FG1Vth_nch) that is the bandgap voltage. As noted above, the capacitor charging current ICAP not only charges capacitor C.sub.1 but also provides the bias current to generate the gate to source voltage for the diode connected NMOS transistor M.sub.3 that is the second trigger voltage Vth_nch.

(41) The set input of the set/reset latch L1 is such that the set output ST1 is activated (1) and the reset output ST0 is deactivated (0). The toggle circuit now turns off the PMOS transistor P.sub.2 and the NMOS transistor M.sub.7 and activates the PMOS transistor P.sub.1 and the NMOS transistor M.sub.8. The voltage V.sub.XCAP at the first plate of the capacitor C.sub.1 falls and the voltage V.sub.CAP at the second plate of the capacitor C.sub.1 begins to rise as the current source I.sub.3 is connected to transfer the charging current ICAP to charge the second plate of the capacitor C.sub.1.

(42) The voltage V.sub.CAP at the second plate of the capacitor C.sub.1 rises and the second plate of the capacitor C.sub.1 begins to rise when the voltage V.sub.XCAP at the second plate of the capacitor C.sub.1 reaches the second threshold voltage Vth_nch. The voltage V.sub.CAP at the second plate the capacitor C.sub.1 continues to rise until the second flipped gate transistor M.sub.FG2 is turned on. The reset input of the set/reset latch L1 is such that the reset output ST0 is activated (1) and the set output ST1 is deactivated (0). The toggle circuit now turns off the PMOS transistor P.sub.2 and the NMOS transistor M.sub.7 and turns on the PMOS transistor P.sub.1 and the NMOS transistor M.sub.8. The voltage V.sub.CAP at the second plate of the capacitor C.sub.1 falls and the voltage V.sub.XCAP at the first plate of the capacitor C.sub.1 begins to rise as the current source I.sub.3 is connected to transfer the current ICAP to charge the first plate of the capacitor C.sub.1. At that time, the current source I.sub.3 is connected to charge the first plate of the capacitor C.sub.1 as described above.

(43) The oscillator will toggle from one operation mode to the other continually with a fixed 50% duty cycle based on the value of the current source I3 and the capacitor C.sub.1. FIG. 7 is a plot showing the voltage V.sub.XCAP at the first plate of the capacitor C.sub.1, voltage V.sub.XCAP at the first plate of the capacitor C.sub.1, and the reset output ST0 of the set/reset latch L1 during operation of the relaxation oscillator of FIG. 5 embodying the principals of the present disclosure having mismatches in the threshold voltages of the transistors. The plot shows that the threshold voltage Vth_FG1 of the first flipped gate transistor M.sub.FG1 is greater than the threshold voltage Vth_FG2 of the second flipped gate transistor M.sub.FG2. Similarly, the plot shows that the threshold voltage Vth_N5 of the NMOS transistor M.sub.5 is greater than the threshold voltage Vth_N3 of the NMOS transistor M.sub.3. Even with these mismatches, the output ST0 of the relaxation oscillator maintains a 50% duty cycle during operation.

(44) FIG. 8a is a simplified schematic diagram of a third implementation of a relaxation oscillator embodying the principals of the present disclosure. This implementation of the relaxation oscillator has two frequency determining capacitors C.sub.1 and C.sub.2, toggle circuit TGL, and a trigger circuit TGR of FIG. 4. The toggle circuit TGL is formed of the toggle switch S.sub.1, the normally closed switches S.sub.2 and S.sub.4, and the normally open switches S.sub.3 and S.sub.5.

(45) The gate-source capacitance of a first and second normal NMOS transistors M.sub.1 and M.sub.2 may be used as the two frequency determining capacitors C.sub.1 and C.sub.2 rather than a separate, dedicated capacitor component. The trigger circuit TGR is connected to a first plate of the capacitor C.sub.1 and to a first plate of the capacitor C.sub.2. The trigger circuit TGR includes a flipped gate transistor M.sub.FG1 having a threshold voltage that is the trigger voltage Vth_FGD and a normal NMOS transistor M.sub.1 with a threshold voltage that is the trigger voltage Vth_nch. The trigger circuit includes a flipped gate transistor M.sub.FG2 having the threshold voltage that is the trigger voltage Vth_nch and a normal NMOS transistor M.sub.2 with the threshold voltage that is the trigger voltage Vth_nch.

(46) The gate of the first flipped gate transistor M.sub.FG1 is connected to the gate of a normal NMOS transistor M.sub.1 and to a first plate of a first frequency determining capacitor C.sub.1. A second plate of the capacitor C.sub.1 is connected to a source of the NMOS transistor M.sub.1. A drain of the flipped gate transistor M.sub.FG1 is connected to a first terminal a first current source I1 for receiving a first current. The second terminal of the current source I1 is connected to a power supply voltage source Vdd. The drain of the flipped gate transistor M.sub.FG1 and the first terminal of the current source I1 are connected to a set terminal SET of a set/reset latch L1. The source of the flipped gate transistor M.sub.FG1 is connected to a normally open terminal NOT of the switch S.sub.2. The source of the NMOS transistor M.sub.1 and the second plate of the capacitor C.sub.1 is connected to a normally closed terminal NCT of the S.sub.3. The drain of the NMOS transistor M.sub.1 is connected to a connected to a normally closed terminal NCT of the toggling switch S.sub.1.

(47) The gate of the second flipped gate transistor M.sub.FG2 is connected to the gate of a normal NMOS transistor M.sub.2 and to a first plate of a second frequency determining capacitor C.sub.2. A second plate of the capacitor C.sub.2 is connected to a source of the NMOS transistor M.sub.2. A drain of the flipped gate transistor M.sub.FG2 is connected to a first terminal a second current source I2 for receiving a second current. The second terminal of the current source I2 is connected to a power supply voltage source Vdd. The drain of the flipped gate transistor M.sub.FG2 and the first terminal of the current source I1 are connected to a reset terminal RST of a set/reset latch L1. The source of the flipped gate transistor M.sub.FG2 is connected to a normally closed terminal NCT of the switch S.sub.5. The source of the NMOS transistor M.sub.2 and the second plate of the capacitor C.sub.2 is connected to a normally closed terminal NCT of the S.sub.4. The drain of the NMOS transistor M.sub.2 is a connected to a normally open terminal NOT of the toggling switch S.sub.1. The gate of the NMOS transistor M.sub.2 and the first plate of the capacitor C.sub.2 are connected to the drain of the NMOS transistor M.sub.1 and the normally closed terminal NCT of the switch S.sub.1. The gate of the NMOS transistor M.sub.1 and the first plate of the capacitor C.sub.1 are connected to the drain of the NMOS transistor M.sub.2 and the normally open terminal NOT of the switch S.sub.1. The common terminals of the switches S.sub.2, S.sub.3, S.sub.4 and S.sub.5 are is connected to the reference voltage source Vss.

(48) A current source I3 provides a capacitor charging current ICAP to the common terminal CT of the toggling switch S.sub.1. The control terminal for each of the switches S.sub.1, S.sub.2, S.sub.3, S.sub.4 and S.sub.5 is connected to the output signal CLK of the set/reset latch L1. When the output signal CLK of the set/reset latch L1 is in its deactivated state (0), the toggling switch S.sub.1 is connected such that the capacitor charging current ICAP is applied to the drain of the NMOS transistor M.sub.1, to the gate of the NMOS transistor M.sub.2, and to the first plate of the capacitor C.sub.2. Similarly, When the output signal CLK of the set/reset latch L1 is in its deactivated state (0), the switches S.sub.2 and S.sub.3 are opened and the switches S.sub.4 and S.sub.5 are closed such that the sources of the flipped gate transistor M.sub.FG2, NMOS transistor M.sub.2 and the second plate of the capacitor C.sub.2 are connected to the reference voltage source Vss. The sources of the flipped gate transistor M.sub.FG1, NMOS transistor M.sub.1 and the second plate of the capacitor C.sub.1 are disconnected and floating.

(49) When the output signal CLK of the set/reset latch L1 is in its activated state (1), the toggling switch S.sub.1 is connected such that the capacitor charging current ICAP is applied to the drain of the NMOS transistor M.sub.2, to the gate of the NMOS transistor M.sub.1, and to the first plate of the capacitor C.sub.1. Similarly, When the output signal CLK of the set/reset latch L1 is in its activated state (1), the switches S.sub.2 and S.sub.3 are closed and the switches S.sub.4 and S.sub.5 are open such that the sources of the flipped gate transistor M.sub.FG1, NMOS transistor M.sub.1 and the second plate of the capacitor C.sub.1 are connected to the reference voltage source Vss. The sources of the flipped gate transistor M.sub.FG2, NMOS transistor M.sub.1 and the second plate of the capacitor C.sub.2 are disconnected and floating.

(50) FIG. 8b is a detailed schematic diagram of the second implementation of the relaxation oscillator of FIG. 8a embodying the principals of the present disclosure. The structure and function of the relaxation oscillator of FIG. 8b is identical to that of FIG. 8a. The toggle circuit TGL of FIG. 8b performs the function of the toggling switch S.sub.1 of FIG. 8a. The set/reset latch L1 in FIG. 8b has two output ST1 and ST0 that have opposite states for the states for the states of the input signals CMP1 and CMP2. The switches S.sub.2, S.sub.3, S.sub.4 and S.sub.5 of the toggle circuit TGL are respectively implemented by the NMOS transistors M.sub.3, M.sub.4, M.sub.5, and M.sub.6. The reset signal ST0 is connected to the gates of the NMOS transistors M.sub.3 and M.sub.4 and the set signal ST1 is connected to the gates of the NMOS transistors M.sub.5, and M.sub.6. Thus, the NMOS transistors M.sub.3 and M.sub.4 are conducting as the normally closed switches S.sub.2 and S.sub.3 in the reset state (the output signal ST0=1 and ST1=0) and the NMOS transistors M.sub.5 and M.sub.6 are not conducting as the normally closed switches S.sub.4 and S.sub.5 in the reset state (the output signal ST0=1 and ST1=0). In the set state (the output signal ST0=0 and ST1=1), the NMOS transistors M.sub.3 and M.sub.4 are not conducting as the normally closed switches S.sub.2 and S.sub.3 in the set state and the NMOS transistors M.sub.5 and M.sub.6 are conducting as the normally closed switches S.sub.4 and S.sub.5 in the set state.

(51) The relaxation oscillator has a trigger circuit TGR that is connected to a first plate of the capacitor C.sub.1 and to a first plate of the capacitor C.sub.2. The second plates of the capacitors C.sub.1 and C.sub.2 are connected to the sources of the NMOS transistors M.sub.1 and M.sub.2.

(52) As described above the trigger circuit TGR includes a flipped gate transistor M.sub.FG1 having a threshold voltage that is the trigger voltage VTH_FGD and a normal NMOS transistor M.sub.1 with a threshold voltage and a normal NMOS transistor having a threshold voltage that is the trigger voltage VTH_nch. The first plate of the capacitor C.sub.1 is connected to a gate of the flipped gate transistor M.sub.FG1 and a gate of the NMOS transistor M.sub.1. The trigger circuit TGR includes a flipped gate transistor M.sub.FG2 having the threshold voltage that is the trigger voltage VTH_FGD and a normal NMOS transistor M.sub.1 with the threshold voltage that is the trigger voltage VTH_nch.

(53) FIG. 9a is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 8b embodying the principals of the present disclosure. FIGS. 9b-9d are simplified schematics showing the current flow during operation of the relaxation oscillator of FIG. 8b embodying the principals of the present disclosure. Referring to FIGS. 8b, 9a, and 9b, the circuit of FIG. 8b is initialized in the set state with the output signal ST0 being activated (1) and the output signal ST1 being deactivated (0). The PMOS transistor P1 is turned off and the PMOS transistor P2 is turned on. The NMOS transistors M.sub.3 and M.sub.4 are turned on and the NMOS transistors M.sub.5 and M.sub.6 are turned off. The charging current ICAP flows through the PMOS transistor P2 to charge the first plate of the first capacitor C.sub.1 such that the voltage V.sub.XCAP increases from the threshold voltage Vth_nch of the NMOS transistor M.sub.2 to the threshold voltage Vth_FGD of the flipped gate transistor M.sub.FG1. The flipped gate transistor M.sub.FG1 turns on and the current from the current source I1 flows through the flipped gate transistor M.sub.FG1 to the reference voltage source Vss. The second comparison signal CMP2 drops to cause the reset input RST of the set/reset latch L1 to reset and the reset output ST0 to be placed at a deactivated state (0).

(54) The set output ST1 of the set/reset latch L1 is activated (1) to turn off the PMOS transistor P2. With the reset output ST0 to be placed at a deactivated state (0), the PMOS transistor P1 is turned on such that the charging current ICAP flows through the PMOS transistor P1 to charge the first plate of the capacitor C.sub.2 such that the voltage V.sub.CAP increases from the threshold voltage Vth_nch of the NMOS transistors M.sub.2 to the threshold voltage Vth_FGD of the flipped gate transistor M.sub.FG2. The charge on capacitor C.sub.1 flows through the NMOS transistor M.sub.2 and the NMOS transistors M.sub.5 to the reference voltage source Vss to discharge the capacitor C.sub.1 until the voltage across capacitor C.sub.1 has decreased to the voltage level of the threshold voltage Vth_nch as shown in FIG. 7c. Referring to FIG. 7d, the NMOS transistor M.sub.1 is turned off. The capacitor charging current ICAP charges the capacitor C.sub.2 and when the voltage V.sub.CAP at the first plate of the capacitor C.sub.2 reaches the threshold voltage Vth_FGD of the flipped gate transistor M.sub.FG2, the flipped gate transistor M.sub.FG3 turns on and the current from the current source I2 flows through the flipped gate transistor M.sub.FG3 to the reference voltage source Vss. The first comparison signal CMP1 drops to cause the set input SET of the set/reset latch L1 to set and the set output ST1 to be placed at a deactivated state (0) and the reset output ST0 is placed at the activated state (1). At this time, the cycle as described above repeats itself continuously.

(55) FIG. 10a is a schematic diagram of a fourth implementation of a relaxation oscillator embodying the principals of the present disclosure. The relaxation oscillation circuit has two frequency determining capacitors C.sub.1 and C.sub.2, a trigger circuit TGR, and a toggle circuit TGL. The trigger circuit TGR, and a toggle circuit TGL are connected to a first plate of the capacitors C.sub.1 and C.sub.2. The trigger circuit TGR includes a flipped gate transistor M.sub.FG1 having a first threshold voltage that is the trigger voltage Vth_FGD and a first normal NMOS transistor M.sub.11 and a second normal NMOS transistor M.sub.12 with a threshold voltage that is the trigger voltage Vth_nch. The gate and drain of the flipped gate transistor M.sub.FG1 are connected to form a diode. The gate and drain of the diode connected flipped gate transistor M.sub.FG1 are connected to the first terminal of the current source I1. The gate and drain of the diode connected flipped gate transistor M.sub.FG1 are further connected to the gates of the normal NMOS transistor M.sub.11 and the normal NMOS transistor M.sub.12 to generate the trigger voltage Vth_FGD that is applied to the gates of the normal NMOS transistors M.sub.11 and M.sub.12.

(56) The drain of the normal NMOS transistor M.sub.11 is connected to a first terminal of the current source I.sub.2. The drain of the normal NMOS transistor M.sub.12 is connected to a first terminal of the current source I.sub.3 and the set input SET of the set/reset latch L1. The toggle circuit TGL includes the switches S.sub.1 and S.sub.2. The source of the normal NMOS transistor M.sub.11 is connected to the common terminal of the switch S.sub.1. The source of the normal NMOS transistor M.sub.12 is connected to the common terminal of the switch S.sub.2.

(57) The second terminals of the current sources I1, I2 and I3 are connected to the power supply voltage source Vdd. The normally open terminals of the switches S.sub.1 and S.sub.2 are connected to the reference voltage source Vss.

(58) The set/reset latch L1 is formed of the cross-coupled NAND gates N1 and N2. A first input of the NAND gate N1 forms the set input SET of the set/reset latch L1. The input of the Schmitt trigger inverter SINV1 is connected to receive the comparison signal CMP2 from the junction of the drain of the NMOS transistor M.sub.11 and the first terminal of the current source I2 and the output of the Schmitt trigger SINV1 is connected to transfer the inverted comparison signal CMP2 to the set input SET of the set/reset latch L1. A second input of the NAND gate N1 is connected to an output ST0 of the second NAND gate N2. The first input of the NAND gate N2 is connected to the output ST1 of the first NAND gate N1. The second input of the NAND gate N2 forms the reset input RST of the set/reset latch L1. The input of the Schmitt trigger inverter SINV2 is connected to receive the comparison signal CMP1 from the junction of the junction of the drain of the NMOS transistor M.sub.12 and the first terminal of the current source I3 and the output of the Schmitt trigger SINV2 is connected to transfer the inverted comparison signal CMP1 to the reset input RST of the set/reset latch L1. The reset output ST0 of the set/reset latch L1 is connected to the control terminal of the switch S1 of the toggle circuit TGL and the set output ST1 of the set/reset latch L1 is connected to the control terminal of the switch S.sub.2 of the toggle circuit TGL. The Schmitt trigger inverters SINV1 and SINV2 have a threshold that prevents a false trigger upon receiving the two comparison signals CMP1 and CMP2.

(59) FIG. 10b is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 10a embodying the principals of the present disclosure. During the time period 1, the relaxation oscillator is initialized. During the time period 2, the switch S.sub.1 is opened and the voltage V.sub.C1 at first plate of the capacitor C.sub.1 begins to rise as the capacitor C.sub.1 charges to the voltage of the bandgap voltage (BANDGAP=VTH_FGDVTH_nch). With the NMOS transistor M.sub.11 turned on, the voltage of the second comparison signal CMP1 is placed at essentially the voltage level of the capacitor voltage VC.sub.1. Also, during the time period 2, the NMOS transistor M.sub.12 is turned on and the voltage of the second comparison signal CMP2 is placed at essentially the voltage level of the reference voltage level Vss. Thus, placing the reset signal ST0 at the activated state (1) and placing the set signal ST1 at the deactivated state (0). When capacitor voltage VC.sub.1 reaches to trigger voltage VTH_nch, NMOS transistor M.sub.11 turns off and comparison signal CMP1 is activated (1), the set input SET of the latch L1 is set to an activated state (1). The reset output signal ST0 is activated (1) and the set output signal ST1 is deactivated (0). The switch S.sub.2 is opened and the switch S.sub.1 is closed. The capacitor C.sub.1 discharges to the voltage level of the reference voltage source Vss and the capacitor C.sub.2 begins to charge.

(60) During the time period 3, the switch S.sub.1 is closed and the voltage VC.sub.1 at first plate of the capacitor C.sub.1 discharges. With the NMOS transistor M.sub.11 turned on, the voltage of the second comparison signal CMP1 is placed at essentially the voltage level of the reference voltage source Vss. The switch S.sub.2 is opened and the voltage V.sub.C2 at first plate of the capacitor C.sub.2 rises as the capacitor C.sub.1 charges to the bandgap voltage (BANGAP=VTH_FGDVTH_nch). With the NMOS transistor M.sub.12 turned on, the voltage of the comparison signal CMP2 is placed at essentially the voltage level of the capacitor voltage VC.sub.2. When capacitor voltage VC.sub.2 reaches to trigger voltage VTH_nch, NMOS transistor M.sub.12 turns off and comparison signal CMP2 is activated (1), the set input SET of the latch L1 is set to an activated state (1). The set output signal ST1 is activated (1) and the reset output signal ST0 is deactivated (0). The switch S.sub.2 is closed and the switch S.sub.1 is open. The capacitor C.sub.2 discharges to the voltage level of the reference voltage source Vss and the capacitor C.sub.1 begins to charge to the bandgap voltage. The cycle as described for the time period 2 is repeated for the time period 4 and time period 6. The time period 3 is repeated for the time period 5. The cycles as described are continue continuously.

(61) FIG. 11a is a schematic diagram of a fifth implementation of a relaxation oscillator embodying the principals of the present disclosure. The relaxation oscillation circuit has trigger circuit TGR, a toggle circuit TGL, and a frequency determining capacitors C.sub.1. The trigger circuit TGR includes a flipped gate transistor M.sub.FG1 having a first threshold voltage that is the trigger voltage Vth_FGD and a normal NMOS transistor M.sub.13 with a second threshold voltage that is the trigger voltage Vth_nch. The trigger circuit TGR is structured such that the gates of the flipped gate transistor M.sub.FG1 and the normal NMOS transistor M.sub.13 are connected to a first plate of the capacitor C.sub.1 and the toggle circuit TGL and thus to the drains of the toggling PMOS transistor P.sub.15 and toggling NMOS transistor M.sub.15. The toggle circuit TGL includes the toggling PMOS transistor P.sub.15, the toggling NMOS transistor M.sub.15, the current source I1, and the current sink I2. The source of the toggling PMOS transistor P.sub.15 is connected to a first terminal of the current source I1 and the source of the NMOS transistor M.sub.15 is connected to the first terminal of a current sink I2. The second terminal of the current source I1 is connected to the power supply voltage source Vdd and the second terminal of the current sink I2 is connected reference voltage source Vss. The drain of the flipped gate transistor M.sub.FG1 is connected to a second terminal of a biasing current source I3, the drain of the NMOS transistor M.sub.14, and the input of the inverter INV.sub.1. The second terminal of the biasing current source I3 is connected to the power supply voltage source Vdd. The output of the inverter INV.sub.1 forms the clock output CLK of the relaxation oscillator. The clock output CLK is connected to the gates of the NMOS transistor M.sub.14, the toggling PMOS transistor P.sub.15, and the toggling NMOS transistor M.sub.15. The source of the NMOS transistor M.sub.14 is connected to the drain of the normal NMOS transistor M.sub.13. The sources of the flipped gate transistor M.sub.FG1 and the normal NMOS transistor M.sub.13 are connected to the reference voltage source Vss.

(62) FIG. 11b is a plot showing signals at various points during operation of the relaxation oscillator of FIG. 11a embodying the principals of the present disclosure. Upon initialization, the flipped gate transistor M.sub.FG1 and the normal NMOS transistor M.sub.13 are turned off and the comparison signal CMP1 is forced to a high level (1). The output of the inverter I1 is placed at the low level (0), thus forcing the toggling transistor M.sub.15 to turn off and turning on the toggling transistor P.sub.15. The current from the current source I1 starts to charge the capacitor C.sub.1 from the threshold voltage Vth_N.sub.13 of the NMOS transistor M.sub.13 to the threshold voltage Vth_FGD of the flipped gate transistor M.sub.FG1 during the time period 1. When voltage VC.sub.1 reaches the threshold voltage Vth_FGD of the first flipped gate transistor M.sub.FG1, the first flipped gate transistor M.sub.FG1 turns on and the comparison signal CMP1 is forced to a low level (0). The output of the inverter I1 is placed at the high level (1), thus forcing the toggling NMOS transistor M.sub.15 to turn on and turning off the toggling PMOS transistor P.sub.15. The gating NMOS transistor M.sub.14 is turned on and the current from the current source I3 flows through the NMOS transistor M.sub.14 and NMOS transistor M.sub.13. The voltage across the capacitor C.sub.1 is less than the threshold voltage Vth_FGD of the flipped gate transistor M.sub.FG1, thus turning off the flipped gate transistor M.sub.FG1 during the time period 2. When the voltage across the capacitor C.sub.1 is less than the threshold voltage Vth_N13 of the NMOS transistor M.sub.13, the NMOS transistor M.sub.13 turns off and the comparison signal CMP1 forced to a high level at the end of the time period 2.

(63) The time periods 3 and 5 are the same at that of the time period 1 and the time period 4 is the same as the time period 2. The toggling between the states of time period 1 and the time period 2 continues during the operation of the relation oscillator.

(64) In all the implementations of the relaxation oscillator, as described above, the comparison of the threshold voltages of the flipped gate transistors with the normal transistors eliminates the separate reference voltage source VREF of FIG. 1. Thus, any kickback noise is eliminated.

(65) It will be noted that the difference between the threshold voltage of the flipped gate transistors and the threshold voltage of the NMOS transistors of the above implementations is approximately the band gap voltage of the semiconductor material in which the devices are manufactured. In these implementations, the semiconductor material is preferably silicon, however any material having a suitable bandgap such as germanium, gallium arsenide, etc. may be used.

(66) While this disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure. For instance, the NMOS flipped gate transistors having a first threshold voltage and the normal NMOS transistors with a second threshold voltage may be implemented as PMOS transistors. Any PMOS transistors may be implemented as N-MOS transistors.