MEMS sensors

Abstract

This application relates to methods and apparatus for operating MEMS sensors, in particular MEMS capacitive sensors (C.sub.MEMS) such as a microphones. An amplifier apparatus is arranged to amplify an input signal (V.sub.INP) received at a sense node from the MEMS capacitive sensor. An antiphase signal generator generates a second signal (V.sub.INN) which is in antiphase with the input signal (V.sub.INP) and an amplifier arrangement is configured to receive the input signal (V.sub.INP) at a first input and the second signal (V.sub.INN) at a second input and to output corresponding amplified first and second output signals. This converts a single ended input signal effectively into a differential input signal.

Claims

1. An amplifier apparatus for amplifying an input signal from a MEMS capacitive sensor comprising: a sense node for receiving the input signal; an antiphase signal generator for generating a second signal which is in antiphase with the input signal; and an amplifier arrangement configured to receive the input signal at a first input and the second signal at a second input and to output corresponding first and second output signals, wherein the amplifier arrangement comprises a first single-ended amplifier for amplifying the input signal, and wherein the first amplifier comprise an input transistor with a gate terminal connected to the sense node and a bootstrap circuit for driving a drain terminal of the input transistor in phase with the first output signal.

2. An amplifier arrangement as claimed in claim 1 further comprising biasing circuitry for generating a bias voltage for biasing the MEMS capacitive sensor at a biasing node wherein the amplifier arrangement is configured to modulate the bias voltage at the bias node with a modulation signal based on the second signal.

3. An amplifier arrangement as claimed in claim 2 comprising a feedback path for feeding the second signal or the second output signal back to the biasing node.

4. An amplifier arrangement as claimed in claim 3 wherein said feedback path comprises a biasing capacitor.

5. An amplifier apparatus as claimed in claim 1 wherein the antiphase signal generator generates the second signal based on a common-mode voltage of the first and second output signals.

6. An amplifier apparatus as claimed in claim 1 wherein the antiphase signal generator comprises a feedback amplifier configured to receive a common-mode signal indicative of a common mode voltage of the first and second output signals and a common-mode reference voltage and to drive the second signal at the second input of amplifier arrangement to keep the common mode voltage of the first and second output signals to be equal to the common-mode reference voltage.

7. An amplifier apparatus as claimed in claim 6 comprising first and second resistances connected in series between a first output node driven with the first output signal and a second output node driven with the second output signal, wherein the common-mode signal is derived from the midpoint of the first and second resistances.

8. An amplifier apparatus as claimed in claim 6 comprising a common-mode reference generator for generating the common-mode reference voltage based on an input reference voltage, wherein the common-mode reference generator comprises a transistor which is a scaled replica of an input transistor of the amplifier arrangement.

9. An amplifier apparatus as claimed in claim 1 wherein the antiphase signal generator comprises an inverting amplifier configured to receive the input signal from the sense node.

10. An amplifier apparatus as claimed in claim 1 wherein the amplifier arrangement further comprises a second single-ended amplifier for amplifying the second signal.

11. An amplifier apparatus as claimed in claim 1 comprising an input bypass switch for connecting the first input of the amplifier arrangement to the second input.

12. An amplifier apparatus as claimed in claim 1 further comprising clamp controller for selectively controlling the input bypass switch to clamp the input signal within a defined voltage range.

13. An amplifier apparatus as claimed in claim 12 wherein the clamp controller is configured to monitor at least one of the input signal, the first output signal and the second output signal against a clamp limit.

14. An amplifier arrangement as claimed in claim 11 wherein the apparatus is configured to close said input bypass switch in response to a start-up control signal.

15. An amplifier arrangement as claimed in claim 2 wherein said biasing circuitry comprises a voltage source for outputting the bias voltage and a resistance between the voltage source and the biasing node and comprising a biasing bypass switch for providing a bypass path that bypassing the resistance between the voltage source and the biasing node.

16. An amplifier arrangement as claimed in claim 15 wherein the voltage source is also configured to generate a control voltage, the control voltage being higher than the bias voltage, wherein the biasing circuitry is configured such that, in normal operation the control voltage is applied to a gate terminal of the biasing bypass switch.

17. An amplifier apparatus for amplifying an input signal from a MEMS capacitive sensor comprising: a sense node for receiving the input signal; an antiphase signal generator for generating a second signal which is in antiphase with the input signal; and an amplifier arrangement configured to receive the input signal at a first input and the second signal at a second input and to output corresponding first and second output signals, wherein the amplifier apparatus further comprises an input bypass switch for connecting the first input of the amplifier arrangement to the second input.

18. An amplifier apparatus for amplifying an input signal from a MEMS capacitive sensor comprising: a sense node for receiving the input signal; an antiphase signal generator for generating a second signal which is in antiphase with the input signal; and an amplifier arrangement configured to receive the input signal at a first input and the second signal at a second input and to output corresponding first and second output signals, wherein the amplifier arrangement further comprises biasing circuitry for generating a bias voltage for biasing the MEMS capacitive sensor at a biasing node wherein the amplifier arrangement is configured to modulate the bias voltage at the bias node with a modulation signal based on the second signal, wherein said biasing circuitry comprises a voltage source for outputting the bias voltage and a resistance between the voltage source and the biasing node and comprising a biasing bypass switch for providing a bypass path that bypassing the resistance between the voltage source and the biasing node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates one example of a MEMS sensor arrangement;

(2) FIG. 2 illustrates a MEMS sensor arrangement according to an embodiment;

(3) FIGS. 3a and 3b illustrate MEMS sensor arrangements according to other embodiments;

(4) FIG. 4 illustrates the example of FIG. 3a in more detail;

(5) FIGS. 5a, 5b and 5c illustrate examples of various LNA implementations without and with bootstrapping;

(6) FIG. 6 illustrates one example for generating a common mode reference;

(7) FIG. 7 illustrates an amplifier arrangement with voltage clamping;

(8) FIGS. 8a and 8b illustrate example of biasing circuitry; and

(9) FIG. 9 illustrates an amplifier arrangement with gain.

DETAILED DESCRIPTION

(10) FIG. 1 illustrates one example of a MEMS sensor arrangement 100 for operation of a MEMS capacitive sensor, such as a MEMS microphone. The MEMS microphone is illustrated as a variable capacitance C.sub.MEMS. A first electrode or plate of the MEMS sensor C.sub.MEMS is biased with a biasing voltage V.sub.BIAS from a voltage source 101. The voltage source 101 may, for instance be a charge-pump, which may boost an input voltage, to the defined bias voltage V.sub.BIAS. The bias voltage V.sub.BIAS may be applied to the first electrode via filter arrangement comprising resistance 102 (for instance comprising polysilicon diodes) and a biasing capacitor C.sub.BIAS to provide a stable biasing voltage for the transducer.

(11) A second plate or electrode of the MEMS capacitive transducer C.sub.MEMS is coupled to a reference voltage V.sub.REF via a high impedance element 103, which may for instance be in the order of gigaohms or so. High impedance element 103 may for instance comprise polysilicon diodes or similar.

(12) The capacitance of the MEMS sensor C.sub.MEMS is typically only of the order of 1 pf or so, and so the sense signal received at a sense node 104 connected to the second plate requires local buffering/amplification. A voltage amplifier 105 may thus be arranged to generate a buffered voltage output. The amplifier 105 may present a high input impedance, so the charge on the MEMS capacitance remains constant. The voltage at a sense node 104 connected to the second plate thus varies inversely proportional to the capacitance, which itself is inversely proportional to the plate separation, so overall the detected voltage V.sub.IN is dependent on the displacement of the plates of the MEMS capacitive sensor C.sub.MEMS. Pressure waves cause displacement of the plates of the MEMS capacitive sensor C.sub.MEMS which results in a voltage variation V.sub.SIG which is detected as the input voltage V.sub.IN from the sense node and amplified by amplifier 105.

(13) In the example illustrated in FIG. 1 the amplifier 105 is configured to provide a differential output signal, i.e. outputs of V.sub.OUTP and V.sub.OUTN which vary inversely from one another to provide a differential voltage that varies with the input signal V.sub.IN. The amplifier 105 thus also receives the voltage reference V.sub.REF. Providing a differential output signal can improve noise performance by increasing the power-supply-rejection-ratio (PSRR) of the MEMS sensor arrangement. A differential output has a benefit because the maximum differential output signal is 2Vdd minus headroom. Compared with a single ended input, single ended output LNA however, there is a noise penalty caused by the extra input device in this example.

(14) In the arrangement illustrated in FIG. 1 the maximum input signal that can be amplified linearly is limited by the input range of amplifier 105, e.g. the power supply voltage VDD minus sufficient headroom. There is an increasing demand for microphones to be able to operate in noisy environments or environments with large low frequency components such as wind noise without distorting and thus there is a general desire to improve the linear operating range of the microphone arrangement, i.e. to improve overload performance by being able to cope with a high input sound pressure level without clipping.

(15) The operating range of the amplifier may be increased by increasing the supply voltage but this would increase power consumption, which is undesirable, especially for portable devices which operate off battery power and where battery life is an important consideration. An increased supply voltage would also result in increased supply noise if for example a DCDC converter was used to boost the supply voltage.

(16) Dynamic range has been extended by using the techniques of compression to vary the sensitivity of the microphone, for instance by reducing the bias voltage V.sub.BIAS for larger amplitude acoustic signals so as to reduce the voltage of the signal V.sub.IN at the sense node. However this results in the overall response of the microphone being non-linear or time-varying or subject to transient artefacts as V.sub.BIAS is changed which may be undesirable in some implementations.

(17) In embodiments of the present disclosure an input voltage signal is received from the MEMS sensor and an additional signal which is in antiphase to the input signal is generated. The input signal and generated antiphase signal can be used to provide a differential output signal. In some embodiments the input signal and generated antiphase signal may be used as differential inputs, e.g. for a differential amplifier arrangement. Thus the input signal is used to provide a first output signal and a complementary second output signal that varies inversely with the first output signal is derived. In effect the single-ended input signal is converted to a differential signal with two antiphase signal components. This extends the input range of the amplifier from being equal to the supply voltage less headroom to being double the supply voltage less headroom. Thus the operating range of the amplifier is improved, without requiring any increase in supply voltage or negative impact on PSRR.

(18) FIG. 2 illustrates an amplifier arrangement 200 according to one embodiment where similar components to those already discussed are identified by the same reference numerals. In this embodiment an antiphase signal generator is configured to generate an antiphase signal from the measurement signal at the sense node. In this embodiment the antiphase signal generator comprises an inverting amplifier 201 coupled to the sense node 104. The inverting amplifier 201 is coupled to the signal path between the sense node 104 and amplifier 105. The inverting amplifier 201 may present a high impedance input, like the amplifier 105, and thus the MEMS sensor may operate in a constant charge mode as described above. The voltage signal from the sense node 104 may be used as a first input signal V.sub.INP for amplifier 105. The inverting amplifier 201 also generates a signal V.sub.INN which is complementary and inverted version of the signal V.sub.INP, i.e. an antiphase signal. The antiphase signal V.sub.INN is provided as a second input signal to the amplifier 105 and is also coupled to the bias capacitor C.sub.BIAS. This signal V.sub.INN is thus coupled through the C.sub.BIAS capacitor to the first plate of the MEMS sensor C.sub.MEMS. The voltage variation V.sub.SIG due to a variation of the separation of the plates or electrodes of MEMS sensor C.sub.MEMS is thus imposed on the inverted signal V.sub.INN with a result that V.sub.SIG becomes the differential voltage between the two input signals V.sub.INP and V.sub.INN. As such each input signal V.sub.INP and V.sub.INN is half the magnitude, for a given signal voltage variation V.sub.SIG, compared to the single-ended input version described with reference to FIG. 1.

(19) The differential input signal level is thus equal to V.sub.INPV.sub.INN and has substantially double the input range compared to the single-ended input signal V.sub.IN.

(20) This increase in linear operating range not only increases the range of sound pressure level (SPL) that can be detected accurately, but the increased operating range available may allow for a greater freedom in the design of various system parameters such as transducer sensitivity and amplifier gain, which can allow for a reduction in overall noise.

(21) However the inverting amplifier 201 will itself be an additional source of noise which can introduce noise into the output signal.

(22) FIG. 3a illustrates another embodiment in which an antiphase signal generator generates the antiphase signal from a common mode output feedback signal. In this embodiment a first single-ended low-noise amplifier (LNA) 301 receives the signal from the sense node 104 as a first input signal V.sub.INP and amplifies this signal to provide the output signal V.sub.OUTP. A second single-ended LNA 302 is arranged to amplify the generated antiphase signal V.sub.INN to provide an output signal V.sub.OUTN. The two outputs are connected on either side of resistances 303 and the midpoint voltage between these resistances is tapped as a common-mode voltage. Amplifier 304 is arranged in a feedback path between the common-mode tap point and the input to the LNA 302. Amplifier 304 receives the feedback common-mode voltage and a reference V.sub.CMREF. This feedback path, in effect, tries to maintain the common-mode voltage to be a constant value based on V.sub.CMREF. Amplifier 304 may be relatively high gain amplifier and thus drives the output V.sub.OUTN of LNA 302 to be the inverse of the output of LNA 301 so as to maintain the common-mode voltage. Thus the output V.sub.OUTN of LNA 302 is complementary to and the inverse of, i.e. in antiphase, the output V.sub.OUTP from LNA 301. The common-mode feedback amplifier 304 can thus be seen as the antiphase signal generator.

(23) The output voltage signal V.sub.OUTN is fed back to the first plate MEMS sensor C.sub.MEMS via the capacitance C.sub.BIAS in a similar fashion as described above with reference to FIG. 2 in order that the voltage variation V.sub.SIG appears as a differential voltage V.sub.INPV.sub.INN.

(24) Any noise introduced by LNA 302 is suppressed through the action of the feedback path including the common-mode feedback amplifier 304. That is, the LNA 302 in FIG. 3a is within a feedback loop for the common-mode feedback amplifier 304. In some implementations this may relax the requirements on size and/or current of LNA 302 for a desired noise performance. In some embodiments there may not be a need for LNA 302 to amplify or buffer the generated antiphase signal. FIG. 3b illustrates an embodiment similar to that illustrated in FIG. 3a but where the LNA 302 is omitted. The output of the common-mode feedback amplifier 304 drives the negative signal path and thus the antiphase signal V.sub.INN may be used to provide the output signal V.sub.OUTN without requiring any buffering etc.

(25) Where the LNA 301 for the first input signal V.sub.INP comprises a PMOS follower, a level shift block 306 may be provided to level shift the generated antiphase signal down to the input DC bias voltage level for DC biasing purposes.

(26) The common-mode feedback amplifier 304 may thus be used to generate an antiphase signal which may drive, substantially directly, a second signal path for the antiphase signal output, e.g. the output of the common-mode feedback amplifier 304 may be directly coupled to an input node of the amplifier arrangement for the antiphase signal. In some instances an LNA or buffer 302 or may be included in the second signal path for the antiphase signal, within the feedback loop for the common-mode feedback amplifier 304, but in some instance buffering of the antiphase signal generated by common-mode feedback amplifier 304 may not be necessary.

(27) Noise introduced by the common-mode feedback amplifier 304 and/or arising on the reference V.sub.CMREF will appear as common mode noise only and may be readily rejected by downstream components receiving the output signals V.sub.OUTP and V.sub.OUTN, e.g. an audio codec or the like.

(28) Note that the embodiment illustrated in FIG. 3a shows two single-ended LNAs 301 and 302 as providing the functionality of a differential-input/differential-output amplifier arrangement 305. In some embodiments a differential amplifier could be used instead of the two LNAs 301 and 302, although the suppression of noise associated with V.sub.OUTN may not be as good.

(29) FIG. 4 illustrates one example of how the embodiment of FIG. 3a may be implemented in more detail, showing just the amplifier arrangement 400. The LNAs 301 and 302 are each implemented comprising PMOS source followers, with Class-AB output drivers 401 and 402 respectively arranged to close the feedback loops to drive the outputs V.sub.OUTP and V.sub.OUTN. The use of Class-AB output drivers 401 and 402 to close the feedback loops provides a super source follower configuration which improves linearity and drive strength.

(30) There is however a secondary noise effect due to the capacitance of the gate-drain of the PMOS 403 of the LNA 301 as illustrated with respect to FIG. 5a. LNA 302, if present, does not create this effect due to the low impedance at V.sub.INN.

(31) FIG. 5a illustrates the LNA 301 implemented as a super-source follower, thus including additional MOS 501, and also including the Class-AB output driver 401 discussed above. FIG. 5a illustrates the gate-drain capacitance of the PMOS 403 as a separate capacitance C.sub.GD for explanation. It can be seen that this gate-drain capacitance C.sub.GD is effectively connected in series with the capacitance of the MEMS sensor C.sub.MEMS and thus these two capacitances form a potential divider. Any common-mode noise at the drain with respect to the gate of PMOS 403 will thus be seen as a signal component at the gate, which will thus be represented in the output signal V.sub.OUTP. In contrast, the gate-drain capacitance C.sub.GD of LNA 302 does not form a capacitive potential divider with the input sensor so it does not convert common mode noise to an input signal. Thus common mode noise may be converted to noise in the differential signal.

(32) To mitigate this effect the drain of the PMOS 403 may be bootstrapped to the output signal as illustrated in FIG. 5b. In this embodiment the gate of MOS 501 is driven by the output signal, possibly after some level shift voltage V.sub.LS is applied for optimising the voltage headroom. This results in a signal, which is in-phase with the input signal, being applied to the drain of PMOS 403 which eliminates the conversion of common-mode noise to the input signal.

(33) This also has the effect of making the input capacitance of the LNA 301 to appear to be nil, which reduces signal attenuation and can allow a larger PMOS to be used than otherwise would be the case, with a resultant reduction in flicker noise. The input signal V.sub.INP would also suffer less attenuation as C.sub.GD is typically the dominant load capacitance.

(34) FIG. 5c illustrates the LNA 301 implemented as a super-source follower in a similar fashion as illustrated in FIG. 5a, thus including additional MOS 501 and also including the Class-AB output driver 401 discussed above. The embodiment of FIG. 5c includes a cascade device 502 which is driven with a level-shifted version of the output signal, e.g. a version of the output signal derived from the output and appropriately level shifted by level-shifter 503. This arrangement of FIG. 5c helps avoid imposing thermal or flicker noise onto the drain node of PMOS 403 which may be advantageous in some applications.

(35) The reference voltage V.sub.CMREF for the common-mode feedback amplifier 304 may be generated in any convenient way. FIG. 6 illustrates that reference voltage V.sub.CMREF may be generated from an input reference V.sub.REF-IN using a replica PMOS 601 which is a scaled down copy of the input PMOS 403. The input reference V.sub.REF-IN may be some suitable reference, for instance a bandgap derived reference voltage.

(36) In some embodiments the input signal, i.e. V.sub.INP, may be voltage clamped so as to avoid the input signal, and hence the output signals, exceeding a defined voltage level. FIG. 7 illustrates an embodiment with voltage clamping.

(37) In this embodiment the output signals V.sub.OUTP and V.sub.OUTN are monitored by clamp controller 702. Monitoring the output signal avoids the need for monitoring to be directly applied to sense node 104 and thus avoids additional leakage and capacitive loading of this node, however in other embodiments the clamp controller could monitor the signal V.sub.INP and/or the derived antiphase signal V.sub.INN. Clamp controller effectively monitors the output signals against a clamp limit CL. Given that the output signals V.sub.OUTP and V.sub.OUTN are complementary signals both signals can be compared to a single clamp limit to provide both clamping for positive and negative voltage excursions. Thus a high positive voltage excursion may lead V.sub.OUTP to go above a positive clamp limit or V.sub.OUTN to drop below a negative clamp limit. Likewise a high negative voltage excursion could result in V.sub.OUTN going above the positive clamp limit or V.sub.OUTP to drop below the negative clamp limit.

(38) In the event that either output signal exceeds the clamp limit a control signal is generated to turn on a bypass switch 701. The bypass switch provides a bypass path between the inputs for V.sub.INP and V.sub.INN that avoids the high impedance element 103. Clamp current may thus flow through the switch 701 from the V.sub.INP node to the V.sub.INN node if V.sub.OUTN exceeds the clamp limit and from V.sub.INN node to the V.sub.INP node if V.sub.OUTP exceeds the clamp limit. In this embodiment the bypass switch 701 is implemented by two series connected NMOS devices 701a and 701b with p-wells connected to the mid-point, rather than ground, to reduce leakage. The clamp controller 702 may comprise an amplifier with moderate gain to avoid stability issues.

(39) The bypass switch 701 may also be used at start-up of the sensor arrangement to allow for rapid charging of the sensor apparatus to the operating voltages/charge levels and thus avoid the long time constants associated with the high impedance element 103. A start-up control 703 may thus be responsive to a start-up signal SU to activate the bypass switch 701.

(40) Using the bypass switch 701 for both rapid start-up and also for voltage clamping also reduces the number of components connected to the sense node 104, compared with separate bypass and clamping arrangements, and thus also helps to reduce leakage and loading at the sense node 104.

(41) There may also be a start-up bypass switch associated with the voltage biasing path for biasing the first plate of the MEMS sensor C.sub.MEMS. The bypass switch associated with the biasing path may provide a bypass path across impedance 102. As noted above however in embodiments of the present disclosure the biasing node for biasing the MEMS sensor C.sub.MEMS may, in use, experience a signal component, e.g. V.sub.INN or V.sub.OUTN which is fed back via the biasing capacitor C.sub.BIAS. This can impact on the operation of a bypass switch.

(42) FIG. 8a illustrates one example of a biasing arrangement with a suitable biasing bypass switch 801. In this example the biasing bypass switch 801 may comprise series connected PMOS devices providing a bypass path across impedance 102. The voltage source 101, e.g. a charge pump, provides, in normal operation, the bias voltage V.sub.BIAS via impedance 102. To ensure that the bypass switch remains turned off in normal operation, given the signal component applied to the biasing node via the biasing capacitor C.sub.BIAS, the voltage source may also provide a voltage V+ which is higher than the bias voltage V.sub.BIAS and which is applied to the gate(s) of the switch 801 via a resistor 802. This higher voltage V+ should be sufficiently higher than the biasing voltage that the bypass switch 801 remains off in normal operation for the expected operating conditions. For a typical MEMS sensor the higher voltage V+ may be of the order of 1V or so higher than the biasing voltage V.sub.BIAS. For start-up operation controller 803 responds to a start-up control SU to bring the gate voltage of the biasing bypass switch 801 down to turn the switch on and provide a bypass path for rapid charging of the MEMS sensor C.sub.MEMS.

(43) FIG. 8b illustrates an alternative example of a biasing arrangement with a bypass switch 801. In the example illustrated in FIG. 8b the gate control signal for controlling the bypass switch 801 is generated by one or more additional charge pump stages 804. The charge pump 101 may, for example, be a Dickson type charge pump and the additional charge pump stages may comprise one or additional stages of the charge pump that can be selectively activated or deactivated by the start-up control signal SU. The voltage input V1 to the additional stages may be derived from the penultimate or previous stage so that the voltage V1 input to the additional stage(s) 804 is lower than the bias voltage. In normal operation the additional stages may be activated to that the voltage supplied to the bypass switch is higher than the bias voltage V.sub.BIAS to ensure the bypass switch remains off in operation. During start-up the additional stage(s) 804 are deactivated and the lower voltage V1 is supplied to the bypass switch. It will be appreciated that although shown as two separate block in FIG. 8b for clarity the function of charge pump 101 and additional stage(s) 804 could be implemented by one charge pump with outputs from appropriate pump stages.

(44) As noted previously the derived differential signal V.sub.OUTN (or V.sub.INN) may be fed back to the biasing node of the MEMS sensor C.sub.MEMS via the biasing capacitor C.sub.BIAS. This effectively provides level shifting of the bias voltage, such that that full scale voltage variation V.sub.SIG is provided as the differential voltage. In some embodiments however the bias voltage could instead be level shifted appropriately by some suitable feedback from one of the differential signals, e.g. V.sub.OUTN (or V.sub.INN), to control the voltage source 101, for example using a charge pump.

(45) FIG. 9 illustrates a further example of amplifier arrangement that includes gain. FIG. 9 illustrates an amplifier arrangement that is similar to that illustrated in FIG. 4 which operates in generally the same way. However the arrangement of FIG. 9 includes resistors 901 which result in voltage gain being applied to the output signals. As noted previously the class AB feedback around the PMOS of LNAs 301 and 302 provide super-source-follower behaviour so that the PMOS operates at the constant current of the current source and thus a signal dependent current flows through resistors 303. The same current will flow through additional resistors 901 and thus the relevant output voltage is gained up by a factor of 1+(R.sub.901/R.sub.303) where R.sub.901 is the resistance of the resistor 901 and R.sub.303 is the resistance of the resistor 303. This allows voltage gain to be applied to the signal (assuming that there is sufficient headroom) at the front end of the MEMS amplifier arrangement, which can relax noise constraints for a subsequent stage in the signal processing path and in some instances could allow for some gain trimming, e.g. to account for part-to-part variations in sensitivity to be compensated. It will be noted that the antiphase signal applied to the biasing node via C.sub.BIAS is tapped from the source of the PMOS and thus this signal sees unity gain from the input V.sub.INN.

(46) Embodiments of the present disclosure thus provide amplifier arrangements for MEMS capacitive sensors that provide good linearity and noise performance over a relatively large operating range by deriving an antiphase signal to the received input signal and using an amplifier arrangement with differential inputs and differential outputs.

(47) Embodiments are particularly applicable to readout circuitry for MEMS capacitive transducers, and especially to MEMS microphones. However the principles may be applied to sensing signals from other transducers or other types of sensors. Embodiments may be arranged as part of an audio and/or signal processing circuit, for instance an audio circuit which may be provided in a host device. Embodiments of the invention also relate to MEMS or similar capacitive ultrasonic transducer circuits. A circuit according to an embodiment of the present invention may be implemented as an integrated circuit. A MEMS transducer may form part of the integrated circuit on a monolithic substrate or be connected to the integrated circuit in use.

(48) Embodiments may be implemented in a host device, especially a portable and/or battery powered host device such as a mobile telephone, an audio player, a video player, a PDA, a mobile computing platform such as a laptop computer or tablet and/or a games device for example.

(49) It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word comprising does not exclude the presence of elements or steps other than those listed in a claim, a or an does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. Any reference numerals or labels in the claims shall not be construed so as to limit their scope.