Embedded time of day receiver for clock transmission

Abstract

In a receiver a method for extracting first and second signals from a single signal includes receiving the single signal, generating a recovered first signal by extracting and phase locking the first signal with respect to the phase of a local clock, decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time, generating a phase difference between the first signal and the second signal as a function of data representing phase difference from a current decode frame time and data representing an encoded phase difference from an immediately prior decode frame time, subtracting the generated phase difference from the phase of the recovered first signal, and generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.

Claims

1. In a receiver receiving a single input signal that includes a first signal at a first frequency modulated by data representing an encoded phase difference between a first phase of the first signal at the first frequency and a second phase of a second signal at a second frequency, a method for extracting the first signal and the second signal from the single input signal, the method comprising: receiving the single input signal; generating a recovered first input signal from the received single input signal by extracting and phase locking the first signal with respect to the phase of a local clock internal to the receiver; decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time between the first signal and the second signal for both a current decode frame time and an immediately prior decode frame time; generating a phase difference between the first signal and the second signal as a function of decoded data representing an encoded phase difference at the start of a current decode frame time and decoded data representing an encoded phase difference at the start of an immediately prior decode frame time; subtracting the generated phase difference from the phase of the generated recovered first signal to obtain a recovered second phase of the second signal; and generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.

2. The method of claim 1 wherein phase locking the first signal with respect to the phase of the local clock internal to the receiver comprises phase locking the first signal with respect to the phase of the local clock internal to the receiver in a first digital phase locked loop.

3. The method of claim 1 wherein generating the recovered second signal by phase locking the signal at the second frequency at the recovered second phase comprises: phase locking the recovered second signal with respect to the phase of the local clock internal to the receiver in a second digital phase locked loop.

4. The method of claim 1 wherein generating the phase difference between the first signal and the second signal as the function of the decoded data representing the encoded phase difference at the start of the current decode frame time and the decoded data representing the encoded phase difference at the start of the immediately prior decode frame time comprises: extrapolating the decoded data representing the encoded phase difference at the start of the current decode frame time and the decoded data representing the encoded phase difference at the start of the immediately prior decode frame time.

5. The method of claim 1 wherein decoding over the decode frame time the data representing the encoded phase difference at the start of the decode frame time between the first signal and the second signal for both a current decode frame time and the immediately prior decode frame time comprises: delaying the decoded data for a delay time of one decode frame time.

6. The method of claim 1 wherein generating the phase difference between the first signal and the second signal as the function of the decoded data representing the encoded phase difference at the start of the current decode frame time and the decoded data representing the encoded phase difference at the start of the immediately prior decode frame time comprises: delaying the first signal by a decode frame time; subtracting the generated phase difference from the phase of the delayed first signal; and interpolating the decoded data representing an encoded phase difference at the start of the current decode frame time and the decoded data representing the encoded phase difference at the start of the immediately prior decode frame time.

7. The method of claim 1 wherein generating the phase difference between the first signal and the second signal as the function of the decoded data representing the encoded phase difference at the start of the current decode frame time and the decoded data representing the encoded phase difference at the start of the immediately prior decode frame time comprises: low-pass filtering the subtracted generated phase difference from the phase of the first signal to obtain the phase of the second signal; and linearly extrapolating the decoded data representing the encoded phase difference at the start of the current decode frame time and the decoded data representing the encoded phase difference at the start of the immediately prior decode frame time.

8. The method of claim 7 wherein low-pass filtering the subtracted generated phase difference from the phase of the first signal to obtain the phase of the second signal comprises: low-pass filtering the subtracted generated phase difference from the phase of the first signal using a multiplier-based low-pass filter.

9. The method of claim 7 wherein low-pass filtering the subtracted generated phase difference from the phase of the first signal to obtain the phase of the second signal comprises: low-pass filtering the subtracted generated phase difference from the phase of the first signal using an adder and shifter based low-pass filter.

10. A receiver for extracting a first signal and a second signal from a single input signal, comprising: a phase acquisition unit and a first phase locked loop circuit coupled to an input of the receiver for extracting and phase locking from the single signal the first signal with respect to the phase of a local clock internal to the receiver; a phase decoder for decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time between the first signal and the second signal for both a current decode frame time and an immediately prior decode frame time; a circuit coupled to the phase acquisition unit and the phase decoder for generating a phase difference between the first signal and the second signal as a function of decoded data representing an encoded phase difference at the start of a current decode frame time and decoded data representing an encoded phase difference at the start of an immediately prior decode frame time; a subtractor circuit, coupled to the phase acquisition unit and the circuit for generating the phase difference, for subtracting the generated phase difference from the phase of the recovered first signal to obtain a recovered second phase of the second signal; and a second phase locked loop circuit for generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.

11. The receiver of claim 10 wherein the first phase locked loop circuit comprises a digital phase locked loop locked to the first signal.

12. The receiver of claim 10 wherein the second phase locked loop circuit for generating the recovered second signal by phase locking the signal at the second frequency at the recovered second phase is a digital phase locked loop locked to the second signal.

13. The receiver of claim 10 wherein the decoder comprises a delay circuit having a delay time of one decode frame time.

14. The receiver of claim 10 wherein the circuit coupled to the phase acquisition unit and the decoder for generating the phase difference between the first signal and the second signal as the function of decoded data representing the encoded phase difference at the start of a current decode frame time and decoded data representing the encoded phase difference at the start of the immediately prior decode frame time comprises an extrapolator circuit.

15. The receiver of claim 10 wherein; the first phase locked loop circuit comprises a digital phase locked loop locked to the first signal through a first signal delay circuit; the circuit coupled to the phase acquisition unit and the decoder for generating the phase difference between the first signal and the second signal as the function of decoded data representing the encoded phase difference at the start of the current decode frame time and decoded data representing the encoded phase difference at the start of the immediately prior decode frame time comprises an interpolator circuit; and the subtractor circuit is coupled to the phase acquisition unit through the first signal delay circuit.

16. The receiver of claim 10 wherein the circuit coupled to the phase acquisition unit and the decoder for generating the phase difference between the first signal and the second signal as the function of decoded data representing the encoded phase difference at the start of the current decode frame time and decoded data representing the encoded phase difference at the start of an immediately prior decode frame time comprises a linear extrapolator circuit.

17. The receiver of claim 16 wherein: the linear extrapolator circuit is directly coupled to the decoder; and the linear extrapolator circuit is further coupled to the decoder through: a delay circuit having an output; a subtractor circuit subtracting the output of the delay circuit from the output of the decoder circuit; and a low pass filter coupled between the subtractor circuit and the linear extrapolator.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The invention will be explained in more detail in the following with reference to embodiments and to the drawing in which are shown:

(2) FIG. 1 is a block diagram of an embedded time of day (eTod) transmitter and receiver;

(3) FIG. 2 is a block diagram showing a portion of an eTod receiver in accordance with an aspect of the present invention using extrapolation for phase adjustment;

(4) FIG. 3 is a block diagram showing a portion of an eTod receiver in accordance with an aspect of the present invention using interpolation for phase adjustment;

(5) FIG. 4 is a block diagram showing a portion of an eTod receiver in accordance with an aspect of the present invention using extrapolation with filtering for phase adjustment;

(6) FIG. 5 is a block diagram showing a simple filter implementation that may be employed in an eTod receiver in accordance with the present invention;

(7) FIG. 6 is a block diagram showing a multiplierless filter implementation that may be employed in an eTod receiver in accordance with the present invention; and

(8) FIG. 7 is a flow diagram illustrating a method for extracting the first signal and the second signal from the single input signal in accordance with an aspect of the invention.

DETAILED DESCRIPTION

(9) Persons of ordinary skill in the art will realize that the following description is illustrative only and not in any way limiting. Other embodiments will readily suggest themselves to such skilled persons.

(10) Such skilled persons will also appreciate that the present invention may be implemented for any eTod-like encode, decode, and modulating scheme using, for example, direct modulation or delta modulation.

(11) In accordance with aspects of the present invention, the relative phase between a first clock reference signal ref1 and a second clock reference signal ref2 presented to the input of a transmitter is replicated at the output of a receiver coupled to the transmitter. Several techniques are presented for addressing the delay problem presented in the prior art without causing extra wander and noise for the second DPLL2 output.

(12) Referring now to FIG. 2, a block diagram of a receiver 70 for performing an extrapolation method for phase adjustment in the receiver is shown. The components of the receiver 70 of FIG. 2 that are the same as the components of the receiver 30 of FIG. 1 will be identified using the same reference numerals that are used to identify these components in FIG. 1. The receiver 70 receives the ref(encoded) signal on line 32 and presents it to both the PA 34 and the demodulator 44. The demodulated value at the output of the demodulator 44 drives the phase decoder 46. The output of the phase decoder 46 is the phase adjustment value for the current decode frame starting time.

(13) FIG. 2 shows a first approach for the alignment of phase adjustment and PA reference clock phase. As in the receiver section depicted in FIG. 1, the phase decoder 46 will decode the phase adjustment value for the current decode frame starting time. At time t.sub.0, the phase decoder 46 provides the decoded phase adjustment value (P.sub.0) for the current decode frame that was sent by the transmitter 10. The delay 72 introduces one decode frame delay period and provides the decoded phase adjustment value (P.sub.1) for the previous decode frame. PA 34 provides the reference phase information for the signal ref1 at the sample time of the receiver local clock which is time t.sub.0. The decode frame starting time t.sub.0T.sub.d as well as the identifier of time t.sub.0 is known to and provided by the receiver 70.

(14) At time t.sub.0, the phase decoder 46 provides decoded phase adjustment value (P.sub.0) at decode frame starting time t.sub.0T.sub.d. The delay 72 provides the phase adjustment value (P.sub.1) which is the phase adjustment value that was decoded at the previous decode frame starting time t.sub.0T.sub.dT, where T is the decode frame period.

(15) The extrapolation is performed in extrapolator 74. Extrapolator 74 has an input taken from PA 34 which provides the time information t.sub.0 and t.sub.0T.sub.d from which T.sub.d is extracted. The extrapolator 74 also has inputs taken from phase decoder 46 (P.sub.0) and delay 72 (P.sub.1). The extrapolator 74 provides the adjustment phase P.sub. at time t.sub.0 as:

(16) $P_{}=P_0+\frac{P_0-P_{-1}}{T}{T}_d$

(17) Thus, extrapolator 74 is an embodiment of a circuit for generating a phase difference between the first signal and the second signal as a function of decoded data representing an encoded phase difference at the start of a current decode frame time and decoded data representing an encoded phase difference at the start of an immediately prior decode frame time. The adjusted phase P.sub. is subtracted from the reference phase provided by PA 34 in subtractor circuit 48 to provide an equivalent phase for clock reference signal ref2 to which the second DPLL2 50 will lock.

(18) If the clock reference signals ref2 and ref1 have a constant phase offset, P.sub.0P.sub.1 will be constant and this method provides a simple way for correct phase adjustment at time t.sub.0. However, if either clock reference signal ref1 or clock reference signal ref2 has noise or wander in it, the noise or wander will be increased due to the extrapolation.

(19) From the sampling theorem, it is known that since phase adjustment is done every T (seconds) and the maximum DPLL sampling rate is 1/T, the maximum noise bandwidth or the highest wander frequency has to be smaller than the Nyquist rate 1/(2T) in order to ensure that the output clock is locked to the reference clock.

(20) For the worst case, when T.sub.d is close to T and the frequency of noise or wander is close to 1/(2T), the magnitude of the noise or wander for the output clock is twice the magnitude of the noise or wander for the reference clock.

(21) Referring now to FIG. 3, a receiver 90 is shown that performs an interpolation method for phase adjustment.

(22) The circuit of FIG. 3 has some function blocks that are the same as those of the circuit of FIG. 2 that are identified using the same reference numerals used in FIG. 2. In the circuit 90 of FIG. 3, the reference clock phase derived from the ref(encoded) signal at the receiver input 32 is delayed in delay 92 by one decode frame cycle before being sent to the first DPLL1 38 so that the interpolation method can be used.

(23) At time t.sub.0, the input to the second DPLL2 50 is the difference between the reference phase output of PA 34 at time t.sub.0T and the modified phase adjustment value provided by the interpolator 94. The phase decoder 46 provides the decoded phase adjustment value (P.sub.0) at decode frame starting time t.sub.0T.sub.d. The delay 72 provides the phase adjustment value (P.sub.1) at the previous decode frame starting time t.sub.0T.sub.dT. Since T>T.sub.d, the adjustment phase P.sub. at time t.sub.0T needs to be obtained, which is between P.sub.0 and P.sub.1. Using linear interpolation performed in interpolator 94:

(24) $P_{}=P_{-1}+\frac{P_0-P_{-1}}{T}{T}_d$

(25) Thus, interpolator 94 is an embodiment of a circuit for generating a phase difference between the first signal and the second signal as a function of decoded data representing an encoded phase difference at the start of a current decode frame time and decoded data representing an encoded phase difference at the start of an immediately prior decode frame time. The subtractor circuit 48 provides phase of the clock reference signal ref2 by subtracting the interpolated phase difference from interpolator 94 from the signal output of PA 34 delayed by delay circuit 92.

(26) The approach shown in FIG. 3 will provide accurate phase adjustment value at the right time without increasing wander and noise in the reference clocks. One drawback of the approach of FIG. 3 is that the extra delay from delay circuit 92 in the reference path may cause clock misalignment. In many applications, it is required that the delay in the transmitter and receiver path be minimized. Also, the delay may impact DPLL loop behavior in the system.

(27) Referring now to FIG. 4, receiver 100 is shown that includes circuitry for performing an extrapolation method with filtering for phase adjustment. The approach of FIG. 4 is linear extrapolation combined with low-pass filtering.

(28) In the circuit 100 of FIG. 4, the linear extrapolator 102 takes the current decoded phase adjustment value from phase decoder 46 as the initial value (P.sub.0) and a filtered phase adjustment difference () obtained as the difference between the output of the phase decoder 46 and the delay 72 from subtractor 104 between two adjacent decode frames as a slope value, after being filtered by low pass filter 106. The decoded phase adjustment value output by phase decoder 46 is the phase difference between the clock reference signals ref1 and ref2, which includes the offset between the two clock reference signals ref1 and ref2 and noise (or wander), since the clock reference signals ref1 and ref2 have a constant frequency offset. The difference between two adjacent phase adjustment values corresponds to the phase difference between the two clock reference signals ref1 and ref2 in one decode frame cycle, which because of the constant frequency offset is a constant value in the absence of noise. The low pass filter 104 cleans the noise and outputs the filtered phase adjustment difference () in one decode frame cycle.

(29) At time t.sub.0, with current decoded phase adjustment value (P.sub.0) representing the phase adjustment at time (t.sub.0T.sub.d) and the delayed phase adjustment value (P.sub.1) representing the phase adjustment at time (t.sub.0T.sub.dT), the linearly extrapolated phase adjustment at time t.sub.0 is calculated by linear extrapolator 102 as:
P.sub.=P.sub.0+T.sub.d

(30) where is the filtered offset P.sub.0P.sub.1. Thus, linear extrapolator 102 is an embodiment of a circuit for generating a phase difference between the first signal and the second signal as a function of decoded data representing an encoded phase difference at the start of a current decode frame time and decoded data representing an encoded phase difference at the start of an immediately prior decode frame time. With the approach shown in FIG. 4, only the stable frequency offset between the clock reference signals ref1 and ref2 provided by the low pass filter 106 is used for extrapolation to obtain the correct phase adjustment at time t.sub.0. From the above equation it can be observed that the noise (or wander) at P will be the same as the noise (or wander) at P.sub.0 received (decoded) at time t.sub.0T.sub.d (the decode frame starting time) since the noise on has been filtered.

(31) Referring now to FIG. 5, a diagram shows a low-pass filter circuit 110 implemented with filter coefficient which is suitable for use as low-pass filter 106. The input IN(x) 112 is added in adder 114 with the constant provided at input 116 and multiplied in multiplier 118 by the output of Z.sup.1 digital filter delay circuit 120, where Z.sup.1 is the unit delay for the digital filter with a delay time the same as the sample period. The output of Z.sup.1 circuit 120 is multiplied by the constant 1 in multiplier 122 to produce the low-pass filtered output at reference numeral 124 to be provided to linear extrapolation circuit 102.

(32) The filter response between the filter input(x) and output(y) is:

(33) $\frac{1-}{1-Z^{-1}}$

(34) The low-pass filter circuit 110 filters out the high frequency wander and noise. For the low frequency wander and noise, the extrapolation would not create too much error. One suitable choice for the filter coefficient is = 1/64.

(35) Referring now to FIG. 6, a multiplierless filter circuit 130 is shown which is suitable for use as low-pass filter 106. The filter circuit 130 of FIG. 6 is implemented using addition and shift operations in place of multiplication. Thus, shift right 6 bits shifter 138 is used in the filter 130 of FIG. 6 in place of multiplier 118 in the filter 110 of FIG. 6. Shift right 6 bits shifter 140 in combination with adder 142 is used in the filter 130 of FIG. 6 in place of multiplier 122 in the filter 110 of FIG. 5.

(36) Referring now to FIG. 7, a flow diagram shows an illustrative method 150 for extracting the first signal and the second signal from the single input signal in accordance with an aspect of the invention. The method begins at reference numeral 152.

(37) At reference numeral 154, the input signal is received. At reference numeral 156, the recovered first input signal is generated by extracting and phase locking the first signal to the local clock.

(38) At reference numeral 158, the data representing an encoded phase difference at the start of the decode frame time between the first signal and the second signal is decoded for both a current decode frame time and an immediately prior decode frame time.

(39) At reference numeral 160, a phase difference between the first signal and the second signal is generated as a function of decoded data representing an encoded phase difference at the start of a current decode frame time and decoded data representing an encoded phase difference at the start of an immediately prior decode frame time.

(40) At reference numeral 162, the generated phase difference is subtracted from the phase of the generated recovered first signal to obtain a recovered second phase of the second signal.

(41) At reference numeral 164, a recovered second signal is generated by phase locking a signal at the second frequency at the recovered second phase. The method ends at reference numeral 166.

(42) The present invention provides a system having a receiver for transmission of two clock signals using a single transmission line. The present invention is well suited for embedded time-of-day (eTod) receiver design. Extrapolation or interpolation are used to provide decoded phase adjustment to improve DPLL loop stability. The use of extrapolation in combination with a low-pass filter can improve DPLL loop stability without increasing output clock wander and noise.

(43) While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.